227 lines
13 KiB
VHDL
227 lines
13 KiB
VHDL
--
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-- fdunit.vhd
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--
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-- Floppy Disk Drive Unit Emulation module
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-- for MZ-80B/2000 on FPGA
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--
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-- Nibbles Lab. 2014
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity fdunit is
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Port (
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RST_n : in std_logic; -- Reset
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CLK : in std_logic; -- System Clock
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-- Interrupt
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INTO : out std_logic; -- Step Pulse interrupt
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-- FD signals
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FCLK : in std_logic;
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DS_n : in std_logic_vector(4 downto 1); -- Drive Select
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HS : in std_logic; -- Head Select
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MOTOR_n : in std_logic; -- Motor On
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INDEX_n : out std_logic; -- Index Hole Detect
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TRACK00 : out std_logic; -- Track 0
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WPRT_n : out std_logic; -- Write Protect
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STEP_n : in std_logic; -- Head Step In/Out
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DIREC : in std_logic; -- Head Step Direction
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WG_n : in std_logic; -- Write Gate
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DTCLK : out std_logic; -- Data Clock
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FDI : in std_logic_vector(7 downto 0); -- Write Data
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FDO : out std_logic_vector(7 downto 0); -- Read Data
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-- Buffer RAM I/F
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BCS_n : out std_logic; -- RAM Request
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BADR : out std_logic_vector(22 downto 0); -- RAM Address
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BWR_n : out std_logic; -- RAM Write Signal
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BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
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BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
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);
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end fdunit;
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architecture RTL of fdunit is
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--
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-- Floppy Signals
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--
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signal RDO0 : std_logic_vector(7 downto 0);
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signal RDO1 : std_logic_vector(7 downto 0);
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signal IDX_0 : std_logic;
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signal IDX_1 : std_logic;
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signal TRK00_0 : std_logic;
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signal TRK00_1 : std_logic;
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signal WPRT_0 : std_logic;
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signal WPRT_1 : std_logic;
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signal FDO0 : std_logic_vector(7 downto 0);
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signal FDO1 : std_logic_vector(7 downto 0);
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signal DTCLK0 : std_logic;
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signal DTCLK1 : std_logic;
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--
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-- Control
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--
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signal INT0 : std_logic;
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signal INT1 : std_logic;
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--
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-- Memory Access
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--
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signal BCS0_n : std_logic;
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signal BCS1_n : std_logic;
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signal BADR0 : std_logic_vector(22 downto 0);
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signal BADR1 : std_logic_vector(22 downto 0);
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signal BWR0_n : std_logic;
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signal BWR1_n : std_logic;
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signal BDO0 : std_logic_vector(7 downto 0);
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signal BDO1 : std_logic_vector(7 downto 0);
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--
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-- Component
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--
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component fd55b
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generic
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(
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DS_SW : std_logic_vector(4 downto 1) := "1111";
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REG_ADDR : std_logic_vector(15 downto 0) := "0000000000000000"
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);
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Port (
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RST_n : in std_logic; -- Reset
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CLK : in std_logic; -- System Clock
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-- Interrupt
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INTO : out std_logic; -- Step Pulse interrupt
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-- FD signals
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FCLK : in std_logic;
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DS_n : in std_logic_vector(4 downto 1); -- Drive Select
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HS : in std_logic; -- Head Select
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MOTOR_n : in std_logic; -- Motor On
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INDEX_n : out std_logic; -- Index Hole Detect
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TRACK00 : out std_logic; -- Track 0
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WPRT_n : out std_logic; -- Write Protect
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STEP_n : in std_logic; -- Head Step In/Out
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DIREC : in std_logic; -- Head Step Direction
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WG_n : in std_logic; -- Write Gate
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DTCLK : out std_logic; -- Data Clock
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FDI : in std_logic_vector(7 downto 0); -- Write Data
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FDO : out std_logic_vector(7 downto 0); -- Read Data
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-- Buffer RAM I/F
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BCS_n : out std_logic; -- RAM Request
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BADR : out std_logic_vector(22 downto 0); -- RAM Address
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BWR_n : out std_logic; -- RAM Write Signal
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BDI : in std_logic_vector(7 downto 0); -- Data Bus Input from RAM
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BDO : out std_logic_vector(7 downto 0) -- Data Bus Output to RAM
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-- HPS Interface
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IOCTL_DOWNLOAD : in std_logic; -- HPS Downloading to FPGA.
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IOCTL_INDEX : in std_logic_vector(7 downto 0); -- Menu index used to upload file.
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IOCTL_WR : in std_logic; -- HPS Write Enable to FPGA.
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IOCTL_RD : in std_logic; -- HPS Read Enable from FPGA.
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IOCTL_ADDR : in std_logic_vector(24 downto 0); -- HPS Address in FPGA to write into.
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IOCTL_DOUT : in std_logic_vector(15 downto 0); -- HPS Data to be written into FPGA.
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IOCTL_DIN : out std_logic_vector(15 downto 0); -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT : out std_logic -- HPS Interrupt.
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);
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end component;
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begin
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FDD0 : fd55b generic map (
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DS_SW => "1110",
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REG_ADDR => X"0040"
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)
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Port map (
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RST_n => RST_n, -- Reset
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CLK => CLK, -- System Clock
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-- Interrupt
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INTO => INT0, -- Step Pulse interrupt
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-- FD signals
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FCLK => FCLK,
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DS_n => DS_n, -- Drive Select
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HS => HS, -- Head Select
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MOTOR_n => MOTOR_n, -- Motor On
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INDEX_n => IDX_0, -- Index Hole Detect
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TRACK00 => TRK00_0, -- Track 0
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WPRT_n => WPRT_0, -- Write Protect
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STEP_n => STEP_n, -- Head Step In/Out
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DIREC => DIREC, -- Head Step Direction
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WG_n => WG_n, -- Write Gate
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DTCLK => DTCLK0, -- Data Clock
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FDI => FDI, -- Write Data
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FDO => FDO0, -- Read Data
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-- Buffer RAM I/F
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BCS_n => BCS0_n, -- RAM Request
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BADR => BADR0, -- RAM Address
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BWR_n => BWR0_n, -- RAM Write Signal
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BDI => BDI, -- Data Bus Input from RAM
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BDO => BDO0 -- Data Bus Output to RAM
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-- HPS Interface
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IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
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IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
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IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
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IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
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IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
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IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
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IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
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);
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FDD1 : fd55b generic map (
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DS_SW => "1101",
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REG_ADDR => X"0050"
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)
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Port map (
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RST_n => RST_n, -- Reset
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CLK => CLK, -- System Clock
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-- Interrupt
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INTO => INT1, -- Step Pulse interrupt
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-- FD signals
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FCLK => FCLK,
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DS_n => DS_n, -- Drive Select
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HS => HS, -- Head Select
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MOTOR_n => MOTOR_n, -- Motor On
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INDEX_n => IDX_1, -- Index Hole Detect
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TRACK00 => TRK00_1, -- Track 0
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WPRT_n => WPRT_1, -- Write Protect
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STEP_n => STEP_n, -- Head Step In/Out
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DIREC => DIREC, -- Head Step Direction
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WG_n => WG_n, -- Write Gate
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DTCLK => DTCLK1, -- Data Clock
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FDI => FDI, -- Write Data
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FDO => FDO1, -- Read Data
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-- Buffer RAM I/F
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BCS_n => BCS1_n, -- RAM Request
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BADR => BADR1, -- RAM Address
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BWR_n => BWR1_n, -- RAM Write Signal
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BDI => BDI, -- Data Bus Input from RAM
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BDO => BDO1 -- Data Bus Output to RAM
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-- HPS Interface
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IOCTL_DOWNLOAD => IOCTL_DOWNLOAD, -- HPS Downloading to FPGA.
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IOCTL_INDEX => IOCTL_INDEX, -- Menu index used to upload file.
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IOCTL_WR => IOCTL_WR, -- HPS Write Enable to FPGA.
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IOCTL_RD => IOCTL_RD, -- HPS Read Enable from FPGA.
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IOCTL_ADDR => IOCTL_ADDR, -- HPS Address in FPGA to write into.
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IOCTL_DOUT => IOCTL_DOUT, -- HPS Data to be written into FPGA.
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IOCTL_DIN => IOCTL_DIN, -- HPS Data to be read into HPS.
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IOCTL_INTERRUPT => IOCTL_INTERRUPT -- HPS Interrupt.
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);
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INDEX_n <= IDX_0 and IDX_1;
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TRACK00 <= TRK00_0 and TRK00_1;
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WPRT_n <= WPRT_0 and WPRT_1;
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FDO <= FDO0 or FDO1;
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DTCLK <= DTCLK0 or DTCLK1;
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BCS_n <= BCS0_n and BCS1_n;
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BADR <= BADR0 or BADR1;
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BWR_n <= BWR0_n and BWR1_n;
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BDO <= BDO0 or BDO1;
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RDO <= RDO0 or RDO1;
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INTO <= INT0 or INT1;
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end RTL;
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