Tidied up
This commit is contained in:
Philip Smart
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
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||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "5.0"
|
||||
DATE = "23:35:58 September 01, 2005"
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||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "CYC1000_zpu"
|
||||
@@ -1,421 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
|
||||
# Date created = 11:51:50 November 03, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# cyc1000_nios_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
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||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:50 NOVEMBER 03, 2017"
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||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone 10 LP"
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||||
set_global_assignment -name TOP_LEVEL_ENTITY CYC1000_zpu
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||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE 10CL025YU256C8G
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "COMPILER CONFIGURED"
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
#============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_F13 -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
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||||
set_location_assignment PIN_F15 -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_location_assignment PIN_D15 -to UART_RX_1
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
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||||
set_location_assignment PIN_C15 -to UART_TX_1
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# SD CARD
|
||||
#============================================================
|
||||
set_location_assignment PIN_F16 -to SDCARD_MISO[0]
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||||
set_location_assignment PIN_D16 -to SDCARD_MOSI[0]
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||||
set_location_assignment PIN_B16 -to SDCARD_CLK[0]
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||||
set_location_assignment PIN_C16 -to SDCARD_CS[0]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_M2 -to CLOCK_12M
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_12M
|
||||
set_location_assignment PIN_E15 -to CLK_X
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_X
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_location_assignment PIN_N3 -to LED[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_location_assignment PIN_N5 -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_location_assignment PIN_R4 -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_location_assignment PIN_T2 -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_location_assignment PIN_R3 -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_location_assignment PIN_T3 -to LED[2]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_location_assignment PIN_T4 -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_location_assignment PIN_M6 -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
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||||
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||||
#============================================================
|
||||
# SDRAM
|
||||
#============================================================
|
||||
# Data bus
|
||||
set_location_assignment PIN_B10 -to SDRAM_DQ[0]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
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||||
set_location_assignment PIN_A10 -to SDRAM_DQ[1]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_B11 -to SDRAM_DQ[2]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
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||||
set_location_assignment PIN_A11 -to SDRAM_DQ[3]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
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||||
set_location_assignment PIN_A12 -to SDRAM_DQ[4]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
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||||
set_location_assignment PIN_D9 -to SDRAM_DQ[5]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
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||||
set_location_assignment PIN_B12 -to SDRAM_DQ[6]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_C9 -to SDRAM_DQ[7]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
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||||
set_location_assignment PIN_D11 -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_E11 -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_A15 -to SDRAM_DQ[10]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
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||||
set_location_assignment PIN_E9 -to SDRAM_DQ[11]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
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||||
set_location_assignment PIN_D14 -to SDRAM_DQ[12]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_F9 -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
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||||
set_location_assignment PIN_C14 -to SDRAM_DQ[14]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
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||||
set_location_assignment PIN_A14 -to SDRAM_DQ[15]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
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||||
# Address Bus
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||||
set_location_assignment PIN_A3 -to SDRAM_ADDR[0]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
|
||||
set_location_assignment PIN_B5 -to SDRAM_ADDR[1]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
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||||
set_location_assignment PIN_B4 -to SDRAM_ADDR[2]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
|
||||
set_location_assignment PIN_B3 -to SDRAM_ADDR[3]
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||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
|
||||
set_location_assignment PIN_C3 -to SDRAM_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
|
||||
set_location_assignment PIN_D3 -to SDRAM_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
|
||||
set_location_assignment PIN_E6 -to SDRAM_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
|
||||
set_location_assignment PIN_E7 -to SDRAM_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
|
||||
set_location_assignment PIN_D6 -to SDRAM_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
|
||||
set_location_assignment PIN_D8 -to SDRAM_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
|
||||
set_location_assignment PIN_A5 -to SDRAM_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
|
||||
set_location_assignment PIN_E8 -to SDRAM_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
|
||||
set_location_assignment PIN_A2 -to SDRAM_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
|
||||
set_location_assignment PIN_C6 -to SDRAM_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13]
|
||||
# Byte addressing
|
||||
set_location_assignment PIN_A4 -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_B6 -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_B13 -to SDRAM_DQM[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
|
||||
set_location_assignment PIN_D12 -to SDRAM_DQM[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
|
||||
# Chip control.
|
||||
set_location_assignment PIN_C8 -to SDRAM_CAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS
|
||||
set_location_assignment PIN_B7 -to SDRAM_RAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS
|
||||
set_location_assignment PIN_A7 -to SDRAM_WE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE
|
||||
set_location_assignment PIN_A6 -to SDRAM_CS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
|
||||
# Clock and enabling.
|
||||
set_location_assignment PIN_F8 -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_location_assignment PIN_B14 -to SDRAM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
|
||||
#============================================================
|
||||
# FT2232H
|
||||
#============================================================
|
||||
# ADBUS
|
||||
set_location_assignment PIN_H3 -to ADBUS_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_0
|
||||
set_location_assignment PIN_H4 -to ADBUS_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_1
|
||||
set_location_assignment PIN_J4 -to ADBUS_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_2
|
||||
set_location_assignment PIN_J5 -to ADBUS_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_3
|
||||
set_location_assignment PIN_M8 -to ADBUS_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_4
|
||||
set_location_assignment PIN_N8 -to ADBUS_7
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_7
|
||||
# BDBUS
|
||||
set_location_assignment PIN_R7 -to BDBUS[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[0]
|
||||
set_location_assignment PIN_T7 -to BDBUS[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[1]
|
||||
set_location_assignment PIN_R6 -to BDBUS[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[2]
|
||||
set_location_assignment PIN_T6 -to BDBUS[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[3]
|
||||
set_location_assignment PIN_R5 -to BDBUS[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[4]
|
||||
set_location_assignment PIN_T5 -to BDBUS[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[5]
|
||||
|
||||
#============================================================
|
||||
# Serial Configuration Memory
|
||||
#============================================================
|
||||
set_location_assignment PIN_H2 -to AS_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DATA0
|
||||
set_location_assignment PIN_C1 -to AS_ASDO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_ASDO
|
||||
set_location_assignment PIN_D2 -to AS_NCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_NCS
|
||||
set_location_assignment PIN_H1 -to AS_DCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DCLK
|
||||
|
||||
#============================================================
|
||||
# PMOD IO Header PIO0 - PIO7
|
||||
#============================================================
|
||||
#set_location_assignment PIN_F13 -to PIO[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[1]
|
||||
#set_location_assignment PIN_F15 -to PIO[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[2]
|
||||
#set_location_assignment PIN_F16 -to PIO[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[3]
|
||||
#set_location_assignment PIN_D16 -to PIO[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[4]
|
||||
#set_location_assignment PIN_D15 -to PIO[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[5]
|
||||
#set_location_assignment PIN_C15 -to PIO[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[6]
|
||||
#set_location_assignment PIN_B16 -to PIO[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[7]
|
||||
#set_location_assignment PIN_C16 -to PIO[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[8]
|
||||
|
||||
#============================================================
|
||||
# GPIO14 - GPIO22 Header
|
||||
#============================================================
|
||||
set_location_assignment PIN_N2 -to GPIO[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
|
||||
set_location_assignment PIN_N1 -to GPIO[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
|
||||
set_location_assignment PIN_P2 -to GPIO[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
|
||||
set_location_assignment PIN_J1 -to GPIO[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
|
||||
set_location_assignment PIN_J2 -to GPIO[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
|
||||
set_location_assignment PIN_K2 -to GPIO[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
|
||||
set_location_assignment PIN_L2 -to GPIO[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
|
||||
set_location_assignment PIN_P1 -to GPIO[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
|
||||
set_location_assignment PIN_R1 -to GPIO[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
|
||||
|
||||
#============================================================
|
||||
# GPIO8 - GPIO13 Header
|
||||
#============================================================
|
||||
set_location_assignment PIN_N16 -to GPIO[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
|
||||
set_location_assignment PIN_L15 -to GPIO[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
|
||||
set_location_assignment PIN_L16 -to GPIO[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
|
||||
set_location_assignment PIN_K15 -to GPIO[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
|
||||
set_location_assignment PIN_K16 -to GPIO[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
|
||||
set_location_assignment PIN_J14 -to GPIO[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
|
||||
set_location_assignment PIN_K1 -to D11_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D11_R
|
||||
set_location_assignment PIN_L1 -to D12_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D12_R
|
||||
|
||||
#============================================================
|
||||
# GPIO0 - GPIO7 Header
|
||||
#============================================================
|
||||
set_location_assignment PIN_T12 -to AIN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AIN
|
||||
set_location_assignment PIN_P11 -to AREF
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AREF
|
||||
set_location_assignment PIN_R12 -to GPIO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
|
||||
set_location_assignment PIN_T13 -to GPIO[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
|
||||
set_location_assignment PIN_R13 -to GPIO[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
|
||||
set_location_assignment PIN_T14 -to GPIO[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
|
||||
set_location_assignment PIN_P14 -to GPIO[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
|
||||
set_location_assignment PIN_R14 -to GPIO[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
|
||||
set_location_assignment PIN_T15 -to GPIO[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
|
||||
set_location_assignment PIN_R11 -to GPIO[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
|
||||
|
||||
#============================================================
|
||||
# Buttons
|
||||
#============================================================
|
||||
set_location_assignment PIN_N6 -to USER_BTN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_BTN
|
||||
|
||||
#============================================================
|
||||
# 3-Axis Accelerometer
|
||||
#============================================================
|
||||
set_location_assignment PIN_D1 -to SEN_CS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_CS
|
||||
set_location_assignment PIN_B1 -to SEN_INT1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT1
|
||||
set_location_assignment PIN_C2 -to SEN_INT2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT2
|
||||
set_location_assignment PIN_G2 -to SEN_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDI
|
||||
set_location_assignment PIN_G1 -to SEN_SDO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDO
|
||||
set_location_assignment PIN_F3 -to SEN_SPC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SPC
|
||||
|
||||
#============================================================
|
||||
# Modules and Files
|
||||
#============================================================
|
||||
#
|
||||
set_global_assignment -name VHDL_FILE ../CYC1000_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_12to100.qip
|
||||
set_global_assignment -name SDC_FILE CYC1000_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
|
||||
set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,176 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity CYC1000_zpu is
|
||||
port (
|
||||
-- Clock
|
||||
CLOCK_12M : in std_logic;
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
-- Debounced keys
|
||||
-- KEY : in std_logic_vector(1 downto 0);
|
||||
-- DIP switches
|
||||
-- SW : in std_logic_vector(3 downto 0);
|
||||
USER_BTN : in std_logic;
|
||||
|
||||
-- TDI : in std_logic;
|
||||
-- TCK : in std_logic;
|
||||
-- TCS : in std_logic;
|
||||
-- TDO : out std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic;
|
||||
UART_RX_1 : in std_logic;
|
||||
UART_TX_1 : out std_logic;
|
||||
|
||||
-- SDRAM signals
|
||||
SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE : out std_logic; -- clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
|
||||
SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
|
||||
SDRAM_CS : out std_logic; -- a single chip select
|
||||
SDRAM_WE : out std_logic; -- write enable
|
||||
SDRAM_RAS : out std_logic; -- row address select
|
||||
SDRAM_CAS : out std_logic -- columns address select
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of CYC1000_zpu is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
LED <= "00000000";
|
||||
|
||||
mypll : entity work.Clock_12to100
|
||||
port map
|
||||
(
|
||||
inclk0 => CLOCK_12M,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
--reset<=(not SW(0) xor KEY(0)) and pll_locked;
|
||||
reset<=(not USER_BTN) and pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_CYC1000_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => UART_RX_1,
|
||||
UART_TX_1 => UART_TX_1,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => open,
|
||||
SPI_CLK => open,
|
||||
SPI_CS => open,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals
|
||||
SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open -- sd ready.
|
||||
|
||||
-- DDR2 DRAM - doesnt exist on the QMV.
|
||||
--DDR2_ADDR => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ => open, -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS => open, -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM => open, -- eight byte masks
|
||||
--DDR2_ODT => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_BA => open, -- 8 banks
|
||||
--DDR2_CS => open, -- 2 chip selects.
|
||||
--DDR2_WE => open, -- write enable
|
||||
--DDR2_RAS => open, -- row address select
|
||||
--DDR2_CAS => open, -- columns address select
|
||||
--DDR2_CKE => open, -- 2 clock enable.
|
||||
--DDR2_CLK => open -- 2 clocks.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,135 +0,0 @@
|
||||
## Generated SDC file "E115_zpu.out.sdc"
|
||||
|
||||
## Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
## Your use of Intel Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Intel Program License
|
||||
## Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
## the Intel FPGA IP License Agreement, or other applicable license
|
||||
## agreement, including, without limitation, that your use is for
|
||||
## the sole purpose of programming logic devices manufactured by
|
||||
## Intel and sold by Intel or its authorized distributors. Please
|
||||
## refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus Prime"
|
||||
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
|
||||
|
||||
## DATE "Sat Jun 22 23:32:00 2019"
|
||||
|
||||
##
|
||||
## DEVICE "EP4CE115F23I7"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
|
||||
#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
derive_clock_uncertainty
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {USER_BTN*}]
|
||||
#set_false_path -from [get_keepers {SW*}]
|
||||
#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -1,25 +0,0 @@
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component Clock_12to100
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
@@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone II" variation_name="Clock_12to100" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,5 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_12to100.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.ppf"]
|
||||
@@ -1,397 +0,0 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: Clock_12to100.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY Clock_12to100 IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END Clock_12to100;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF clock_12to100 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
gate_lock_signal : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
invalid_lock_multiplier : NATURAL;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
valid_lock_multiplier : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire6_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
sub_wire4 <= inclk0;
|
||||
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
clk0_divide_by => 3,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 25,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 3,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 50,
|
||||
clk1_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
gate_lock_signal => "NO",
|
||||
inclk0_input_frequency => 83333,
|
||||
intended_device_family => "Cyclone II",
|
||||
invalid_lock_multiplier => 5,
|
||||
lpm_hint => "CBX_MODULE_PREFIX=Clock_12to100",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_UNUSED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
valid_lock_multiplier => 1
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire5,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_12to100.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,25 +0,0 @@
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component Clock_25to100
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
@@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone II" variation_name="Clock_25to100" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,5 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_25to100.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.ppf"]
|
||||
@@ -1,397 +0,0 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: Clock_25to100.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY Clock_25to100 IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END Clock_25to100;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF clock_25to100 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
gate_lock_signal : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
invalid_lock_multiplier : NATURAL;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
valid_lock_multiplier : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire6_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
sub_wire4 <= inclk0;
|
||||
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
clk0_divide_by => 1,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 4,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 1,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 8,
|
||||
clk1_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
gate_lock_signal => "NO",
|
||||
inclk0_input_frequency => 40000,
|
||||
intended_device_family => "Cyclone II",
|
||||
invalid_lock_multiplier => 5,
|
||||
lpm_hint => "CBX_MODULE_PREFIX=Clock_25to100",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_UNUSED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
valid_lock_multiplier => 1
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire5,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_25to100.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,25 +0,0 @@
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component Clock_50to100
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
@@ -1,209 +0,0 @@
|
||||
VERSION: WM1.0
|
||||
MODULE: altpll
|
||||
PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
PRIVATE: BANDWIDTH STRING "1.000"
|
||||
PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||||
PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
|
||||
PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
|
||||
PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
|
||||
PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
|
||||
PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
|
||||
PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
|
||||
PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
|
||||
PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
PRIVATE: SPREAD_USE STRING "0"
|
||||
PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
PRIVATE: STICKY_CLK0 STRING "1"
|
||||
PRIVATE: STICKY_CLK1 STRING "1"
|
||||
PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
PRIVATE: USE_CLK0 STRING "1"
|
||||
PRIVATE: USE_CLK1 STRING "1"
|
||||
PRIVATE: USE_CLKENA0 STRING "0"
|
||||
PRIVATE: USE_CLKENA1 STRING "0"
|
||||
PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
|
||||
CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
|
||||
CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
||||
CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
|
||||
CONSTANT: LPM_TYPE STRING "altpll"
|
||||
CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
|
||||
USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
|
||||
GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
|
||||
LIB_FILE: altera_mf
|
||||
|
||||
LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 10915102B3011615119A
|
||||
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 10915102A3011615119A
|
||||
LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 10915102T3011615119M
|
||||
LICENSE_ID: "DEVICE_FAMILY_MAX V" 10915102H3011615119A
|
||||
LICENSE_ID: "DEVICE_FAMILY_Arria II GX" 10915102P3011615119S
|
||||
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 10915102B3011615119A
|
||||
LICENSE_ID: "DEVICE_FAMILY_MAX II" 10915102N3011615119S
|
||||
LICENSE_ID: "DEVICE_FAMILY_MAX 10" 10915102N3011615119S
|
||||
LICENSE_ID: "FEATURE_STRATIXGX_DPA" 10915102V3011615119C
|
||||
LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 10915102T3011615119M
|
||||
|
||||
|
||||
SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP"
|
||||
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
|
||||
SUPPORTED_DEVICE_FAMILY: "Arria II GX"
|
||||
SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
|
||||
SUPPORTED_DEVICE_FAMILY: "MAX 10"
|
||||
SUPPORTED_DEVICE_FAMILY: "Cyclone II"
|
||||
|
||||
WIZARD_TITLE: "ALTPLL"
|
||||
QUARTUS_VERSION: "Version 17.0"
|
||||
QUARTUS_SVERSION: "17.0.2 Build 602 07/19/2017 SJ Lite Edition:07/19/2017"
|
||||
QUARTUS_BUILD_DATE: "07/19/2017"
|
||||
ALTERA_COPYRIGHT: "Copyright (C) 2017 Intel Corporation. All rights reserved."
|
||||
|
||||
|
||||
HELP_MENU_ITEM: FALSE "IUG$altpll Megafunction User Guide$http://www.altera.com/literature/ug/ug_altpll.pdf"
|
||||
HELP_MENU_ITEM: FALSE "IUG$General-Purpose PLLs in Stratix (GX) Devices$http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf"
|
||||
HELP_MENU_ITEM: FALSE "IUG$PLLs in Stratix II Devices$http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf"
|
||||
HELP_MENU_ITEM: FALSE "IUG$Clock Networks and PLLs in Stratix III Devices$http://www.altera.com/literature/hb/stx3/stx3_siii51006.pdf "
|
||||
HELP_MENU_ITEM: FALSE "IUG$PLLs in Cyclone II Devices$http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf"
|
||||
@@ -1,7 +0,0 @@
|
||||
*******************************************
|
||||
** CNX File Error Log **
|
||||
*******************************************
|
||||
|
||||
Line 0: WM1.0
|
||||
No valid wizard signature (generation mode ) found
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone II" variation_name="Clock_50to100" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -1,5 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_50to100.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.ppf"]
|
||||
@@ -1,399 +0,0 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: Clock_50to100.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY Clock_50to100 IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END Clock_50to100;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF clock_50to100 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
gate_lock_signal : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
invalid_lock_multiplier : NATURAL;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
valid_lock_multiplier : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire6_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
sub_wire4 <= inclk0;
|
||||
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 1,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 2,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 1,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 2,
|
||||
clk1_phase_shift => "-2500 ps",
|
||||
compensate_clock => "CLK0",
|
||||
gate_lock_signal => "NO",
|
||||
inclk0_input_frequency => 20000,
|
||||
intended_device_family => "Cyclone V",
|
||||
invalid_lock_multiplier => 5,
|
||||
lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_UNUSED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
valid_lock_multiplier => 1
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire5,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
||||
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,6 +0,0 @@
|
||||
DATE = "14:58:03 December 18, 2014"
|
||||
QUARTUS_VERSION = "14.0"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "DE0_nano_zpu"
|
||||
@@ -1,476 +0,0 @@
|
||||
#============================================================
|
||||
# Build by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEMA4U23C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu"
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014"
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
|
||||
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
set_location_assignment PIN_U9 -to ADC_CONVST
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
|
||||
set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
|
||||
|
||||
#============================================================
|
||||
# ARDUINO
|
||||
#============================================================
|
||||
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
|
||||
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
|
||||
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
|
||||
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
|
||||
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
|
||||
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
|
||||
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
|
||||
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
|
||||
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
|
||||
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
|
||||
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
|
||||
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
|
||||
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
|
||||
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
|
||||
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
|
||||
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
|
||||
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
#set_location_assignment PIN_V11 -to FPGA_CLK1_50
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
|
||||
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
|
||||
set_location_assignment PIN_E11 -to FPGA_CLK3_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
|
||||
|
||||
#set_location_assignment PIN_R8 -to CLOCK_50
|
||||
|
||||
set_location_assignment PIN_V11 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
|
||||
#============================================================
|
||||
# HPS
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_location_assignment PIN_L10 -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_location_assignment PIN_L9 -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_location_assignment PIN_H6 -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_location_assignment PIN_H5 -to SW[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
|
||||
#============================================================
|
||||
# GPIO_0, GPIO connect to GPIO Default
|
||||
#============================================================
|
||||
set_location_assignment PIN_V12 -to GPIO_0[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
set_location_assignment PIN_AF7 -to GPIO_0[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
set_location_assignment PIN_W12 -to GPIO_0[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
set_location_assignment PIN_AF8 -to GPIO_0[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
set_location_assignment PIN_Y8 -to GPIO_0[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
set_location_assignment PIN_AB4 -to GPIO_0[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
set_location_assignment PIN_W8 -to GPIO_0[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
set_location_assignment PIN_Y4 -to GPIO_0[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
set_location_assignment PIN_Y5 -to GPIO_0[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
set_location_assignment PIN_U11 -to GPIO_0[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
set_location_assignment PIN_T8 -to GPIO_0[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
set_location_assignment PIN_T12 -to GPIO_0[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
set_location_assignment PIN_AH5 -to GPIO_0[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
set_location_assignment PIN_AH6 -to GPIO_0[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
set_location_assignment PIN_AH4 -to GPIO_0[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
set_location_assignment PIN_AG5 -to GPIO_0[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
set_location_assignment PIN_AH3 -to GPIO_0[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
set_location_assignment PIN_AH2 -to GPIO_0[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
set_location_assignment PIN_AF4 -to GPIO_0[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
set_location_assignment PIN_AG6 -to GPIO_0[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
set_location_assignment PIN_AF5 -to GPIO_0[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
set_location_assignment PIN_AE4 -to GPIO_0[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
set_location_assignment PIN_T13 -to GPIO_0[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
set_location_assignment PIN_T11 -to GPIO_0[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
set_location_assignment PIN_AE7 -to GPIO_0[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
set_location_assignment PIN_AF6 -to GPIO_0[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
set_location_assignment PIN_AF9 -to GPIO_0[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
set_location_assignment PIN_AE8 -to GPIO_0[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
set_location_assignment PIN_AD10 -to GPIO_0[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
set_location_assignment PIN_AE9 -to GPIO_0[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
set_location_assignment PIN_AD11 -to GPIO_0[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
set_location_assignment PIN_AF10 -to GPIO_0[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
#set_location_assignment PIN_AD12 -to GPIO_0[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
#set_location_assignment PIN_AE11 -to GPIO_0[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
#set_location_assignment PIN_AF11 -to GPIO_0[34]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
|
||||
#set_location_assignment PIN_AE12 -to GPIO_0[35]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
|
||||
|
||||
#============================================================
|
||||
# GPIO_1, GPIO connect to GPIO Default
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y15 -to GPIO_1[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
set_location_assignment PIN_AG28 -to GPIO_1[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
set_location_assignment PIN_AA15 -to GPIO_1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
set_location_assignment PIN_AH27 -to GPIO_1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
set_location_assignment PIN_AG26 -to GPIO_1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
set_location_assignment PIN_AH24 -to GPIO_1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
set_location_assignment PIN_AF23 -to GPIO_1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
set_location_assignment PIN_AE22 -to GPIO_1[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
set_location_assignment PIN_AF21 -to GPIO_1[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
set_location_assignment PIN_AG20 -to GPIO_1[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
set_location_assignment PIN_AG19 -to GPIO_1[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
set_location_assignment PIN_AF20 -to GPIO_1[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
set_location_assignment PIN_AC23 -to GPIO_1[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
set_location_assignment PIN_AG18 -to GPIO_1[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
set_location_assignment PIN_AH26 -to GPIO_1[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
set_location_assignment PIN_AA19 -to GPIO_1[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
set_location_assignment PIN_AG24 -to GPIO_1[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
set_location_assignment PIN_AF25 -to GPIO_1[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
set_location_assignment PIN_AH23 -to GPIO_1[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
set_location_assignment PIN_AG23 -to GPIO_1[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
set_location_assignment PIN_AE19 -to GPIO_1[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
set_location_assignment PIN_AF18 -to GPIO_1[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
set_location_assignment PIN_AD19 -to GPIO_1[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
set_location_assignment PIN_AE20 -to GPIO_1[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
set_location_assignment PIN_AE24 -to GPIO_1[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
set_location_assignment PIN_AD20 -to GPIO_1[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
set_location_assignment PIN_AF22 -to GPIO_1[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
set_location_assignment PIN_AH22 -to GPIO_1[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
set_location_assignment PIN_AH19 -to GPIO_1[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
set_location_assignment PIN_AH21 -to GPIO_1[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
set_location_assignment PIN_AG21 -to GPIO_1[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
set_location_assignment PIN_AH18 -to GPIO_1[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
set_location_assignment PIN_AD23 -to GPIO_1[32]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
set_location_assignment PIN_AE23 -to GPIO_1[33]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
set_location_assignment PIN_AA18 -to GPIO_1[34]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
|
||||
set_location_assignment PIN_AC22 -to GPIO_1[35]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
|
||||
|
||||
|
||||
set_location_assignment PIN_AE12 -to UART_TX_0
|
||||
set_location_assignment PIN_AE11 -to UART_RX_0
|
||||
set_location_assignment PIN_AF11 -to UART_TX_1
|
||||
set_location_assignment PIN_AD12 -to UART_RX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
|
||||
set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
|
||||
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../DE0_nano_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_50to100.qip
|
||||
set_global_assignment -name SDC_FILE DE0_nano_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
@@ -1,92 +0,0 @@
|
||||
#**************************************************************
|
||||
# This .sdc file is created by Terasic Tool.
|
||||
# Users are recommended to modify this file to match users logic.
|
||||
#**************************************************************
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
|
||||
|
||||
# for enhancing USB BlasterII to be reliable, 25MHz
|
||||
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
|
||||
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
|
||||
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
|
||||
set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
derive_pll_clocks
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
derive_clock_uncertainty
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Load
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
@@ -1,176 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity DE0_nano_zpu is
|
||||
port (
|
||||
-- Clock
|
||||
CLOCK_50 : in std_logic;
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
-- Debounced keys
|
||||
KEY : in std_logic_vector(1 downto 0);
|
||||
-- DIP switches
|
||||
SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
TDI : out std_logic;
|
||||
TCK : out std_logic;
|
||||
TCS : out std_logic;
|
||||
TDO : in std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
-- UART Serial channels.
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic;
|
||||
UART_RX_1 : in std_logic;
|
||||
UART_TX_1 : out std_logic
|
||||
|
||||
-- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
|
||||
-- SDRAM_CKE : out std_logic; -- clock enable.
|
||||
-- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
-- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
|
||||
-- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
|
||||
-- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
|
||||
-- SDRAM_CS : out std_logic; -- a single chip select
|
||||
-- SDRAM_WE : out std_logic; -- write enable
|
||||
-- SDRAM_RAS : out std_logic; -- row address select
|
||||
-- SDRAM_CAS : out std_logic -- columns address select
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of DE0_nano_zpu is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
LED <= "00000000";
|
||||
|
||||
mypll : entity work.Clock_50to100
|
||||
port map
|
||||
(
|
||||
inclk0 => CLOCK_50,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
reset<=(not SW(0) xor KEY(0)) and pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_DE0_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => UART_RX_1,
|
||||
UART_TX_1 => UART_TX_1,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => TDI,
|
||||
SPI_CLK => TCK,
|
||||
SPI_CS => TCS,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals
|
||||
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => open, --SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open
|
||||
|
||||
-- DDR2 DRAM - doesnt exist on the QMV.
|
||||
--DDR2_ADDR => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ => open, -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS => open, -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM => open, -- eight byte masks
|
||||
--DDR2_ODT => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_BA => open, -- 8 banks
|
||||
--DDR2_CS => open, -- 2 chip selects.
|
||||
--DDR2_WE => open, -- write enable
|
||||
--DDR2_RAS => open, -- row address select
|
||||
--DDR2_CAS => open, -- columns address select
|
||||
--DDR2_CKE => open, -- 2 clock enable.
|
||||
--DDR2_CLK => open -- 2 clocks.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,137 +0,0 @@
|
||||
## Generated SDC file "hello_led.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2011 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
|
||||
|
||||
## DATE "Fri Jul 06 23:05:47 2012"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25Q240C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}]
|
||||
create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
|
||||
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
|
||||
set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
|
||||
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
|
||||
set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
|
||||
#derive_clock_uncertainty
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {KEY*}]
|
||||
set_false_path -from [get_keepers {SW*}]
|
||||
#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
|
||||
#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
|
||||
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
@@ -1,32 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||||
# Date created = 15:48:30 August 02, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "16.1"
|
||||
DATE = "15:48:30 August 02, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "DE10_nano_zpu"
|
||||
PROJECT_REVISION = "DE10_nano_zpu"
|
||||
@@ -1,498 +0,0 @@
|
||||
#============================================================
|
||||
# Build by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
|
||||
#============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y15 -to UART_TX_0
|
||||
set_location_assignment PIN_AA15 -to UART_RX_0
|
||||
set_location_assignment PIN_AG28 -to UART_TX_1
|
||||
set_location_assignment PIN_AG26 -to UART_RX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# SD CARD
|
||||
#============================================================
|
||||
set_location_assignment PIN_AF25 -to SDCARD_MISO[0]
|
||||
set_location_assignment PIN_AF27 -to SDCARD_MOSI[0]
|
||||
set_location_assignment PIN_AH26 -to SDCARD_CLK[0]
|
||||
set_location_assignment PIN_AF28 -to SDCARD_CS[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
#set_location_assignment PIN_R8 -to CLOCK_50
|
||||
set_location_assignment PIN_V11 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_location_assignment PIN_Y24 -to SW[0]
|
||||
set_location_assignment PIN_W24 -to SW[1]
|
||||
set_location_assignment PIN_W21 -to SW[2]
|
||||
set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
#============================================================
|
||||
# SDIO
|
||||
#============================================================
|
||||
#set_location_assignment PIN_AF25 -to SDIO_DAT[0]
|
||||
#set_location_assignment PIN_AF23 -to SDIO_DAT[1]
|
||||
#set_location_assignment PIN_AD26 -to SDIO_DAT[2]
|
||||
#set_location_assignment PIN_AF28 -to SDIO_DAT[3]
|
||||
#set_location_assignment PIN_AF27 -to SDIO_CMD
|
||||
#set_location_assignment PIN_AH26 -to SDIO_CLK
|
||||
#set_location_assignment PIN_AH7 -to SDIO_CD
|
||||
#set_location_assignment PIN_AF25 -to TDO
|
||||
#set_location_assignment PIN_AF28 -to TCS
|
||||
#set_location_assignment PIN_AF27 -to TDI
|
||||
#set_location_assignment PIN_AH26 -to TCK
|
||||
|
||||
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
|
||||
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS
|
||||
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDO
|
||||
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TCS
|
||||
#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDI
|
||||
|
||||
#============================================================
|
||||
# SDRAM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_M7 -to SDRAM_BA[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
#set_location_assignment PIN_M6 -to SDRAM_BA[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
#set_location_assignment PIN_R6 -to SDRAM_DQM[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
|
||||
#set_location_assignment PIN_T5 -to SDRAM_DQM[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
|
||||
#set_location_assignment PIN_L2 -to SDRAM_RAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_N
|
||||
#set_location_assignment PIN_L1 -to SDRAM_CAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_N
|
||||
#set_location_assignment PIN_L7 -to SDRAM_CKE
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
#set_location_assignment PIN_R4 -to SDRAM_CLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
#set_location_assignment PIN_C2 -to SDRAM_WE_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_N
|
||||
#set_location_assignment PIN_P6 -to SDRAM_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_N
|
||||
#set_location_assignment PIN_G2 -to SDRAM_DQ[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
#set_location_assignment PIN_G1 -to SDRAM_DQ[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
#set_location_assignment PIN_L8 -to SDRAM_DQ[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
#set_location_assignment PIN_K5 -to SDRAM_DQ[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
#set_location_assignment PIN_K2 -to SDRAM_DQ[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
#set_location_assignment PIN_J2 -to SDRAM_DQ[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
#set_location_assignment PIN_J1 -to SDRAM_DQ[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
#set_location_assignment PIN_R7 -to SDRAM_DQ[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
#set_location_assignment PIN_T4 -to SDRAM_DQ[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
#set_location_assignment PIN_T2 -to SDRAM_DQ[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
#set_location_assignment PIN_T3 -to SDRAM_DQ[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
#set_location_assignment PIN_R3 -to SDRAM_DQ[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
#set_location_assignment PIN_R5 -to SDRAM_DQ[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
#set_location_assignment PIN_P3 -to SDRAM_DQ[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
#set_location_assignment PIN_N3 -to SDRAM_DQ[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
#set_location_assignment PIN_K1 -to SDRAM_DQ[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
#set_location_assignment PIN_P2 -to SDRAM_ADDR[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
|
||||
#set_location_assignment PIN_N5 -to SDRAM_ADDR[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
|
||||
#set_location_assignment PIN_N6 -to SDRAM_ADDR[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
|
||||
#set_location_assignment PIN_M8 -to SDRAM_ADDR[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
|
||||
#set_location_assignment PIN_P8 -to SDRAM_ADDR[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
|
||||
#set_location_assignment PIN_T7 -to SDRAM_ADDR[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
|
||||
#set_location_assignment PIN_N8 -to SDRAM_ADDR[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
|
||||
#set_location_assignment PIN_T6 -to SDRAM_ADDR[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
|
||||
#set_location_assignment PIN_R1 -to SDRAM_ADDR[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
|
||||
#set_location_assignment PIN_P1 -to SDRAM_ADDR[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
|
||||
#set_location_assignment PIN_N2 -to SDRAM_ADDR[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
|
||||
#set_location_assignment PIN_N1 -to SDRAM_ADDR[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
|
||||
#set_location_assignment PIN_L4 -to SDRAM_ADDR[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
|
||||
|
||||
#============================================================
|
||||
# EPCS
|
||||
#============================================================
|
||||
#set_location_assignment PIN_H2 -to EPCS_DATA0
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
|
||||
#set_location_assignment PIN_H1 -to EPCS_DCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
|
||||
#set_location_assignment PIN_D2 -to EPCS_NCSO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
|
||||
#set_location_assignment PIN_C1 -to EPCS_ASDO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
|
||||
|
||||
#============================================================
|
||||
# Accelerometer and EEPROM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_F2 -to I2C_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
|
||||
#set_location_assignment PIN_F1 -to I2C_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
|
||||
#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
|
||||
#set_location_assignment PIN_M2 -to G_SENSOR_INT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A10 -to ADC_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
|
||||
#set_location_assignment PIN_B10 -to ADC_SADDR
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
|
||||
#set_location_assignment PIN_B14 -to ADC_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
|
||||
#set_location_assignment PIN_A9 -to ADC_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
|
||||
|
||||
#============================================================
|
||||
# 2x13 GPIO Header
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A14 -to GPIO_2[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
|
||||
#set_location_assignment PIN_B16 -to GPIO_2[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
|
||||
#set_location_assignment PIN_C14 -to GPIO_2[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
|
||||
#set_location_assignment PIN_C16 -to GPIO_2[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
|
||||
#set_location_assignment PIN_C15 -to GPIO_2[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
|
||||
#set_location_assignment PIN_D16 -to GPIO_2[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
|
||||
#set_location_assignment PIN_D15 -to GPIO_2[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
|
||||
#set_location_assignment PIN_D14 -to GPIO_2[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
|
||||
#set_location_assignment PIN_F15 -to GPIO_2[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
|
||||
#set_location_assignment PIN_F16 -to GPIO_2[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
|
||||
#set_location_assignment PIN_F14 -to GPIO_2[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
|
||||
#set_location_assignment PIN_G16 -to GPIO_2[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
|
||||
#set_location_assignment PIN_G15 -to GPIO_2[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
|
||||
#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
|
||||
#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
|
||||
#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
|
||||
|
||||
#============================================================
|
||||
# GPIO_0, GPIO_0 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
|
||||
#set_location_assignment PIN_D3 -to GPIO_0[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
|
||||
#set_location_assignment PIN_C3 -to GPIO_0[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
#set_location_assignment PIN_A2 -to GPIO_0[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
#set_location_assignment PIN_A3 -to GPIO_0[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
#set_location_assignment PIN_B3 -to GPIO_0[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
#set_location_assignment PIN_B4 -to GPIO_0[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
#set_location_assignment PIN_A4 -to GPIO_0[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
#set_location_assignment PIN_B5 -to GPIO_0[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
#set_location_assignment PIN_A5 -to GPIO_0[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
#set_location_assignment PIN_D5 -to GPIO_0[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
#set_location_assignment PIN_B6 -to GPIO_0[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
#set_location_assignment PIN_A6 -to GPIO_0[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
#set_location_assignment PIN_B7 -to GPIO_0[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
#set_location_assignment PIN_D6 -to GPIO_0[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
#set_location_assignment PIN_A7 -to GPIO_0[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
#set_location_assignment PIN_C6 -to GPIO_0[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
#set_location_assignment PIN_C8 -to GPIO_0[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
#set_location_assignment PIN_E6 -to GPIO_0[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
#set_location_assignment PIN_E7 -to GPIO_0[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
#set_location_assignment PIN_D8 -to GPIO_0[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
#set_location_assignment PIN_E8 -to GPIO_0[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
#set_location_assignment PIN_F8 -to GPIO_0[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
#set_location_assignment PIN_F9 -to GPIO_0[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
#set_location_assignment PIN_E9 -to GPIO_0[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
#set_location_assignment PIN_C9 -to GPIO_0[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
#set_location_assignment PIN_D9 -to GPIO_0[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
#set_location_assignment PIN_E11 -to GPIO_0[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
#set_location_assignment PIN_E10 -to GPIO_0[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
#set_location_assignment PIN_C11 -to GPIO_0[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
#set_location_assignment PIN_B11 -to GPIO_0[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
#set_location_assignment PIN_A12 -to GPIO_0[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
#set_location_assignment PIN_D11 -to GPIO_0[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
#set_location_assignment PIN_D12 -to GPIO_0[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
#set_location_assignment PIN_B12 -to GPIO_0[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
|
||||
#============================================================
|
||||
# GPIO_1, GPIO_1 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
|
||||
#set_location_assignment PIN_F13 -to GPIO_1[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
|
||||
#set_location_assignment PIN_T15 -to GPIO_1[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
#set_location_assignment PIN_T14 -to GPIO_1[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
#set_location_assignment PIN_T13 -to GPIO_1[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
#set_location_assignment PIN_R13 -to GPIO_1[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
#set_location_assignment PIN_T12 -to GPIO_1[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
#set_location_assignment PIN_R12 -to GPIO_1[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
#set_location_assignment PIN_T11 -to GPIO_1[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
#set_location_assignment PIN_T10 -to GPIO_1[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
#set_location_assignment PIN_R11 -to GPIO_1[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
#set_location_assignment PIN_P11 -to GPIO_1[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
#set_location_assignment PIN_R10 -to GPIO_1[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
#set_location_assignment PIN_N12 -to GPIO_1[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
#set_location_assignment PIN_P9 -to GPIO_1[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
#set_location_assignment PIN_N9 -to GPIO_1[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
#set_location_assignment PIN_N11 -to GPIO_1[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
#set_location_assignment PIN_L16 -to GPIO_1[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
#set_location_assignment PIN_K16 -to GPIO_1[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
#set_location_assignment PIN_R16 -to GPIO_1[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
#set_location_assignment PIN_L15 -to GPIO_1[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
#set_location_assignment PIN_P15 -to GPIO_1[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
#set_location_assignment PIN_P16 -to GPIO_1[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
#set_location_assignment PIN_R14 -to GPIO_1[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
#set_location_assignment PIN_N16 -to GPIO_1[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
#set_location_assignment PIN_N15 -to GPIO_1[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
#set_location_assignment PIN_P14 -to GPIO_1[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
#set_location_assignment PIN_L14 -to GPIO_1[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
#set_location_assignment PIN_N14 -to GPIO_1[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
#set_location_assignment PIN_M10 -to GPIO_1[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
#set_location_assignment PIN_L13 -to GPIO_1[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
#set_location_assignment PIN_J16 -to GPIO_1[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
#set_location_assignment PIN_K15 -to GPIO_1[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
#set_location_assignment PIN_J13 -to GPIO_1[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
#set_location_assignment PIN_J14 -to GPIO_1[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
|
||||
|
||||
set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
|
||||
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_50to100.qip
|
||||
set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
|
||||
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,478 +0,0 @@
|
||||
#============================================================
|
||||
# Build by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
|
||||
set_location_assignment PIN_AA13 -to UART_TX_0
|
||||
set_location_assignment PIN_AA11 -to UART_RX_0
|
||||
set_location_assignment PIN_Y11 -to UART_TX_1
|
||||
set_location_assignment PIN_AA26 -to UART_RX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
#set_location_assignment PIN_R8 -to CLOCK_50
|
||||
set_location_assignment PIN_V11 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_location_assignment PIN_Y24 -to SW[0]
|
||||
set_location_assignment PIN_W24 -to SW[1]
|
||||
set_location_assignment PIN_W21 -to SW[2]
|
||||
set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
#============================================================
|
||||
# SDRAM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_M7 -to DRAM_BA[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
|
||||
#set_location_assignment PIN_M6 -to DRAM_BA[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
|
||||
#set_location_assignment PIN_R6 -to DRAM_DQM[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
|
||||
#set_location_assignment PIN_T5 -to DRAM_DQM[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
|
||||
#set_location_assignment PIN_L2 -to DRAM_RAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
|
||||
#set_location_assignment PIN_L1 -to DRAM_CAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
|
||||
#set_location_assignment PIN_L7 -to DRAM_CKE
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
|
||||
#set_location_assignment PIN_R4 -to DRAM_CLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
|
||||
#set_location_assignment PIN_C2 -to DRAM_WE_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
|
||||
#set_location_assignment PIN_P6 -to DRAM_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
|
||||
#set_location_assignment PIN_G2 -to DRAM_DQ[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
|
||||
#set_location_assignment PIN_G1 -to DRAM_DQ[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
|
||||
#set_location_assignment PIN_L8 -to DRAM_DQ[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
|
||||
#set_location_assignment PIN_K5 -to DRAM_DQ[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
|
||||
#set_location_assignment PIN_K2 -to DRAM_DQ[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
|
||||
#set_location_assignment PIN_J2 -to DRAM_DQ[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
|
||||
#set_location_assignment PIN_J1 -to DRAM_DQ[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
|
||||
#set_location_assignment PIN_R7 -to DRAM_DQ[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
|
||||
#set_location_assignment PIN_T4 -to DRAM_DQ[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
|
||||
#set_location_assignment PIN_T2 -to DRAM_DQ[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
|
||||
#set_location_assignment PIN_T3 -to DRAM_DQ[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
|
||||
#set_location_assignment PIN_R3 -to DRAM_DQ[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
|
||||
#set_location_assignment PIN_R5 -to DRAM_DQ[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
|
||||
#set_location_assignment PIN_P3 -to DRAM_DQ[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
|
||||
#set_location_assignment PIN_N3 -to DRAM_DQ[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
|
||||
#set_location_assignment PIN_K1 -to DRAM_DQ[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
|
||||
#set_location_assignment PIN_P2 -to DRAM_ADDR[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
|
||||
#set_location_assignment PIN_N5 -to DRAM_ADDR[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
|
||||
#set_location_assignment PIN_N6 -to DRAM_ADDR[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
|
||||
#set_location_assignment PIN_M8 -to DRAM_ADDR[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
|
||||
#set_location_assignment PIN_P8 -to DRAM_ADDR[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
|
||||
#set_location_assignment PIN_T7 -to DRAM_ADDR[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
|
||||
#set_location_assignment PIN_N8 -to DRAM_ADDR[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
|
||||
#set_location_assignment PIN_T6 -to DRAM_ADDR[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
|
||||
#set_location_assignment PIN_R1 -to DRAM_ADDR[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
|
||||
#set_location_assignment PIN_P1 -to DRAM_ADDR[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
|
||||
#set_location_assignment PIN_N2 -to DRAM_ADDR[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
|
||||
#set_location_assignment PIN_N1 -to DRAM_ADDR[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
|
||||
#set_location_assignment PIN_L4 -to DRAM_ADDR[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
|
||||
|
||||
#============================================================
|
||||
# EPCS
|
||||
#============================================================
|
||||
#set_location_assignment PIN_H2 -to EPCS_DATA0
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
|
||||
#set_location_assignment PIN_H1 -to EPCS_DCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
|
||||
#set_location_assignment PIN_D2 -to EPCS_NCSO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
|
||||
#set_location_assignment PIN_C1 -to EPCS_ASDO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
|
||||
|
||||
#============================================================
|
||||
# Accelerometer and EEPROM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_F2 -to I2C_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
|
||||
#set_location_assignment PIN_F1 -to I2C_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
|
||||
#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
|
||||
#set_location_assignment PIN_M2 -to G_SENSOR_INT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A10 -to ADC_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
|
||||
#set_location_assignment PIN_B10 -to ADC_SADDR
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
|
||||
#set_location_assignment PIN_B14 -to ADC_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
|
||||
#set_location_assignment PIN_A9 -to ADC_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
|
||||
|
||||
#============================================================
|
||||
# 2x13 GPIO Header
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A14 -to GPIO_2[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
|
||||
#set_location_assignment PIN_B16 -to GPIO_2[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
|
||||
#set_location_assignment PIN_C14 -to GPIO_2[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
|
||||
#set_location_assignment PIN_C16 -to GPIO_2[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
|
||||
#set_location_assignment PIN_C15 -to GPIO_2[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
|
||||
#set_location_assignment PIN_D16 -to GPIO_2[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
|
||||
#set_location_assignment PIN_D15 -to GPIO_2[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
|
||||
#set_location_assignment PIN_D14 -to GPIO_2[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
|
||||
#set_location_assignment PIN_F15 -to GPIO_2[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
|
||||
#set_location_assignment PIN_F16 -to GPIO_2[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
|
||||
#set_location_assignment PIN_F14 -to GPIO_2[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
|
||||
#set_location_assignment PIN_G16 -to GPIO_2[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
|
||||
#set_location_assignment PIN_G15 -to GPIO_2[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
|
||||
#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
|
||||
#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
|
||||
#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
|
||||
|
||||
#============================================================
|
||||
# GPIO_0, GPIO_0 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
|
||||
#set_location_assignment PIN_D3 -to GPIO_0[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
|
||||
#set_location_assignment PIN_C3 -to GPIO_0[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
#set_location_assignment PIN_A2 -to GPIO_0[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
#set_location_assignment PIN_A3 -to GPIO_0[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
#set_location_assignment PIN_B3 -to GPIO_0[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
#set_location_assignment PIN_B4 -to GPIO_0[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
#set_location_assignment PIN_A4 -to GPIO_0[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
#set_location_assignment PIN_B5 -to GPIO_0[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
#set_location_assignment PIN_A5 -to GPIO_0[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
#set_location_assignment PIN_D5 -to GPIO_0[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
#set_location_assignment PIN_B6 -to GPIO_0[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
#set_location_assignment PIN_A6 -to GPIO_0[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
#set_location_assignment PIN_B7 -to GPIO_0[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
#set_location_assignment PIN_D6 -to GPIO_0[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
#set_location_assignment PIN_A7 -to GPIO_0[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
#set_location_assignment PIN_C6 -to GPIO_0[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
#set_location_assignment PIN_C8 -to GPIO_0[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
#set_location_assignment PIN_E6 -to GPIO_0[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
#set_location_assignment PIN_E7 -to GPIO_0[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
#set_location_assignment PIN_D8 -to GPIO_0[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
#set_location_assignment PIN_E8 -to GPIO_0[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
#set_location_assignment PIN_F8 -to GPIO_0[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
#set_location_assignment PIN_F9 -to GPIO_0[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
#set_location_assignment PIN_E9 -to GPIO_0[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
#set_location_assignment PIN_C9 -to GPIO_0[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
#set_location_assignment PIN_D9 -to GPIO_0[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
#set_location_assignment PIN_E11 -to GPIO_0[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
#set_location_assignment PIN_E10 -to GPIO_0[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
#set_location_assignment PIN_C11 -to GPIO_0[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
#set_location_assignment PIN_B11 -to GPIO_0[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
#set_location_assignment PIN_A12 -to GPIO_0[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
#set_location_assignment PIN_D11 -to GPIO_0[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
#set_location_assignment PIN_D12 -to GPIO_0[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
#set_location_assignment PIN_B12 -to GPIO_0[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
|
||||
#============================================================
|
||||
# GPIO_1, GPIO_1 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
|
||||
#set_location_assignment PIN_F13 -to GPIO_1[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
|
||||
#set_location_assignment PIN_T15 -to GPIO_1[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
#set_location_assignment PIN_T14 -to GPIO_1[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
#set_location_assignment PIN_T13 -to GPIO_1[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
#set_location_assignment PIN_R13 -to GPIO_1[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
#set_location_assignment PIN_T12 -to GPIO_1[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
#set_location_assignment PIN_R12 -to GPIO_1[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
#set_location_assignment PIN_T11 -to GPIO_1[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
#set_location_assignment PIN_T10 -to GPIO_1[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
#set_location_assignment PIN_R11 -to GPIO_1[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
#set_location_assignment PIN_P11 -to GPIO_1[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
#set_location_assignment PIN_R10 -to GPIO_1[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
#set_location_assignment PIN_N12 -to GPIO_1[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
#set_location_assignment PIN_P9 -to GPIO_1[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
#set_location_assignment PIN_N9 -to GPIO_1[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
#set_location_assignment PIN_N11 -to GPIO_1[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
#set_location_assignment PIN_L16 -to GPIO_1[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
#set_location_assignment PIN_K16 -to GPIO_1[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
#set_location_assignment PIN_R16 -to GPIO_1[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
#set_location_assignment PIN_L15 -to GPIO_1[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
#set_location_assignment PIN_P15 -to GPIO_1[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
#set_location_assignment PIN_P16 -to GPIO_1[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
#set_location_assignment PIN_R14 -to GPIO_1[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
#set_location_assignment PIN_N16 -to GPIO_1[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
#set_location_assignment PIN_N15 -to GPIO_1[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
#set_location_assignment PIN_P14 -to GPIO_1[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
#set_location_assignment PIN_L14 -to GPIO_1[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
#set_location_assignment PIN_N14 -to GPIO_1[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
#set_location_assignment PIN_M10 -to GPIO_1[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
#set_location_assignment PIN_L13 -to GPIO_1[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
#set_location_assignment PIN_J16 -to GPIO_1[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
#set_location_assignment PIN_K15 -to GPIO_1[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
#set_location_assignment PIN_J13 -to GPIO_1[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
#set_location_assignment PIN_J14 -to GPIO_1[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
|
||||
|
||||
set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
|
||||
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_50to100.qip
|
||||
#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,486 +0,0 @@
|
||||
#============================================================
|
||||
# Build by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
|
||||
#set_location_assignment PIN_AA13 -to UART_TX_0
|
||||
#set_location_assignment PIN_AA11 -to UART_RX_0
|
||||
#set_location_assignment PIN_Y11 -to UART_TX_1
|
||||
#set_location_assignment PIN_AA26 -to UART_RX_1
|
||||
set_location_assignment PIN_Y15 -to UART_TX_0
|
||||
set_location_assignment PIN_AA15 -to UART_RX_0
|
||||
set_location_assignment PIN_AG28 -to UART_TX_1
|
||||
set_location_assignment PIN_AG26 -to UART_RX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
#set_location_assignment PIN_R8 -to CLOCK_50
|
||||
set_location_assignment PIN_V11 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_location_assignment PIN_Y24 -to SW[0]
|
||||
set_location_assignment PIN_W24 -to SW[1]
|
||||
set_location_assignment PIN_W21 -to SW[2]
|
||||
set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
#============================================================
|
||||
# SDRAM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_M7 -to DRAM_BA[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
|
||||
#set_location_assignment PIN_M6 -to DRAM_BA[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
|
||||
#set_location_assignment PIN_R6 -to DRAM_DQM[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
|
||||
#set_location_assignment PIN_T5 -to DRAM_DQM[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
|
||||
#set_location_assignment PIN_L2 -to DRAM_RAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
|
||||
#set_location_assignment PIN_L1 -to DRAM_CAS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
|
||||
#set_location_assignment PIN_L7 -to DRAM_CKE
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
|
||||
#set_location_assignment PIN_R4 -to DRAM_CLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
|
||||
#set_location_assignment PIN_C2 -to DRAM_WE_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
|
||||
#set_location_assignment PIN_P6 -to DRAM_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
|
||||
#set_location_assignment PIN_G2 -to DRAM_DQ[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
|
||||
#set_location_assignment PIN_G1 -to DRAM_DQ[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
|
||||
#set_location_assignment PIN_L8 -to DRAM_DQ[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
|
||||
#set_location_assignment PIN_K5 -to DRAM_DQ[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
|
||||
#set_location_assignment PIN_K2 -to DRAM_DQ[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
|
||||
#set_location_assignment PIN_J2 -to DRAM_DQ[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
|
||||
#set_location_assignment PIN_J1 -to DRAM_DQ[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
|
||||
#set_location_assignment PIN_R7 -to DRAM_DQ[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
|
||||
#set_location_assignment PIN_T4 -to DRAM_DQ[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
|
||||
#set_location_assignment PIN_T2 -to DRAM_DQ[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
|
||||
#set_location_assignment PIN_T3 -to DRAM_DQ[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
|
||||
#set_location_assignment PIN_R3 -to DRAM_DQ[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
|
||||
#set_location_assignment PIN_R5 -to DRAM_DQ[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
|
||||
#set_location_assignment PIN_P3 -to DRAM_DQ[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
|
||||
#set_location_assignment PIN_N3 -to DRAM_DQ[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
|
||||
#set_location_assignment PIN_K1 -to DRAM_DQ[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
|
||||
#set_location_assignment PIN_P2 -to DRAM_ADDR[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
|
||||
#set_location_assignment PIN_N5 -to DRAM_ADDR[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
|
||||
#set_location_assignment PIN_N6 -to DRAM_ADDR[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
|
||||
#set_location_assignment PIN_M8 -to DRAM_ADDR[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
|
||||
#set_location_assignment PIN_P8 -to DRAM_ADDR[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
|
||||
#set_location_assignment PIN_T7 -to DRAM_ADDR[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
|
||||
#set_location_assignment PIN_N8 -to DRAM_ADDR[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
|
||||
#set_location_assignment PIN_T6 -to DRAM_ADDR[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
|
||||
#set_location_assignment PIN_R1 -to DRAM_ADDR[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
|
||||
#set_location_assignment PIN_P1 -to DRAM_ADDR[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
|
||||
#set_location_assignment PIN_N2 -to DRAM_ADDR[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
|
||||
#set_location_assignment PIN_N1 -to DRAM_ADDR[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
|
||||
#set_location_assignment PIN_L4 -to DRAM_ADDR[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
|
||||
|
||||
#============================================================
|
||||
# EPCS
|
||||
#============================================================
|
||||
#set_location_assignment PIN_H2 -to EPCS_DATA0
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
|
||||
#set_location_assignment PIN_H1 -to EPCS_DCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
|
||||
#set_location_assignment PIN_D2 -to EPCS_NCSO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
|
||||
#set_location_assignment PIN_C1 -to EPCS_ASDO
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
|
||||
|
||||
#============================================================
|
||||
# Accelerometer and EEPROM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_F2 -to I2C_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
|
||||
#set_location_assignment PIN_F1 -to I2C_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
|
||||
#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
|
||||
#set_location_assignment PIN_M2 -to G_SENSOR_INT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A10 -to ADC_CS_N
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
|
||||
#set_location_assignment PIN_B10 -to ADC_SADDR
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
|
||||
#set_location_assignment PIN_B14 -to ADC_SCLK
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
|
||||
#set_location_assignment PIN_A9 -to ADC_SDAT
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
|
||||
|
||||
#============================================================
|
||||
# 2x13 GPIO Header
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A14 -to GPIO_2[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
|
||||
#set_location_assignment PIN_B16 -to GPIO_2[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
|
||||
#set_location_assignment PIN_C14 -to GPIO_2[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
|
||||
#set_location_assignment PIN_C16 -to GPIO_2[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
|
||||
#set_location_assignment PIN_C15 -to GPIO_2[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
|
||||
#set_location_assignment PIN_D16 -to GPIO_2[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
|
||||
#set_location_assignment PIN_D15 -to GPIO_2[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
|
||||
#set_location_assignment PIN_D14 -to GPIO_2[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
|
||||
#set_location_assignment PIN_F15 -to GPIO_2[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
|
||||
#set_location_assignment PIN_F16 -to GPIO_2[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
|
||||
#set_location_assignment PIN_F14 -to GPIO_2[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
|
||||
#set_location_assignment PIN_G16 -to GPIO_2[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
|
||||
#set_location_assignment PIN_G15 -to GPIO_2[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
|
||||
#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
|
||||
#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
|
||||
#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
|
||||
|
||||
#============================================================
|
||||
# GPIO_0, GPIO_0 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
|
||||
#set_location_assignment PIN_D3 -to GPIO_0[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
|
||||
#set_location_assignment PIN_C3 -to GPIO_0[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
#set_location_assignment PIN_A2 -to GPIO_0[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
#set_location_assignment PIN_A3 -to GPIO_0[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
#set_location_assignment PIN_B3 -to GPIO_0[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
#set_location_assignment PIN_B4 -to GPIO_0[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
#set_location_assignment PIN_A4 -to GPIO_0[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
#set_location_assignment PIN_B5 -to GPIO_0[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
#set_location_assignment PIN_A5 -to GPIO_0[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
#set_location_assignment PIN_D5 -to GPIO_0[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
#set_location_assignment PIN_B6 -to GPIO_0[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
#set_location_assignment PIN_A6 -to GPIO_0[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
#set_location_assignment PIN_B7 -to GPIO_0[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
#set_location_assignment PIN_D6 -to GPIO_0[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
#set_location_assignment PIN_A7 -to GPIO_0[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
#set_location_assignment PIN_C6 -to GPIO_0[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
#set_location_assignment PIN_C8 -to GPIO_0[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
#set_location_assignment PIN_E6 -to GPIO_0[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
#set_location_assignment PIN_E7 -to GPIO_0[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
#set_location_assignment PIN_D8 -to GPIO_0[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
#set_location_assignment PIN_E8 -to GPIO_0[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
#set_location_assignment PIN_F8 -to GPIO_0[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
#set_location_assignment PIN_F9 -to GPIO_0[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
#set_location_assignment PIN_E9 -to GPIO_0[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
#set_location_assignment PIN_C9 -to GPIO_0[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
#set_location_assignment PIN_D9 -to GPIO_0[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
#set_location_assignment PIN_E11 -to GPIO_0[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
#set_location_assignment PIN_E10 -to GPIO_0[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
#set_location_assignment PIN_C11 -to GPIO_0[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
#set_location_assignment PIN_B11 -to GPIO_0[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
#set_location_assignment PIN_A12 -to GPIO_0[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
#set_location_assignment PIN_D11 -to GPIO_0[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
#set_location_assignment PIN_D12 -to GPIO_0[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
#set_location_assignment PIN_B12 -to GPIO_0[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
|
||||
#============================================================
|
||||
# GPIO_1, GPIO_1 connect to GPIO Default
|
||||
#============================================================
|
||||
#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
|
||||
#set_location_assignment PIN_F13 -to GPIO_1[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
|
||||
#set_location_assignment PIN_T15 -to GPIO_1[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
#set_location_assignment PIN_T14 -to GPIO_1[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
#set_location_assignment PIN_T13 -to GPIO_1[3]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
#set_location_assignment PIN_R13 -to GPIO_1[4]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
#set_location_assignment PIN_T12 -to GPIO_1[5]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
#set_location_assignment PIN_R12 -to GPIO_1[6]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
#set_location_assignment PIN_T11 -to GPIO_1[7]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
#set_location_assignment PIN_T10 -to GPIO_1[8]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
#set_location_assignment PIN_R11 -to GPIO_1[9]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
#set_location_assignment PIN_P11 -to GPIO_1[10]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
#set_location_assignment PIN_R10 -to GPIO_1[11]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
#set_location_assignment PIN_N12 -to GPIO_1[12]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
#set_location_assignment PIN_P9 -to GPIO_1[13]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
#set_location_assignment PIN_N9 -to GPIO_1[14]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
#set_location_assignment PIN_N11 -to GPIO_1[15]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
#set_location_assignment PIN_L16 -to GPIO_1[16]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
#set_location_assignment PIN_K16 -to GPIO_1[17]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
#set_location_assignment PIN_R16 -to GPIO_1[18]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
#set_location_assignment PIN_L15 -to GPIO_1[19]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
#set_location_assignment PIN_P15 -to GPIO_1[20]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
#set_location_assignment PIN_P16 -to GPIO_1[21]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
#set_location_assignment PIN_R14 -to GPIO_1[22]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
#set_location_assignment PIN_N16 -to GPIO_1[23]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
#set_location_assignment PIN_N15 -to GPIO_1[24]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
#set_location_assignment PIN_P14 -to GPIO_1[25]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
#set_location_assignment PIN_L14 -to GPIO_1[26]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
#set_location_assignment PIN_N14 -to GPIO_1[27]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
#set_location_assignment PIN_M10 -to GPIO_1[28]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
#set_location_assignment PIN_L13 -to GPIO_1[29]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
#set_location_assignment PIN_J16 -to GPIO_1[30]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
#set_location_assignment PIN_K15 -to GPIO_1[31]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
#set_location_assignment PIN_J13 -to GPIO_1[32]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
#set_location_assignment PIN_J14 -to GPIO_1[33]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
|
||||
|
||||
set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
|
||||
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_50to100.qip
|
||||
#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,174 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity DE10_nano_zpu is
|
||||
port (
|
||||
-- Clock
|
||||
CLOCK_50 : in std_logic;
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
-- Debounced keys
|
||||
KEY : in std_logic_vector(1 downto 0);
|
||||
-- DIP switches
|
||||
SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
TDI : out std_logic;
|
||||
TCK : out std_logic;
|
||||
TCS : out std_logic;
|
||||
TDO : in std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
-- UART Serial channels.
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic;
|
||||
UART_RX_1 : in std_logic;
|
||||
UART_TX_1 : out std_logic
|
||||
|
||||
-- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
|
||||
-- SDRAM_CKE : out std_logic; -- clock enable.
|
||||
-- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
-- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
|
||||
-- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
|
||||
-- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
|
||||
-- SDRAM_CS : out std_logic; -- a single chip select
|
||||
-- SDRAM_WE : out std_logic; -- write enable
|
||||
-- SDRAM_RAS : out std_logic; -- row address select
|
||||
-- SDRAM_CAS : out std_logic -- columns address select
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of DE10_nano_zpu is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
LED <= "00000000";
|
||||
|
||||
mypll : entity work.Clock_50to100
|
||||
port map
|
||||
(
|
||||
inclk0 => CLOCK_50,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
reset<=(not SW(0) xor KEY(0)) and pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_DE10_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => UART_RX_1,
|
||||
UART_TX_1 => UART_TX_1,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => TDI,
|
||||
SPI_CLK => TCK,
|
||||
SPI_CS => TCS,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals
|
||||
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => open, --SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open
|
||||
|
||||
-- DDR2 DRAM - doesnt exist on the QMV.
|
||||
--DDR2_ADDR => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ => open, -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS => open, -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM => open, -- eight byte masks
|
||||
--DDR2_ODT => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_BA => open, -- 8 banks
|
||||
--DDR2_CS => open, -- 2 chip selects.
|
||||
--DDR2_WE => open, -- write enable
|
||||
--DDR2_RAS => open, -- row address select
|
||||
--DDR2_CAS => open, -- columns address select
|
||||
--DDR2_CKE => open, -- 2 clock enable.
|
||||
--DDR2_CLK => open -- 2 clocks.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,154 +0,0 @@
|
||||
## Generated SDC file "hello_led.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2011 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
|
||||
|
||||
## DATE "Fri Jul 06 23:05:47 2012"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25Q240C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -multiply_by 2 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll1_outclk}]
|
||||
#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -phase 0 -multiply_by 4 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll2_outclk}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
|
||||
derive_clock_uncertainty
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
|
||||
#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {KEY*}]
|
||||
set_false_path -from [get_keepers {SW*}]
|
||||
#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
|
||||
#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
|
||||
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
@@ -1,13 +0,0 @@
|
||||
/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
P ActionCode(Cfg)
|
||||
Device PartName(EP4CE115F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("E115_zpu.sof") MfrSpec(OpMask(1));
|
||||
|
||||
ChainEnd;
|
||||
|
||||
AlteraBegin;
|
||||
ChainType(JTAG);
|
||||
AlteraEnd;
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "5.0"
|
||||
DATE = "23:35:58 September 01, 2005"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "E115_zpu"
|
||||
@@ -1,302 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# ledwater_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name CDF_FILE E115.cdf
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP4CE115F23I7
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
set_global_assignment -name ENABLE_SIGNALTAP ON
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
|
||||
|
||||
|
||||
|
||||
#============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_A7 -to UART_RX_0
|
||||
set_location_assignment PIN_B7 -to UART_TX_0
|
||||
set_location_assignment PIN_C6 -to UART_RX_1
|
||||
set_location_assignment PIN_D7 -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# SD CARD
|
||||
#============================================================
|
||||
set_location_assignment PIN_C8 -to SDCARD_MISO[0]
|
||||
set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
|
||||
set_location_assignment PIN_B8 -to SDCARD_CLK[0]
|
||||
set_location_assignment PIN_A8 -to SDCARD_CS[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_AB11 -to CLOCK_25
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_25
|
||||
#set_location_assignment PIN_AB11 -to clk_25M
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_location_assignment PIN_A5 -to LED[0]
|
||||
set_location_assignment PIN_B5 -to LED[1]
|
||||
set_location_assignment PIN_C4 -to LED[2]
|
||||
set_location_assignment PIN_C3 -to LED[3]
|
||||
|
||||
#============================================================
|
||||
# DDR2 DRAM
|
||||
#============================================================
|
||||
#set_location_assignment PIN_AA20 -to DDR2_ADDR[13]
|
||||
#set_location_assignment PIN_V8 -to DDR2_ADDR[12]
|
||||
#set_location_assignment PIN_AB6 -to DDR2_ADDR[11]
|
||||
#set_location_assignment PIN_K22 -to DDR2_ADDR[10]
|
||||
#set_location_assignment PIN_W10 -to DDR2_ADDR[9]
|
||||
#set_location_assignment PIN_T19 -to DDR2_ADDR[8]
|
||||
#set_location_assignment PIN_Y14 -to DDR2_ADDR[7]
|
||||
#set_location_assignment PIN_W14 -to DDR2_ADDR[6]
|
||||
#set_location_assignment PIN_T20 -to DDR2_ADDR[5]
|
||||
#set_location_assignment PIN_Y15 -to DDR2_ADDR[4]
|
||||
#set_location_assignment PIN_L22 -to DDR2_ADDR[3]
|
||||
#set_location_assignment PIN_Y17 -to DDR2_ADDR[2]
|
||||
#set_location_assignment PIN_L21 -to DDR2_ADDR[1]
|
||||
#set_location_assignment PIN_AB10 -to DDR2_ADDR[0]
|
||||
#set_location_assignment PIN_Y6 -to DDR2_BA[2]
|
||||
#set_location_assignment PIN_AB17 -to DDR2_BA[1]
|
||||
#set_location_assignment PIN_K21 -to DDR2_BA[0]
|
||||
#set_location_assignment PIN_J18 -to DDR2_CAS
|
||||
#set_location_assignment PIN_Y4 -to DDR2_CKE[0]
|
||||
#set_location_assignment PIN_AB5 -to DDR2_CKE[1]
|
||||
#set_location_assignment PIN_AA19 -to DDR2_CS[0]
|
||||
#set_location_assignment PIN_E21 -to DDR2_CS[1]
|
||||
#
|
||||
#set_location_assignment PIN_F20 -to DDR2_DM[7]
|
||||
#set_location_assignment PIN_F22 -to DDR2_DM[6]
|
||||
#set_location_assignment PIN_P22 -to DDR2_DM[5]
|
||||
#set_location_assignment PIN_V22 -to DDR2_DM[4]
|
||||
#set_location_assignment PIN_W15 -to DDR2_DM[3]
|
||||
#set_location_assignment PIN_AA14 -to DDR2_DM[2]
|
||||
#set_location_assignment PIN_AA8 -to DDR2_DM[1]
|
||||
#set_location_assignment PIN_AA5 -to DDR2_DM[0]
|
||||
#
|
||||
#set_location_assignment PIN_B21 -to DDR2_DQ[63]
|
||||
#set_location_assignment PIN_B22 -to DDR2_DQ[62]
|
||||
#set_location_assignment PIN_C21 -to DDR2_DQ[61]
|
||||
#set_location_assignment PIN_C22 -to DDR2_DQ[60]
|
||||
#set_location_assignment PIN_D22 -to DDR2_DQ[59]
|
||||
#set_location_assignment PIN_F19 -to DDR2_DQ[58]
|
||||
#set_location_assignment PIN_F17 -to DDR2_DQ[57]
|
||||
#set_location_assignment PIN_G18 -to DDR2_DQ[56]
|
||||
#set_location_assignment PIN_E22 -to DDR2_DQ[55]
|
||||
#set_location_assignment PIN_F21 -to DDR2_DQ[54]
|
||||
#set_location_assignment PIN_H21 -to DDR2_DQ[53]
|
||||
#set_location_assignment PIN_H22 -to DDR2_DQ[52]
|
||||
#set_location_assignment PIN_H19 -to DDR2_DQ[51]
|
||||
#set_location_assignment PIN_H20 -to DDR2_DQ[50]
|
||||
#set_location_assignment PIN_K18 -to DDR2_DQ[49]
|
||||
#set_location_assignment PIN_J21 -to DDR2_DQ[48]
|
||||
#set_location_assignment PIN_M22 -to DDR2_DQ[47]
|
||||
#set_location_assignment PIN_M21 -to DDR2_DQ[46]
|
||||
#set_location_assignment PIN_R22 -to DDR2_DQ[45]
|
||||
#set_location_assignment PIN_R21 -to DDR2_DQ[44]
|
||||
#set_location_assignment PIN_M20 -to DDR2_DQ[43]
|
||||
#set_location_assignment PIN_N20 -to DDR2_DQ[42]
|
||||
#set_location_assignment PIN_P21 -to DDR2_DQ[41]
|
||||
#set_location_assignment PIN_R19 -to DDR2_DQ[40]
|
||||
#set_location_assignment PIN_U22 -to DDR2_DQ[39]
|
||||
#set_location_assignment PIN_U21 -to DDR2_DQ[38]
|
||||
#set_location_assignment PIN_V21 -to DDR2_DQ[37]
|
||||
#set_location_assignment PIN_W22 -to DDR2_DQ[36]
|
||||
#set_location_assignment PIN_R20 -to DDR2_DQ[35]
|
||||
#set_location_assignment PIN_U20 -to DDR2_DQ[34]
|
||||
#set_location_assignment PIN_Y22 -to DDR2_DQ[33]
|
||||
#set_location_assignment PIN_AA21 -to DDR2_DQ[32]
|
||||
#set_location_assignment PIN_AB20 -to DDR2_DQ[31]
|
||||
#set_location_assignment PIN_AB18 -to DDR2_DQ[30]
|
||||
#set_location_assignment PIN_AA16 -to DDR2_DQ[29]
|
||||
#set_location_assignment PIN_AB16 -to DDR2_DQ[28]
|
||||
#set_location_assignment PIN_W17 -to DDR2_DQ[27]
|
||||
#set_location_assignment PIN_V15 -to DDR2_DQ[26]
|
||||
#set_location_assignment PIN_T15 -to DDR2_DQ[25]
|
||||
#set_location_assignment PIN_V14 -to DDR2_DQ[24]
|
||||
#set_location_assignment PIN_AA15 -to DDR2_DQ[23]
|
||||
#set_location_assignment PIN_AB15 -to DDR2_DQ[22]
|
||||
#set_location_assignment PIN_AB14 -to DDR2_DQ[21]
|
||||
#set_location_assignment PIN_AA13 -to DDR2_DQ[20]
|
||||
#set_location_assignment PIN_W13 -to DDR2_DQ[19]
|
||||
#set_location_assignment PIN_U12 -to DDR2_DQ[18]
|
||||
#set_location_assignment PIN_AB13 -to DDR2_DQ[17]
|
||||
#set_location_assignment PIN_AA10 -to DDR2_DQ[16]
|
||||
#set_location_assignment PIN_AA9 -to DDR2_DQ[15]
|
||||
#set_location_assignment PIN_AB8 -to DDR2_DQ[14]
|
||||
#set_location_assignment PIN_AB7 -to DDR2_DQ[13]
|
||||
#set_location_assignment PIN_AA7 -to DDR2_DQ[12]
|
||||
#set_location_assignment PIN_V11 -to DDR2_DQ[11]
|
||||
#set_location_assignment PIN_Y10 -to DDR2_DQ[10]
|
||||
#set_location_assignment PIN_U10 -to DDR2_DQ[9]
|
||||
#set_location_assignment PIN_Y8 -to DDR2_DQ[8]
|
||||
#set_location_assignment PIN_W8 -to DDR2_DQ[7]
|
||||
#set_location_assignment PIN_V5 -to DDR2_DQ[6]
|
||||
#set_location_assignment PIN_AA4 -to DDR2_DQ[5]
|
||||
#set_location_assignment PIN_Y3 -to DDR2_DQ[4]
|
||||
#set_location_assignment PIN_U9 -to DDR2_DQ[3]
|
||||
#set_location_assignment PIN_W7 -to DDR2_DQ[2]
|
||||
#set_location_assignment PIN_Y7 -to DDR2_DQ[1]
|
||||
#set_location_assignment PIN_W6 -to DDR2_DQ[0]
|
||||
#
|
||||
#set_location_assignment PIN_C20 -to DDR2_DQS[7]
|
||||
#set_location_assignment PIN_J22 -to DDR2_DQS[6]
|
||||
#set_location_assignment PIN_N18 -to DDR2_DQS[5]
|
||||
#set_location_assignment PIN_W20 -to DDR2_DQS[4]
|
||||
#set_location_assignment PIN_V13 -to DDR2_DQS[3]
|
||||
#set_location_assignment PIN_Y13 -to DDR2_DQS[2]
|
||||
#set_location_assignment PIN_AB9 -to DDR2_DQS[1]
|
||||
#set_location_assignment PIN_V10 -to DDR2_DQS[0]
|
||||
#
|
||||
#set_location_assignment PIN_AB19 -to DDR2_ODT[0]
|
||||
#set_location_assignment PIN_D21 -to DDR2_ODT[1]
|
||||
#set_location_assignment PIN_AA17 -to DDR2_RAS
|
||||
#set_location_assignment PIN_J20 -to DDR2_WE
|
||||
|
||||
#============================================================
|
||||
# Modules and Files
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_25to100.qip
|
||||
set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,176 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# ledwater_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
#set_global_assignment -name VERILOG_FILE ledwater.v
|
||||
set_global_assignment -name CDF_FILE E115.cdf
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP4CE115F23I7
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
#============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_A7 -to UART_RX_0
|
||||
set_location_assignment PIN_B7 -to UART_TX_0
|
||||
set_location_assignment PIN_C6 -to UART_RX_1
|
||||
set_location_assignment PIN_D7 -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_AB11 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
#set_location_assignment PIN_AB11 -to clk_25M
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_location_assignment PIN_A5 -to LED[0]
|
||||
set_location_assignment PIN_B5 -to LED[1]
|
||||
set_location_assignment PIN_C4 -to LED[2]
|
||||
set_location_assignment PIN_C3 -to LED[3]
|
||||
|
||||
#============================================================
|
||||
# Modules and Files
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_25to100.qip
|
||||
set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
|
||||
#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
|
||||
#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,177 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity E115_zpu is
|
||||
port (
|
||||
-- Clock
|
||||
CLOCK_25 : in std_logic;
|
||||
-- LED
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
-- Debounced keys
|
||||
KEY : in std_logic_vector(1 downto 0);
|
||||
-- DIP switches
|
||||
SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- TDI : in std_logic;
|
||||
-- TCK : in std_logic;
|
||||
-- TCS : in std_logic;
|
||||
-- TDO : out std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
-- UART Serial channels.
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic;
|
||||
UART_RX_1 : in std_logic;
|
||||
UART_TX_1 : out std_logic
|
||||
|
||||
-- DDR2 DRAM
|
||||
--DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
|
||||
--DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
|
||||
--DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
|
||||
--DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
|
||||
--DDR2_WE : out std_logic; -- write enable
|
||||
--DDR2_RAS : out std_logic; -- row address select
|
||||
--DDR2_CAS : out std_logic; -- columns address select
|
||||
--DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
|
||||
--DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of E115_zpu is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
LED <= "00000000";
|
||||
|
||||
mypll : entity work.Clock_25to100
|
||||
port map
|
||||
(
|
||||
inclk0 => CLOCK_25,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
reset<=(not SW(0) xor KEY(0)) and pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => UART_RX_1,
|
||||
UART_TX_1 => UART_TX_1,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => open,
|
||||
SPI_CLK => open,
|
||||
SPI_CS => open,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals which do not exist on the E115
|
||||
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => open, --SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open -- sd ready.
|
||||
|
||||
-- DDR2 DRAM
|
||||
--DDR2_ADDR => DDR2_ADDR, -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ => DDR2_DQ, -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS => DDR2_DQS, -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM => DDR2_DQM, -- eight byte masks
|
||||
--DDR2_ODT => DDR2_ODT, -- 14 bit multiplexed address bus
|
||||
--DDR2_BA => DDR2_BA, -- 8 banks
|
||||
--DDR2_CS => DDR2_CS, -- 2 chip selects.
|
||||
--DDR2_WE => DDR2_WE, -- write enable
|
||||
--DDR2_RAS => DDR2_RAS, -- row address select
|
||||
--DDR2_CAS => DDR2_CAS, -- columns address select
|
||||
--DDR2_CKE => DDR2_CKE, -- 2 clock enable.
|
||||
--DDR2_CLK => DDR2_CLK -- 2 clocks.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,129 +0,0 @@
|
||||
## Generated SDC file "E115_zpu.out.sdc"
|
||||
|
||||
## Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
## Your use of Intel Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Intel Program License
|
||||
## Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
## the Intel FPGA IP License Agreement, or other applicable license
|
||||
## agreement, including, without limitation, that your use is for
|
||||
## the sole purpose of programming logic devices manufactured by
|
||||
## Intel and sold by Intel or its authorized distributors. Please
|
||||
## refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus Prime"
|
||||
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
|
||||
|
||||
## DATE "Sat Jun 22 23:32:00 2019"
|
||||
|
||||
##
|
||||
## DEVICE "EP4CE115F23I7"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk_25} -period 40.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_25}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 4 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk0}]
|
||||
#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 8 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk1}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
|
||||
#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
|
||||
derive_clock_uncertainty
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {KEY*}]
|
||||
set_false_path -from [get_keepers {SW*}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -1,303 +0,0 @@
|
||||
#########################################################################################################
|
||||
##
|
||||
## Name: Makefile
|
||||
## Created: June 2019
|
||||
## Author(s): Philip Smart
|
||||
## Description: ZPU Makefile
|
||||
## This script builds the ZPU test images and should be used as a basis for main
|
||||
## project builds.
|
||||
##
|
||||
## Credits:
|
||||
## Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
|
||||
##
|
||||
## History: June 2019 - Initial script written.
|
||||
##
|
||||
#########################################################################################################
|
||||
## This source file is free software: you can redistribute it and#or modify
|
||||
## it under the terms of the GNU General Public License as published
|
||||
## by the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This source file is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#########################################################################################################
|
||||
|
||||
DE10_IP = 192.168.10.1
|
||||
DE10_USER = root
|
||||
DE10_PWD = 1
|
||||
ROOT = ../
|
||||
|
||||
# Build utilites
|
||||
QUARTUS_SH = quartus_sh
|
||||
QUARTUS_CPF = quartus_cpf
|
||||
TEE = tee
|
||||
ECHO = echo
|
||||
MV = mv
|
||||
GREP = grep
|
||||
RM = rm
|
||||
CC = CC $(CINCLUDES)
|
||||
AR = ar
|
||||
LD = ld
|
||||
|
||||
# Build flags
|
||||
SH_FLAGS = --flow compile
|
||||
CPF_FLAGS = -c -o bitstream_compression=on
|
||||
MSG_FILTER = "Error\|success"
|
||||
# MSG_FILTER = "Info\|Warning\|Error\|success"
|
||||
# MSG_FILTER = "Info\|Warning\|Error\|success"
|
||||
# MSG_FILTER = "Info\|Warning\|Error\|success"
|
||||
|
||||
SOC = $(ROOT)/zpu_soc.vhd $(ROOT)/zpu_soc_pkg.vhd
|
||||
ZPU_EVO = $(ROOT)/cpu/zpu_core_evo.vhd $(ROOT)/cpu/zpu_pkg.vhd
|
||||
|
||||
.PHONY: all
|
||||
all: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
|
||||
DE0_nano: DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL
|
||||
DE10_nano: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL
|
||||
E115: E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL
|
||||
QMV: QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL
|
||||
CYC1000: CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
|
||||
SMALL: DE10_nano_SMALL E115_SMALL DE0_nano_SMALL QMV_SMALL CYC1000_SMALL
|
||||
MEDIUM: DE10_nano_MEDIUM E115_MEDIUM DE0_nano_MEDIUM QMV_MEDIUM CYC1000_MEDIUM
|
||||
FLEX: DE10_nano_FLEX E115_FLEX DE0_nano_FLEX QMV_FLEX CYC1000_FLEX
|
||||
EVO: DE10_nano_EVO E115_EVO DE0_nano_EVO QMV_EVO CYC1000_EVO
|
||||
EVO_MINIMAL: DE10_nano_EVO_MINIMAL E115_EVO_MINIMAL DE0_nano_EVO_MINIMAL QMV_EVO_MINIMAL CYC1000_EVO_MINIMAL
|
||||
|
||||
DE10_nano_SMALL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE10_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE10_nano_MEDIUM:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE10_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE10_nano_FLEX:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE10_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE10_nano_EVO:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE10_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE10_nano_EVO_MINIMAL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE10_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE0_nano_SMALL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE0_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE0_nano_MEDIUM:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE0_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE0_nano_FLEX:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE0_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE0_nano_EVO:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE0_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
DE0_nano_EVO_MINIMAL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) DE0_nano_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
E115_SMALL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) E115_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
E115_MEDIUM:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) E115_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
E115_FLEX:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) E115_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
E115_EVO:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) E115_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
E115_EVO_MINIMAL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) E115_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
QMV_SMALL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) QMV_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
QMV_MEDIUM:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) QMV_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
QMV_FLEX:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) QMV_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
QMV_EVO:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) QMV_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
QMV_EVO_MINIMAL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) QMV_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
CYC1000_SMALL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) CYC1000_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
CYC1000_MEDIUM:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) CYC1000_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
CYC1000_FLEX:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) CYC1000_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
CYC1000_EVO:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) CYC1000_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
CYC1000_EVO_MINIMAL:
|
||||
@cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
|
||||
> $(ROOT)/zpu_soc_pkg.vhd
|
||||
@$(ECHO) "Compiling $@..."
|
||||
@$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(MV) CYC1000_zpu.sof $@.sof
|
||||
@$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
|
||||
@$(ECHO) "$@.sof and $@.rbf generated..."
|
||||
|
||||
clean:
|
||||
@$(ECHO) "Removing all temporary files..."
|
||||
@$(RM) -fr c5_pin_model_dump.txt ./db ./simulation DE0_nano_zpu.asm.rpt DE0_nano_zpu.done DE0_nano_zpu.fit.rpt DE0_nano_zpu.fit.smsg DE0_nano_zpu.fit.summary DE0_nano_zpu.flow.rpt DE0_nano_zpu.jdi DE0_nano_zpu.map.rpt DE0_nano_zpu.map.smsg DE0_nano_zpu.map.summary DE0_nano_zpu.pin DE0_nano_zpu.rbf DE0_nano_zpu.sld DE0_nano_zpu.sof DE0_nano_zpu.sta.rpt DE0_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE0*.log DE0_nano*.rbf DE0_nano*.sof DE0_nano*.sta.smsg
|
||||
@$(RM) -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE10*.log DE10_nano*.rbf DE10_nano*.sof DE10_nano*.sta.smsg
|
||||
@$(RM) -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof E115*.log E115*.rbf E115*.sof E115*.sta.smsg
|
||||
@$(RM) -fr c5_pin_model_dump.txt ./db CYC1000_zpu.asm.rpt CYC1000_zpu.done CYC1000_zpu.fit.rpt CYC1000_zpu.fit.smsg CYC1000_zpu.fit.summary CYC1000_zpu.flow.rpt CYC1000_zpu.jdi CYC1000_zpu.map.rpt CYC1000_zpu.map.smsg CYC1000_zpu.map.summary CYC1000_zpu.pin CYC1000_zpu.rbf CYC1000_zpu.sld CYC1000_zpu.sof CYC1000_zpu.sta.rpt CYC1000_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt CYC1000_zpu.pof CYC1000*.log CYC1000*.rbf CYC1000*.sof CYC1000*.sta.smsg
|
||||
@$(RM) -fr c5_pin_model_dump.txt ./db QMV_zpu.asm.rpt QMV_zpu.done QMV_zpu.fit.rpt QMV_zpu.fit.smsg QMV_zpu.fit.summary QMV_zpu.flow.rpt QMV_zpu.jdi QMV_zpu.map.rpt QMV_zpu.map.smsg QMV_zpu.map.summary QMV_zpu.pin QMV_zpu.rbf QMV_zpu.sld QMV_zpu.sof QMV_zpu.sta.rpt QMV_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt QMV_zpu.pof QMV*.log QMV*.rbf QMV*.sof QMV*.sta.smsg
|
||||
@$(RM) -fr output_files
|
||||
@@ -1,13 +0,0 @@
|
||||
/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
P ActionCode(Cfg)
|
||||
Device PartName(5CEFA2F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("QMV_zpu.sof") MfrSpec(OpMask(1));
|
||||
|
||||
ChainEnd;
|
||||
|
||||
AlteraBegin;
|
||||
ChainType(JTAG);
|
||||
AlteraEnd;
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "5.0"
|
||||
DATE = "23:35:58 September 01, 2005"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "QMV_zpu"
|
||||
@@ -1,473 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# ledwater_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
set_global_assignment -name CDF_FILE QMV.cdf
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY QMV_zpu
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE 5CEFA2F23C8
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
set_global_assignment -name ENABLE_SIGNALTAP ON
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS 8
|
||||
|
||||
|
||||
#============================================================
|
||||
# CLOCK2
|
||||
#============================================================
|
||||
|
||||
#============================================================
|
||||
# CLOCK3
|
||||
#============================================================
|
||||
|
||||
#============================================================
|
||||
# CLOCK4
|
||||
#============================================================
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_M9 -to CLOCK_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
|
||||
|
||||
#============================================================
|
||||
# DRAM
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y9 -to SDRAM_ADDR[12]
|
||||
set_location_assignment PIN_T9 -to SDRAM_ADDR[11]
|
||||
set_location_assignment PIN_R6 -to SDRAM_ADDR[10]
|
||||
set_location_assignment PIN_W8 -to SDRAM_ADDR[9]
|
||||
set_location_assignment PIN_T8 -to SDRAM_ADDR[8]
|
||||
set_location_assignment PIN_U8 -to SDRAM_ADDR[7]
|
||||
set_location_assignment PIN_V6 -to SDRAM_ADDR[6]
|
||||
set_location_assignment PIN_U7 -to SDRAM_ADDR[5]
|
||||
set_location_assignment PIN_U6 -to SDRAM_ADDR[4]
|
||||
set_location_assignment PIN_N6 -to SDRAM_ADDR[3]
|
||||
set_location_assignment PIN_N8 -to SDRAM_ADDR[2]
|
||||
set_location_assignment PIN_P7 -to SDRAM_ADDR[1]
|
||||
set_location_assignment PIN_P8 -to SDRAM_ADDR[0]
|
||||
set_location_assignment PIN_P9 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_T7 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_AA7 -to SDRAM_CAS
|
||||
set_location_assignment PIN_V9 -to SDRAM_CKE
|
||||
set_location_assignment PIN_AB11 -to SDRAM_CLK
|
||||
set_location_assignment PIN_AB5 -to SDRAM_CS
|
||||
set_location_assignment PIN_P12 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_R12 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_U12 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_R11 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_R10 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_U11 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_T10 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_U10 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_AA8 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_AB8 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_AA9 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_Y10 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_AB10 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_AA10 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_Y11 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_AA12 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_AB7 -to SDRAM_DQM[0]
|
||||
set_location_assignment PIN_AB6 -to SDRAM_RAS
|
||||
set_location_assignment PIN_V10 -to SDRAM_DQM[1]
|
||||
set_location_assignment PIN_W9 -to SDRAM_WE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[13]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[0]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[1]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[2]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[3]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[4]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[5]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[6]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[7]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[8]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[9]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[10]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[11]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[12]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[1]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[0]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[1]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[0]
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_RAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_WE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CS
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CAS
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_RAS
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_WE
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CKE
|
||||
set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CLK
|
||||
|
||||
#============================================================
|
||||
# GPIO
|
||||
#============================================================
|
||||
# U8 5 - 59, odd
|
||||
#
|
||||
# U8 6 - 58 Even
|
||||
set_location_assignment PIN_AA13 -to BANK_4A_AA13
|
||||
set_location_assignment PIN_AB15 -to BANK_4A_AB15
|
||||
set_location_assignment PIN_Y14 -to BANK_4A_Y14
|
||||
set_location_assignment PIN_AB17 -to BANK_4A_AB17
|
||||
set_location_assignment PIN_Y16 -to BANK_4A_Y16
|
||||
set_location_assignment PIN_AA17 -to BANK_4A_AA17
|
||||
set_location_assignment PIN_AA19 -to BANK_4A_AA19
|
||||
set_location_assignment PIN_Y19 -to BANK_4A_Y19
|
||||
set_location_assignment PIN_AB20 -to BANK_4A_AB20
|
||||
set_location_assignment PIN_AB22 -to BANK_4A_AB22
|
||||
set_location_assignment PIN_Y22 -to BANK_4A_Y22
|
||||
set_location_assignment PIN_W21 -to BANK_4A_W21
|
||||
set_location_assignment PIN_V21 -to BANK_4A_V21
|
||||
set_location_assignment PIN_W19 -to BANK_4A_W19
|
||||
set_location_assignment PIN_U20 -to BANK_4A_U20
|
||||
set_location_assignment PIN_T22 -to BANK_5A_T22
|
||||
set_location_assignment PIN_R21 -to BANK_5A_R21
|
||||
set_location_assignment PIN_T19 -to BANK_5A_T19
|
||||
set_location_assignment PIN_P17 -to BANK_5A_P17
|
||||
set_location_assignment PIN_N21 -to BANK_5B_N21
|
||||
set_location_assignment PIN_M20 -to BANK_5B_M20
|
||||
set_location_assignment PIN_N19 -to BANK_5B_N19
|
||||
set_location_assignment PIN_L19 -to BANK_5B_L19
|
||||
set_location_assignment PIN_L22 -to BANK_5B_L22
|
||||
set_location_assignment PIN_K17 -to BANK_5B_K17
|
||||
set_location_assignment PIN_K21 -to BANK_5B_K21
|
||||
set_location_assignment PIN_N16 -to BANK_5B_N16
|
||||
#
|
||||
# U7 5 - 59 odd
|
||||
#set_location_assignment PIN_AA14 -to BANK_4A_AA14
|
||||
#set_location_assignment PIN_AA15 -to BANK_4A_AA15
|
||||
#set_location_assignment PIN_Y15 -to BANK_4A_Y15
|
||||
#set_location_assignment PIN_AB18 -to BANK_4A_AB18
|
||||
set_location_assignment PIN_Y17 -to BANK_4A_Y17
|
||||
set_location_assignment PIN_AA18 -to BANK_4A_AA18
|
||||
set_location_assignment PIN_AA20 -to BANK_4A_AA20
|
||||
set_location_assignment PIN_Y20 -to BANK_4A_Y20
|
||||
set_location_assignment PIN_AB21 -to BANK_4A_AB21
|
||||
set_location_assignment PIN_AA22 -to BANK_4A_AA22
|
||||
set_location_assignment PIN_W22 -to BANK_4A_W22
|
||||
set_location_assignment PIN_Y21 -to BANK_4A_Y21
|
||||
set_location_assignment PIN_U22 -to BANK_4A_U22
|
||||
set_location_assignment PIN_V20 -to BANK_4A_V20
|
||||
set_location_assignment PIN_U21 -to BANK_4A_U21
|
||||
set_location_assignment PIN_R22 -to BANK_5A_R22
|
||||
set_location_assignment PIN_P22 -to BANK_5A_P22
|
||||
set_location_assignment PIN_T20 -to BANK_5A_T20
|
||||
set_location_assignment PIN_P16 -to BANK_5A_P16
|
||||
set_location_assignment PIN_N20 -to BANK_5B_N20
|
||||
set_location_assignment PIN_M21 -to BANK_5B_M21
|
||||
set_location_assignment PIN_M18 -to BANK_5B_M18
|
||||
set_location_assignment PIN_L18 -to BANK_5B_L18
|
||||
set_location_assignment PIN_M22 -to BANK_5B_M22
|
||||
set_location_assignment PIN_L17 -to BANK_5B_L17
|
||||
set_location_assignment PIN_K22 -to BANK_5B_K22
|
||||
set_location_assignment PIN_M16 -to BANK_5B_M16
|
||||
#
|
||||
# U7 6 - 60 even
|
||||
set_location_assignment PIN_AA1 -to BANK_2A_AA1
|
||||
set_location_assignment PIN_W2 -to BANK_2A_W2
|
||||
set_location_assignment PIN_U2 -to BANK_2A_U2
|
||||
set_location_assignment PIN_N2 -to BANK_2A_N2
|
||||
set_location_assignment PIN_L2 -to BANK_2A_L2
|
||||
set_location_assignment PIN_G2 -to BANK_2A_G2
|
||||
set_location_assignment PIN_D3 -to BANK_2A_D3
|
||||
set_location_assignment PIN_C2 -to BANK_2A_C2
|
||||
set_location_assignment PIN_H6 -to BANK_8A_H6
|
||||
set_location_assignment PIN_H8 -to BANK_8A_H8
|
||||
set_location_assignment PIN_E7 -to BANK_8A_E7
|
||||
set_location_assignment PIN_C6 -to BANK_8A_C6
|
||||
set_location_assignment PIN_D9 -to BANK_8A_D9
|
||||
set_location_assignment PIN_A5 -to BANK_8A_A5
|
||||
set_location_assignment PIN_B7 -to BANK_8A_B7
|
||||
set_location_assignment PIN_A8 -to BANK_8A_A8
|
||||
set_location_assignment PIN_A10 -to BANK_8A_A10
|
||||
set_location_assignment PIN_C9 -to BANK_8A_C9
|
||||
set_location_assignment PIN_F10 -to BANK_8A_F10
|
||||
set_location_assignment PIN_B11 -to BANK_7A_B11
|
||||
set_location_assignment PIN_A12 -to BANK_7A_A12
|
||||
set_location_assignment PIN_D12 -to BANK_7A_D12
|
||||
set_location_assignment PIN_C13 -to BANK_7A_C13
|
||||
set_location_assignment PIN_A13 -to BANK_7A_A13
|
||||
set_location_assignment PIN_A14 -to BANK_7A_A14
|
||||
set_location_assignment PIN_C15 -to BANK_7A_C15
|
||||
set_location_assignment PIN_B16 -to BANK_7A_B16
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_location_assignment PIN_AB13 -to KEY
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY
|
||||
|
||||
#============================================================
|
||||
# LEDR
|
||||
#============================================================
|
||||
set_location_assignment PIN_D17 -to LEDR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR
|
||||
|
||||
#============================================================
|
||||
# PS2
|
||||
#============================================================
|
||||
|
||||
#============================================================
|
||||
# RESET
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
|
||||
set_location_assignment PIN_V18 -to RESET_N
|
||||
|
||||
##============================================================
|
||||
# SD CARD
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y17 -to SDCARD_MISO[0]
|
||||
set_location_assignment PIN_AA18 -to SDCARD_MOSI[0]
|
||||
set_location_assignment PIN_AA20 -to SDCARD_CLK[0]
|
||||
set_location_assignment PIN_Y20 -to SDCARD_CS[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
|
||||
##============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_AA14 -to UART_RX_0
|
||||
set_location_assignment PIN_AA15 -to UART_TX_0
|
||||
set_location_assignment PIN_Y15 -to UART_RX_1
|
||||
set_location_assignment PIN_AB18 -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
#============================================================
|
||||
# Modules and Files
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../QMV_zpu_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_50to100.qip
|
||||
set_global_assignment -name SDC_FILE QMV_zpu_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,175 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity QMV_zpu is
|
||||
port (
|
||||
-- Clock
|
||||
CLOCK_50 : in std_logic;
|
||||
-- RED LED
|
||||
LEDR : out std_logic;
|
||||
-- Debounced keys
|
||||
KEY : in std_logic;
|
||||
-- DIP switches
|
||||
-- SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- TDI : in std_logic;
|
||||
-- TCK : in std_logic;
|
||||
-- TCS : in std_logic;
|
||||
-- TDO : out std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
-- UART Serial channels.
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic;
|
||||
UART_RX_1 : in std_logic;
|
||||
UART_TX_1 : out std_logic;
|
||||
|
||||
SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE : out std_logic; -- clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
|
||||
SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
|
||||
SDRAM_CS : out std_logic; -- a single chip select
|
||||
SDRAM_WE : out std_logic; -- write enable
|
||||
SDRAM_RAS : out std_logic; -- row address select
|
||||
SDRAM_CAS : out std_logic -- columns address select
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of QMV_zpu is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
LEDR <= '0';
|
||||
|
||||
mypll : entity work.Clock_50to100
|
||||
port map
|
||||
(
|
||||
areset => not KEY,
|
||||
inclk0 => CLOCK_50,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
reset <= KEY and pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_QMV_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => UART_RX_1,
|
||||
UART_TX_1 => UART_TX_1,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => open,
|
||||
SPI_CLK => open,
|
||||
SPI_CS => open,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals
|
||||
SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open -- sd ready.
|
||||
|
||||
-- DDR2 DRAM - doesnt exist on the QMV.
|
||||
--DDR2_ADDR => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ => open, -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS => open, -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM => open, -- eight byte masks
|
||||
--DDR2_ODT => open, -- 14 bit multiplexed address bus
|
||||
--DDR2_BA => open, -- 8 banks
|
||||
--DDR2_CS => open, -- 2 chip selects.
|
||||
--DDR2_WE => open, -- write enable
|
||||
--DDR2_RAS => open, -- row address select
|
||||
--DDR2_CAS => open, -- columns address select
|
||||
--DDR2_CKE => open, -- 2 clock enable.
|
||||
--DDR2_CLK => open -- 2 clocks.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,121 +0,0 @@
|
||||
## Generated SDC file "QMV_zpu.out.sdc"
|
||||
|
||||
## Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
## Your use of Intel Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Intel Program License
|
||||
## Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
## the Intel FPGA IP License Agreement, or other applicable license
|
||||
## agreement, including, without limitation, that your use is for
|
||||
## the sole purpose of programming logic devices manufactured by
|
||||
## Intel and sold by Intel or its authorized distributors. Please
|
||||
## refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus Prime"
|
||||
## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
|
||||
|
||||
## DATE "Sat Jun 22 23:32:00 2019"
|
||||
|
||||
##
|
||||
## DEVICE "5CEFA2F23C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
create_generated_clock -name {SYSCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -phase 000 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}]
|
||||
create_generated_clock -name {MEMCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -offset -2500 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}]
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
derive_clock_uncertainty
|
||||
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060
|
||||
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080
|
||||
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060
|
||||
#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080
|
||||
#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
# Delays for async signals - not necessary, but might as well avoid
|
||||
# having unconstrained ports in the design
|
||||
#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
|
||||
#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
|
||||
set_false_path -from [get_keepers {KEY*}]
|
||||
#set_false_path -from [get_keepers {SW*}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
|
||||
#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
|
||||
#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
|
||||
#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
|
||||
# Date created = 00:31:03 November 27, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "17.1"
|
||||
DATE = "00:31:03 November 27, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "ReVerSE-U16"
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "5.0"
|
||||
DATE = "23:35:58 September 01, 2005"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "ReVerSE_U16"
|
||||
@@ -1,211 +0,0 @@
|
||||
# Copyright (C) 1991-2005 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# ledwater_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
|
||||
#set_global_assignment -name VERILOG_FILE ledwater.v
|
||||
set_global_assignment -name CDF_FILE E115.cdf
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY ReVerSE_U16
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP4CE22E22C7
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
|
||||
|
||||
#============================================================
|
||||
# UART
|
||||
#============================================================
|
||||
set_location_assignment PIN_72 -to UART_RX_0
|
||||
set_location_assignment PIN_71 -to UART_TX_0
|
||||
#set_location_assignment PIN_C6 -to UART_RX_1
|
||||
#set_location_assignment PIN_D7 -to UART_TX_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
|
||||
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
|
||||
|
||||
#============================================================
|
||||
# SD CARD
|
||||
#============================================================
|
||||
#set_location_assignment PIN_C8 -to SDCARD_MISO[0]
|
||||
#set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
|
||||
#set_location_assignment PIN_B8 -to SDCARD_CLK[0]
|
||||
#set_location_assignment PIN_A8 -to SDCARD_CS[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
|
||||
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
|
||||
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
|
||||
#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_location_assignment PIN_25 -to REVERSEU16_CLOCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to REVERSEU16_CLOCK
|
||||
#set_location_assignment PIN_AB11 -to clk_25M
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
#set_location_assignment PIN_A5 -to LED[0]
|
||||
#set_location_assignment PIN_B5 -to LED[1]
|
||||
#set_location_assignment PIN_C4 -to LED[2]
|
||||
#set_location_assignment PIN_C3 -to LED[3]
|
||||
|
||||
|
||||
set_location_assignment PIN_32 -to reset_button
|
||||
set_location_assignment PIN_98 -to SDRAM_ADDR[0]
|
||||
set_location_assignment PIN_86 -to SDRAM_ADDR[1]
|
||||
set_location_assignment PIN_87 -to SDRAM_ADDR[2]
|
||||
set_location_assignment PIN_105 -to SDRAM_ADDR[3]
|
||||
set_location_assignment PIN_76 -to SDRAM_ADDR[4]
|
||||
set_location_assignment PIN_77 -to SDRAM_ADDR[5]
|
||||
set_location_assignment PIN_80 -to SDRAM_ADDR[6]
|
||||
set_location_assignment PIN_83 -to SDRAM_ADDR[7]
|
||||
set_location_assignment PIN_85 -to SDRAM_ADDR[8]
|
||||
set_location_assignment PIN_67 -to SDRAM_ADDR[9]
|
||||
set_location_assignment PIN_99 -to SDRAM_ADDR[10]
|
||||
set_location_assignment PIN_69 -to SDRAM_ADDR[11]
|
||||
set_location_assignment PIN_68 -to SDRAM_ADDR[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_100 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PIN_119 -to SDRAM_DQM[0]
|
||||
set_location_assignment PIN_66 -to SDRAM_DQM[1]
|
||||
set_location_assignment PIN_142 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_141 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_137 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_136 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_135 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_125 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_121 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_120 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_65 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_64 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_60 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_46 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_44 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_59 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_42 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_58 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_106 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_103 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_104 -to SDRAM_nWE
|
||||
|
||||
#============================================================
|
||||
# Modules and Files
|
||||
#============================================================
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../ReVerSE_U16_Toplevel.vhd
|
||||
set_global_assignment -name QIP_FILE Clock_25to100.qip
|
||||
set_global_assignment -name SDC_FILE ReVerSE_U16_constraints.sdc
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
|
||||
set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/sdram.qip
|
||||
#set_global_assignment -name VHDL_FILE ../devices/sysbus/SDRAM/sdram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
|
||||
#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
|
||||
set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
|
||||
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,165 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
|
||||
entity ReVerSE_U16 is
|
||||
port (
|
||||
-- Clock
|
||||
REVERSEU16_CLOCK: in std_logic;
|
||||
--
|
||||
reset_button : in std_logic;
|
||||
-- LED
|
||||
--LED : out std_logic_vector(7 downto 0);
|
||||
-- Debounced keys
|
||||
--KEY : in std_logic_vector(1 downto 0);
|
||||
-- DIP switches
|
||||
--SW : in std_logic_vector(3 downto 0);
|
||||
|
||||
-- TDI : in std_logic;
|
||||
-- TCK : in std_logic;
|
||||
-- TCS : in std_logic;
|
||||
-- TDO : out std_logic;
|
||||
-- I2C_SDAT : inout std_logic;
|
||||
-- I2C_SCLK : out std_logic;
|
||||
-- GPIO_0 : inout std_logic_vector(33 downto 0);
|
||||
-- GPIO_1 : inout std_logic_vector(33 downto 0);
|
||||
|
||||
-- SD Card 1
|
||||
SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
|
||||
|
||||
-- UART Serial channels.
|
||||
UART_RX_0 : in std_logic;
|
||||
UART_TX_0 : out std_logic
|
||||
--UART_RX_1 : in std_logic;
|
||||
--UART_TX_1 : out std_logic
|
||||
|
||||
-- DDR2 DRAM
|
||||
--DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
|
||||
--DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
|
||||
--DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
|
||||
--DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
|
||||
--DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
|
||||
--DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
|
||||
--DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
|
||||
--DDR2_WE : out std_logic; -- write enable
|
||||
--DDR2_RAS : out std_logic; -- row address select
|
||||
--DDR2_CAS : out std_logic; -- columns address select
|
||||
--DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
|
||||
--DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
|
||||
);
|
||||
END entity;
|
||||
|
||||
architecture rtl of ReVerSE_U16 is
|
||||
|
||||
signal reset : std_logic;
|
||||
signal sysclk : std_logic;
|
||||
signal memclk : std_logic;
|
||||
signal pll_locked : std_logic;
|
||||
|
||||
--signal ps2m_clk_in : std_logic;
|
||||
--signal ps2m_clk_out : std_logic;
|
||||
--signal ps2m_dat_in : std_logic;
|
||||
--signal ps2m_dat_out : std_logic;
|
||||
|
||||
--signal ps2k_clk_in : std_logic;
|
||||
--signal ps2k_clk_out : std_logic;
|
||||
--signal ps2k_dat_in : std_logic;
|
||||
--signal ps2k_dat_out : std_logic;
|
||||
|
||||
--alias PS2_MDAT : std_logic is GPIO_1(19);
|
||||
--alias PS2_MCLK : std_logic is GPIO_1(18);
|
||||
|
||||
begin
|
||||
|
||||
--I2C_SDAT <= 'Z';
|
||||
--GPIO_0(33 downto 2) <= (others => 'Z');
|
||||
--GPIO_1 <= (others => 'Z');
|
||||
--LED <= "101010" & reset & UART_RX_0;
|
||||
--LED <= "00000000";
|
||||
|
||||
mypll : entity work.Clock_25to100
|
||||
port map
|
||||
(
|
||||
inclk0 => REVERSEU16_CLOCK,
|
||||
c0 => sysclk,
|
||||
c1 => memclk,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
reset <= reset_button or pll_locked;
|
||||
|
||||
myVirtualToplevel : entity work.zpu_soc
|
||||
generic map
|
||||
(
|
||||
SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
|
||||
)
|
||||
port map
|
||||
(
|
||||
SYSCLK => sysclk,
|
||||
MEMCLK => memclk,
|
||||
RESET_IN => reset,
|
||||
|
||||
-- RS232
|
||||
UART_RX_0 => UART_RX_0,
|
||||
UART_TX_0 => UART_TX_0,
|
||||
UART_RX_1 => '0',
|
||||
UART_TX_1 => open,
|
||||
|
||||
-- SPI signals
|
||||
SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
|
||||
SPI_MOSI => open,
|
||||
SPI_CLK => open,
|
||||
SPI_CS => open,
|
||||
|
||||
-- SD Card (SPI) signals
|
||||
SDCARD_MISO => SDCARD_MISO,
|
||||
SDCARD_MOSI => SDCARD_MOSI,
|
||||
SDCARD_CLK => SDCARD_CLK,
|
||||
SDCARD_CS => SDCARD_CS,
|
||||
|
||||
-- PS/2 signals
|
||||
PS2K_CLK_IN => '1',
|
||||
PS2K_DAT_IN => '1',
|
||||
PS2K_CLK_OUT => open,
|
||||
PS2K_DAT_OUT => open,
|
||||
PS2M_CLK_IN => '1',
|
||||
PS2M_DAT_IN => '1',
|
||||
PS2M_CLK_OUT => open,
|
||||
PS2M_DAT_OUT => open,
|
||||
|
||||
-- I²C signals
|
||||
I2C_SCL_IO => open,
|
||||
I2C_SDA_IO => open,
|
||||
|
||||
-- IOCTL Bus --
|
||||
IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
|
||||
IOCTL_UPLOAD => open, -- Uploading from FPGA.
|
||||
IOCTL_CLK => open, -- I/O Clock.
|
||||
IOCTL_WR => open, -- Write Enable to FPGA.
|
||||
IOCTL_RD => open, -- Read Enable from FPGA.
|
||||
IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
|
||||
IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
|
||||
IOCTL_ADDR => open, -- Address in FPGA to write into.
|
||||
IOCTL_DOUT => open, -- Data to be written into FPGA.
|
||||
IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
|
||||
|
||||
-- SDRAM signals which do not exist on the E115
|
||||
SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
|
||||
SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
|
||||
SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
|
||||
SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
|
||||
SDRAM_BA => open, --SDRAM_BA, -- two banks
|
||||
SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
|
||||
SDRAM_WE_n => open, --SDRAM_WE, -- write enable
|
||||
SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
|
||||
SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
|
||||
SDRAM_READY => open -- sd ready.
|
||||
);
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -1,4 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
rm -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt
|
||||
rm -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof
|
||||
617
zpu/build/ddd
617
zpu/build/ddd
@@ -1,617 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: sdram.vhd
|
||||
-- Created: September 2019
|
||||
-- Original Author: Stephen J. Leary 2013-2014
|
||||
-- VHDL Author: Philip Smart
|
||||
-- Description: Original verilog module written by Stephen J. Leary 2013-2014 for the Archimedes
|
||||
-- emulator with the MT48LC16M16 chip.
|
||||
-- The verilog has been translated into VHDL and adapted for both the system bus and
|
||||
-- the Wishbone bus undergoing extensive modifications to work with the ZPU EVO processor,
|
||||
-- specifically parameterisation and burst tuning to enhance L2 Cache Fill performance.
|
||||
-- Credits:
|
||||
-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved.
|
||||
-- VHDL translation, sysbus adaptation and enhancements (c) 2019 Philip Smart
|
||||
-- <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog
|
||||
-- source code.
|
||||
-- November 2019 - Adapted for the system bus for use when no Wishbone interface is
|
||||
-- instantiated in the ZPU Evo.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity SDRAM is
|
||||
generic (
|
||||
MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions.
|
||||
SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM.
|
||||
SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row).
|
||||
SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM.
|
||||
SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (ie. 16, 32).
|
||||
SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz.
|
||||
SDRAM_tRCD : integer := 2; -- tRCD - RAS to CAS minimum period (in ns), ie. 20ns -> 2 cycles@100MHz
|
||||
SDRAM_tRP : integer := 2; -- tRP - Precharge delay, min time for a precharge command to complete (in ns), ie. 15ns -> 2 cycles@100MHz
|
||||
SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
|
||||
SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms).
|
||||
);
|
||||
port (
|
||||
-- SDRAM Interface
|
||||
SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK.
|
||||
SDRAM_RST : in std_logic; -- Reset the sdram controller.
|
||||
SDRAM_CKE : out std_logic; -- Clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks.
|
||||
SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM
|
||||
SDRAM_CS_n : out std_logic; -- Single chip select
|
||||
SDRAM_WE_n : out std_logic; -- Write enable
|
||||
SDRAM_RAS_n : out std_logic; -- Row address select
|
||||
SDRAM_CAS_n : out std_logic; -- Columns address select
|
||||
SDRAM_READY : out std_logic; -- SD ready.
|
||||
|
||||
-- CPU Interface
|
||||
CLK : in std_logic; -- System master clock
|
||||
RESET : in std_logic; -- High active sync reset
|
||||
ADDR : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0);
|
||||
DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); -- Write data
|
||||
DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); -- Read data
|
||||
WRITE_BYTE : in std_logic; -- Write a single byte as specified in A1:A0
|
||||
WRITE_HWORD : in std_logic; -- Write a 16bit word as specified in A1
|
||||
CS : in std_logic; -- Chip Select.
|
||||
WREN : in std_logic; -- Write enable.
|
||||
RDEN : in std_logic; -- Read enable.
|
||||
BUSY : out std_logic -- Memory is busy, hold CPU.
|
||||
);
|
||||
end SDRAM;
|
||||
|
||||
architecture Structure of SDRAM is
|
||||
|
||||
-- Constants to define the structure of the SDRAM in bits for provisioning of signals.
|
||||
constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS);
|
||||
constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS);
|
||||
constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS);
|
||||
constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS);
|
||||
constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS);
|
||||
|
||||
-- Command table for a standard SDRAM.
|
||||
--
|
||||
-- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ
|
||||
-- COMMAND INHIBIT (NOP) H H X X X X X X
|
||||
-- NO OPERATION (NOP) H L H H H X X X
|
||||
-- ACTIVE (select bank and activate row) H L L H H X Bank/row X
|
||||
-- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X
|
||||
-- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid
|
||||
-- BURST TERMINATE H L H H L X X Active
|
||||
-- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X
|
||||
-- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X
|
||||
-- LOAD MODE REGISTER H L L L L X Op-code X
|
||||
-- Write enable/output enable H X X X X L X Active
|
||||
-- Write inhibit/output High-Z H X X X X H X High-Z
|
||||
-- Self Refresh Entry L L L L H X X X
|
||||
-- Self Refresh Exit (Device is idle) H H X X X X X X
|
||||
-- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X
|
||||
-- Clock suspend mode Entry L X X X X X X X
|
||||
-- Clock suspend mode Exit H X X X X X X X
|
||||
-- Power down mode Entry (Device is idle) L H X X X X X X
|
||||
-- Power down mode Entry (Device is Active) L L H H X X X X
|
||||
-- Power down mode Exit (Any state) H H X X X X X X
|
||||
-- Power down mode Exit (Device is powered down) H L H H X X X X
|
||||
|
||||
constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111";
|
||||
constant CMD_NOP : std_logic_vector(4 downto 0) := "10111";
|
||||
constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011";
|
||||
constant CMD_READ : std_logic_vector(4 downto 0) := "10101";
|
||||
constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100";
|
||||
constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010";
|
||||
constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001";
|
||||
constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001";
|
||||
constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000";
|
||||
constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000";
|
||||
constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100";
|
||||
|
||||
-- Load Mode Register setting for a standard SDRAM.
|
||||
--
|
||||
-- xx:10 = Reserved :
|
||||
-- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
|
||||
-- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
|
||||
-- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
|
||||
-- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
|
||||
-- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
|
||||
-- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
|
||||
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
|
||||
constant WRITE_BURST_MODE : std_logic := '1';
|
||||
constant OP_MODE : std_logic_vector(1 downto 0) := "00";
|
||||
constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
|
||||
constant BURST_TYPE : std_logic := '0';
|
||||
constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000";
|
||||
constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS));
|
||||
|
||||
-- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time.
|
||||
--
|
||||
constant CYCLE_PRECHARGE : integer := 0; -- 0
|
||||
constant CYCLE_RAS_START : integer := tRP; -- 3
|
||||
constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4
|
||||
constant CYCLE_CAS0 : integer := CYCLE_RAS_START + tRCD; -- 3 + tRCD
|
||||
constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + tRCD
|
||||
constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_END : integer := CYCLE_READ1 + 1; -- 9 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_RFSH_START : integer := tRP; -- tRP
|
||||
constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((tRFC/SDRAM_CLK_FREQ) * 10000000) + tRP + 1; -- tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks.
|
||||
|
||||
-- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is
|
||||
-- the time it takes when a refresh starts to completion.
|
||||
constant REFRESH_PERIOD : integer := (((tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (tRFC * 1000)) / 1000;
|
||||
|
||||
type BankArray is array(natural range 0 to 3) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
|
||||
-- Cache for holding burst reads to allow for differing speeds of WishBone Master.
|
||||
type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal readCache : DataCacheArray;
|
||||
attribute ramstyle : string;
|
||||
attribute ramstyle of readCache : signal is "logic";
|
||||
signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
|
||||
-- SDRAM domain signals.
|
||||
signal sdCycle : integer range 0 to 31;
|
||||
signal sdDone : std_logic;
|
||||
signal sdCmd : std_logic_vector(4 downto 0);
|
||||
signal sdRefreshCount : unsigned(11 downto 0);
|
||||
signal sdAutoRefresh : std_logic;
|
||||
signal sdResetTimer : unsigned(7 downto 0);
|
||||
signal sdMuxAddr : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); -- 12+ bit multiplexed address bus
|
||||
signal sdDoneLast : std_logic;
|
||||
signal sdInResetCounter : unsigned(7 downto 0);
|
||||
signal isReady : std_logic;
|
||||
signal sdDataOut : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0);
|
||||
signal sdDataIn : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0);
|
||||
signal sdActiveRow : BankArray;
|
||||
signal sdActiveBank : std_logic_vector(1 downto 0);
|
||||
signal cpuBank : natural range 0 to 3;
|
||||
signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0);
|
||||
signal sdDQM : std_logic_vector(1 downto 0);
|
||||
|
||||
-- CPU domain signals.
|
||||
signal cpuBusy : std_logic;
|
||||
signal cpuDQM : std_logic_vector(3 downto 0);
|
||||
signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal cpuIsWriting : std_logic;
|
||||
|
||||
signal cpuReq : std_logic;
|
||||
signal cpuLastEN : std_logic;
|
||||
signal sdReqLast : std_logic;
|
||||
signal sdAck : std_logic;
|
||||
signal cpuDoneAck : std_logic;
|
||||
|
||||
type ramArray is array(natural range 0 to SDRAM_COLUMNS) of std_logic_vector(WORD_32BIT_RANGE);
|
||||
type ramCtrl is array(0 downto 0) of std_logic_vector(SDRAM_ADDR_BITS downto 0);
|
||||
|
||||
shared variable READRAM : ramArray :=
|
||||
(
|
||||
others => X"00000000"
|
||||
);
|
||||
|
||||
shared variable WRITERAM : ramArray :=
|
||||
(
|
||||
others => X"00000000"
|
||||
);
|
||||
shared variable WRITECTRL : ramCtrl :=
|
||||
(
|
||||
others => (others => '0')
|
||||
);
|
||||
shared variable READCTRL : ramCtrl :=
|
||||
(
|
||||
others => (others => '0')
|
||||
);
|
||||
|
||||
signal cpuReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS);
|
||||
signal sdReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS);
|
||||
signal fifoSdWREN : std_logic;
|
||||
signal fifoCpuWREN : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- Tri-state control of the SDRAM data bus.
|
||||
-- process(cpuIsWriting, SDRAM_DQ, sdDataOut)
|
||||
-- begin
|
||||
-- if (cpuIsWriting = '1') then
|
||||
-- SDRAM_DQ <= sdDataOut;
|
||||
-- sdDataIn <= SDRAM_DQ;
|
||||
-- else
|
||||
-- SDRAM_DQ <= (others => 'Z');
|
||||
-- sdDataIn <= SDRAM_DQ;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
-- SDRAM Side of dual port RAM.
|
||||
-- For Read: sdDataOut <= FIFO(sdFifoAddr)
|
||||
-- For WriteL FIFO(sdFifoAddr) <= sdDataIn
|
||||
-- process(SDRAM_CLK)
|
||||
-- begin
|
||||
-- if rising_edge(SDRAM_CLK) then
|
||||
-- if fifoSdWREN = '1' then
|
||||
-- FIFO(to_integer(unsigned(sdWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := sdDataIn;
|
||||
-- sdDataOut(WORD_32BIT_RANGE) <= sdDataIn;
|
||||
-- else
|
||||
-- sdDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(sdReadColumnAddr(SDRAM_COLUMN-1 downto 0))));
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
-- Main FSM for SDRAM control and refresh.
|
||||
process(ALL)
|
||||
begin
|
||||
if (cpuIsWriting = '1') then
|
||||
SDRAM_DQ <= sdDataOut;
|
||||
else
|
||||
SDRAM_DQ <= (others => 'Z');
|
||||
end if;
|
||||
sdDataIn <= SDRAM_DQ;
|
||||
|
||||
if (SDRAM_RST = '1') then
|
||||
sdResetTimer <= (others => '0'); -- 0 upto 127
|
||||
sdInResetCounter <= (others => '1'); -- 255 downto 0
|
||||
sdMuxAddr <= (others => '0');
|
||||
sdAutoRefresh <= '0';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
isReady <= '0';
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
SDRAM_DQM <= (others => '1');
|
||||
sdCycle <= 0;
|
||||
sdDone <= '0';
|
||||
cacheWriteAddr <= (others => '0');
|
||||
sdAck <= '0';
|
||||
sdReqLast <= '0';
|
||||
|
||||
elsif rising_edge(SDRAM_CLK) then
|
||||
|
||||
-- If no specific command given the default is NOP.
|
||||
sdCmd <= CMD_NOP;
|
||||
|
||||
-- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied.
|
||||
if (isReady = '0') then
|
||||
sdResetTimer <= sdResetTimer + 1;
|
||||
|
||||
-- 1uS timer.
|
||||
if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then
|
||||
sdResetTimer <= (others => '0');
|
||||
sdInResetCounter <= sdInResetCounter - 1;
|
||||
end if;
|
||||
|
||||
-- Every 1uS check for the next init action.
|
||||
if (sdResetTimer = 0) then
|
||||
|
||||
-- 200uS wait, no action as the SDRAM starts up.
|
||||
-- ie. 255 downto 55
|
||||
|
||||
-- Precharge all banks
|
||||
if(sdInResetCounter = 55) then
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- Load the Mode register with our parameters.
|
||||
if(sdInResetCounter = 39) then
|
||||
sdCmd <= CMD_LOAD_MODE;
|
||||
SDRAM_ADDR <= MODE;
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- SDRAM ready.
|
||||
if(sdInResetCounter = 20) then
|
||||
isReady <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
-- Counter to the next auto-refresh in sdram clock ticks.
|
||||
sdRefreshCount <= sdRefreshCount + 1;
|
||||
|
||||
-- Store the CPU request signal state to detect a change.
|
||||
sdReqLast <= cpuReq;
|
||||
|
||||
-- If the CPU makes an SDRAM request and we arent already processing, acknowledge it.
|
||||
-- This mechanism is used to reduce the possibility of metastability issues due to differing clocks.
|
||||
if ((sdReqLast = '0' and cpuReq = '1') and sdAck = '0') then
|
||||
sdAck <= '1';
|
||||
end if;
|
||||
|
||||
-- If the CPU completes its request because it detects the SDRAM ACK, remove the ACK signal as it is no longer needed.
|
||||
if ((sdReqLast = '1' and cpuReq = '0') and sdAck = '1') then
|
||||
sdAck <= '0';
|
||||
end if;
|
||||
|
||||
-- If the SDRAM has completed its transaction and the CPU has acknowledged it, remove the signals.
|
||||
if (sdDone = '1' and cpuDoneAck = '1') then
|
||||
sdDone <= '0';
|
||||
end if;
|
||||
|
||||
-- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are
|
||||
-- issued in a tRFC period. Other bus operations are stalled during this period.
|
||||
if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then
|
||||
sdAutoRefresh <= '1';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
|
||||
-- In auto refresh period.
|
||||
elsif (sdAutoRefresh = '1') then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
when CYCLE_RFSH_START =>
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
|
||||
when CYCLE_RFSH_END =>
|
||||
-- reset the count.
|
||||
sdAutoRefresh <= '0';
|
||||
sdCycle <= 0;
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
-- If we are not acknowledging a CPU request (and signals to stabilize and latch), run the FSM to refresh or service a request.
|
||||
elsif sdAck = '0' then
|
||||
-- if sdAck = '0' then
|
||||
|
||||
if ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
|
||||
when CYCLE_PRECHARGE =>
|
||||
-- If the bank is not open then no need to precharge, move onto RAS.
|
||||
if (sdActiveBank(cpuBank) = '0') then
|
||||
sdCycle <= CYCLE_RAS_START;
|
||||
|
||||
-- If the requested row is already active, go to CAS for immediate access to this row.
|
||||
elsif (sdActiveRow(cpuBank) = cpuRow) then
|
||||
sdCycle <= CYCLE_CAS0;
|
||||
|
||||
-- Otherwise we close out the open bank by issuing a PRECHARGE.
|
||||
else
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '0';
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length));
|
||||
sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active.
|
||||
end if;
|
||||
|
||||
-- Open the requested row.
|
||||
when CYCLE_RAS_START =>
|
||||
sdCmd <= CMD_ACTIVE;
|
||||
SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address.
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select.
|
||||
sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active
|
||||
sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active.
|
||||
|
||||
when CYCLE_RAS_NEXT =>
|
||||
SDRAM_DQM <= "11"; -- Set DQ to tri--state.
|
||||
|
||||
-- this is the first CAS cycle
|
||||
when CYCLE_CAS0 =>
|
||||
-- Process on a 32bit boundary, this core is originally intended for a a 16bit chip so we need 2 accesses for a 32bit alignment, for a 32bit chip, remove CAS1 (TODO: Auto enable logic based on datawidth).
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
-- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
|
||||
|
||||
SDRAM_DQM <= not cpuDQM(3 downto 2);
|
||||
sdDataOut <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus.
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (cpuIsWriting = '1') then
|
||||
sdCmd <= CMD_WRITE;
|
||||
else
|
||||
-- Setup for a read.
|
||||
sdCmd <= CMD_READ;
|
||||
SDRAM_DQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
when CYCLE_CAS1 =>
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge
|
||||
-- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
|
||||
|
||||
SDRAM_DQM <= not cpuDQM(1 downto 0);
|
||||
sdDataOut <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0);
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (cpuIsWriting = '1') then
|
||||
sdCmd <= CMD_WRITE;
|
||||
-- sdDone <= '1'; --not sdDone;
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
-- Setup for a read, change to write if flag set.
|
||||
sdCmd <= CMD_READ;
|
||||
SDRAM_DQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
-- Data is available CAS Latency clocks after the read request.
|
||||
when CYCLE_READ0 =>
|
||||
-- If writing, then we are complete, exit else read the first word.
|
||||
if (cpuIsWriting = '1') then
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
cpuDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= sdDataIn;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ1 =>
|
||||
-- If writing, then we are complete, exit else read the first word.
|
||||
if (cpuIsWriting = '1') then
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
cpuDataOut(SDRAM_DATAWIDTH-1 downto 0) <= sdDataIn;
|
||||
end if;
|
||||
|
||||
when CYCLE_END =>
|
||||
sdDone <= '1'; --not sdDone;
|
||||
sdCycle <= 0;
|
||||
|
||||
-- Other states are wait states, waiting for the correct time slot for SDRAM access.
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
sdCycle <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- CPU Side of dual port RAM.
|
||||
-- For Read: cpuDataOut <= FIFO(cpuFifoAddr)
|
||||
-- For Write: FIFO(cpuFifoAddr) <= cpuDataIn
|
||||
-- process(CLK)
|
||||
-- begin
|
||||
-- if rising_edge(CLK) then
|
||||
-- if fifoCpuWREN = '1' then
|
||||
-- FIFO(to_integer(unsigned(cpuWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := cpuDataIn;
|
||||
-- cpuDataOut(WORD_32BIT_RANGE) <= cpuDataIn;
|
||||
-- else
|
||||
-- cpuDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(cpuReadColumnAddr(SDRAM_COLUMN-1 downto 0))));
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
-- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent
|
||||
-- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know
|
||||
-- when the transation is complete and data read.
|
||||
--
|
||||
process(ALL)
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
sdDoneLast <= '0';
|
||||
cpuBusy <= '0';
|
||||
cpuBank <= 0;
|
||||
cpuRow <= (others => '0');
|
||||
cpuCol <= (others => '0');
|
||||
cpuDQM <= (others => '1');
|
||||
cpuDoneAck <= '0';
|
||||
cpuReq <= '0';
|
||||
cpuLastEN <= '0';
|
||||
|
||||
-- If the SDRAM isnt ready, we can only wait.
|
||||
elsif isReady = '0' then
|
||||
|
||||
elsif rising_edge(CLK) then
|
||||
|
||||
-- Preserve current enable state to detect activation.
|
||||
cpuLastEN <= RDEN or WREN;
|
||||
|
||||
-- Detect a Chip Select state change signalling access.
|
||||
if cpuLastEN = '0' and (RDEN = '1' or WREN = '1') then
|
||||
cpuBusy <= '1';
|
||||
cpuIsWriting <= WREN;
|
||||
cpuBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS downto SDRAM_ARRAY_BITS+1)));
|
||||
cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS));
|
||||
cpuCol <= ADDR(SDRAM_COLUMN_BITS downto 2) & '0';
|
||||
cpuReq <= '1';
|
||||
|
||||
-- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values.
|
||||
if(WRITE_BYTE = '1') then
|
||||
case ADDR(1 downto 0) is
|
||||
when "00" => cpuDQM <= "1000";
|
||||
cpuDataIn <= DATA_IN(7 downto 0) & X"000000";
|
||||
when "01" => cpuDQM <= "0100";
|
||||
cpuDataIn <= X"00" & DATA_IN(7 downto 0) & X"0000";
|
||||
when "10" => cpuDQM <= "0010";
|
||||
cpuDataIn <= X"0000" & DATA_IN(7 downto 0) & X"00";
|
||||
when "11" => cpuDQM <= "0001";
|
||||
cpuDataIn <= X"000000" & DATA_IN(7 downto 0);
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif(WRITE_HWORD = '1') then
|
||||
|
||||
case ADDR(1) is
|
||||
when '0' => cpuDQM <= "1100";
|
||||
cpuDataIn <= DATA_IN(15 downto 0) & X"0000";
|
||||
when '1' => cpuDQM <= "0011";
|
||||
cpuDataIn <= X"0000" & DATA_IN(15 downto 0);
|
||||
end case;
|
||||
|
||||
else
|
||||
-- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit.
|
||||
cpuDataIn <= DATA_IN(31 downto 0);
|
||||
cpuDQM <= "1111";
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if cpuReq = '1' and sdAck = '1' then
|
||||
cpuReq <= '0';
|
||||
end if;
|
||||
|
||||
-- Note SDRAM activity via a previous/last signal.
|
||||
sdDoneLast <= sdDone;
|
||||
|
||||
-- If there has been a change in the SDRAM done activity reset the signals as initiated transaction is complete.
|
||||
if (sdDoneLast = '0' and sdDone = '1') then
|
||||
cpuDoneAck <= '1';
|
||||
end if;
|
||||
|
||||
if (sdDoneLast = '1' and sdDone = '0' and cpuDoneAck = '1') then
|
||||
cpuDoneAck <= '0';
|
||||
cpuBusy <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Assign stored data to the CPU bus to be read.
|
||||
DATA_OUT <= cpuDataOut;
|
||||
|
||||
-- drive control signals according to current command
|
||||
SDRAM_CKE <= sdCmd(4);
|
||||
SDRAM_CS_n <= sdCmd(3);
|
||||
SDRAM_RAS_n <= sdCmd(2);
|
||||
SDRAM_CAS_n <= sdCmd(1);
|
||||
SDRAM_WE_n <= sdCmd(0);
|
||||
-- SDRAM_DQM <= sdDQM;
|
||||
-- SDRAM_ADDR <= sdMuxAddr;
|
||||
|
||||
-- System bus control signals.
|
||||
BUSY <= '1' when (cpuLastEN = '0' and (RDEN = '1' or WREN = '1')) else cpuBusy;
|
||||
SDRAM_READY <= isReady;
|
||||
|
||||
end Structure;
|
||||
@@ -1 +0,0 @@
|
||||
set tool_name "ModelSim-Altera (VHDL)"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,576 +0,0 @@
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE revB2 I2C Master Core; bit-controller ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- Author: Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- www.asics.ws ----
|
||||
---- ----
|
||||
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2000 Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer.----
|
||||
---- ----
|
||||
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
||||
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
||||
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
||||
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
||||
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
||||
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
||||
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
||||
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
||||
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
||||
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
||||
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
||||
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
||||
---- POSSIBILITY OF SUCH DAMAGE. ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
|
||||
-- CVS Log
|
||||
--
|
||||
-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
|
||||
--
|
||||
-- $Date: 2009-02-04 20:17:34 $
|
||||
-- $Revision: 1.17 $
|
||||
-- $Author: rherveille $
|
||||
-- $Locker: $
|
||||
-- $State: Exp $
|
||||
--
|
||||
-- Change History:
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.16 2009/01/20 20:40:36 rherveille
|
||||
-- Fixed type iscl_oen instead of scl_oen
|
||||
--
|
||||
-- Revision 1.15 2009/01/20 10:34:51 rherveille
|
||||
-- Added SCL clock synchronization logic
|
||||
-- Fixed slave_wait signal generation
|
||||
--
|
||||
-- Revision 1.14 2006/10/11 12:10:13 rherveille
|
||||
-- Added missing semicolons ';' on endif
|
||||
--
|
||||
-- Revision 1.13 2006/10/06 10:48:24 rherveille
|
||||
-- fixed short scl high pulse after clock stretch
|
||||
--
|
||||
-- Revision 1.12 2004/05/07 11:53:31 rherveille
|
||||
-- Fixed previous fix :) Made a variable vs signal mistake.
|
||||
--
|
||||
-- Revision 1.11 2004/05/07 11:04:00 rherveille
|
||||
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
|
||||
--
|
||||
-- Revision 1.10 2004/02/27 07:49:43 rherveille
|
||||
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
|
||||
--
|
||||
-- Revision 1.9 2003/08/12 14:48:37 rherveille
|
||||
-- Forgot an 'end if' :-/
|
||||
--
|
||||
-- Revision 1.8 2003/08/09 07:01:13 rherveille
|
||||
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
||||
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
|
||||
--
|
||||
-- Revision 1.7 2003/02/05 00:06:02 rherveille
|
||||
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
|
||||
--
|
||||
-- Revision 1.6 2003/02/01 02:03:06 rherveille
|
||||
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
|
||||
--
|
||||
-- Revision 1.5 2002/12/26 16:05:47 rherveille
|
||||
-- Core is now a Multimaster I2C controller.
|
||||
--
|
||||
-- Revision 1.4 2002/11/30 22:24:37 rherveille
|
||||
-- Cleaned up code
|
||||
--
|
||||
-- Revision 1.3 2002/10/30 18:09:53 rherveille
|
||||
-- Fixed some reported minor start/stop generation timing issuess.
|
||||
--
|
||||
-- Revision 1.2 2002/06/15 07:37:04 rherveille
|
||||
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
||||
--
|
||||
-- Revision 1.1 2001/11/05 12:02:33 rherveille
|
||||
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
|
||||
-- Code updated, is now up-to-date to doc. rev.0.4.
|
||||
-- Added headers.
|
||||
--
|
||||
|
||||
|
||||
--
|
||||
-------------------------------------
|
||||
-- Bit controller section
|
||||
------------------------------------
|
||||
--
|
||||
-- Translate simple commands into SCL/SDA transitions
|
||||
-- Each command has 5 states, A/B/C/D/idle
|
||||
--
|
||||
-- start: SCL ~~~~~~~~~~~~~~\____
|
||||
-- SDA XX/~~~~~~~\______
|
||||
-- x | A | B | C | D | i
|
||||
--
|
||||
-- repstart SCL ______/~~~~~~~\___
|
||||
-- SDA __/~~~~~~~\______
|
||||
-- x | A | B | C | D | i
|
||||
--
|
||||
-- stop SCL _______/~~~~~~~~~~~
|
||||
-- SDA ==\___________/~~~~~
|
||||
-- x | A | B | C | D | i
|
||||
--
|
||||
--- write SCL ______/~~~~~~~\____
|
||||
-- SDA XXX===============XX
|
||||
-- x | A | B | C | D | i
|
||||
--
|
||||
--- read SCL ______/~~~~~~~\____
|
||||
-- SDA XXXXXXX=XXXXXXXXXXX
|
||||
-- x | A | B | C | D | i
|
||||
--
|
||||
|
||||
-- Timing: Normal mode Fast mode
|
||||
-----------------------------------------------------------------
|
||||
-- Fscl 100KHz 400KHz
|
||||
-- Th_scl 4.0us 0.6us High period of SCL
|
||||
-- Tl_scl 4.7us 1.3us Low period of SCL
|
||||
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
||||
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
|
||||
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2c_master_bit_ctrl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
nReset : in std_logic;
|
||||
ena : in std_logic; -- core enable signal
|
||||
|
||||
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
||||
|
||||
cmd : in std_logic_vector(3 downto 0);
|
||||
cmd_ack : out std_logic; -- command completed
|
||||
busy : out std_logic; -- i2c bus busy
|
||||
al : out std_logic; -- arbitration lost
|
||||
|
||||
din : in std_logic;
|
||||
dout : out std_logic;
|
||||
|
||||
-- i2c lines
|
||||
scl_i : in std_logic; -- i2c clock line input
|
||||
scl_o : out std_logic; -- i2c clock line output
|
||||
scl_oen : out std_logic; -- i2c clock line output enable, active low
|
||||
sda_i : in std_logic; -- i2c data line input
|
||||
sda_o : out std_logic; -- i2c data line output
|
||||
sda_oen : out std_logic -- i2c data line output enable, active low
|
||||
);
|
||||
end entity i2c_master_bit_ctrl;
|
||||
|
||||
architecture structural of i2c_master_bit_ctrl is
|
||||
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
|
||||
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
|
||||
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
|
||||
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
|
||||
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
|
||||
|
||||
type states is (idle, start_a, start_b, start_c, start_d, start_e,
|
||||
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
|
||||
signal c_state : states;
|
||||
|
||||
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
|
||||
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
|
||||
signal dscl_oen : std_logic; -- delayed scl_oen signals
|
||||
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
|
||||
signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
|
||||
signal clk_en : std_logic; -- statemachine clock enable
|
||||
signal scl_sync, slave_wait : std_logic; -- clock generation signals
|
||||
signal ial : std_logic; -- internal arbitration lost signal
|
||||
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
|
||||
|
||||
begin
|
||||
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
|
||||
-- delay scl_oen
|
||||
process (clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
dscl_oen <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
dscl_oen <= iscl_oen;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
|
||||
-- slave_wait remains asserted until the slave releases SCL
|
||||
process (clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
slave_wait <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- master drives SCL high, but another master pulls it low
|
||||
-- master start counting down its low cycle now (clock synchronization)
|
||||
scl_sync <= dSCL and not sSCL and iscl_oen;
|
||||
|
||||
-- generate clk enable signal
|
||||
gen_clken: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
cnt <= (others => '0');
|
||||
clk_en <= '1';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
|
||||
cnt <= clk_cnt;
|
||||
clk_en <= '1';
|
||||
elsif (slave_wait = '1') then
|
||||
cnt <= cnt;
|
||||
clk_en <= '0';
|
||||
else
|
||||
cnt <= cnt -1;
|
||||
clk_en <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process gen_clken;
|
||||
|
||||
|
||||
-- generate bus status controller
|
||||
bus_status_ctrl: block
|
||||
signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
|
||||
signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
|
||||
signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
|
||||
signal sta_condition : std_logic; -- start detected
|
||||
signal sto_condition : std_logic; -- stop detected
|
||||
signal cmd_stop : std_logic; -- STOP command
|
||||
signal ibusy : std_logic; -- internal busy signal
|
||||
begin
|
||||
-- capture SCL and SDA
|
||||
capture_scl_sda: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
cSCL <= "00";
|
||||
cSDA <= "00";
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
cSCL <= "00";
|
||||
cSDA <= "00";
|
||||
else
|
||||
cSCL <= (cSCL(0) & scl_i);
|
||||
cSDA <= (cSDA(0) & sda_i);
|
||||
end if;
|
||||
end if;
|
||||
end process capture_scl_sda;
|
||||
|
||||
-- filter SCL and SDA; (attempt to) remove glitches
|
||||
filter_divider: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
filter_cnt <= (others => '0');
|
||||
elsif (clk'event and clk = '1') then
|
||||
if ( (rst = '1') or (ena = '0') ) then
|
||||
filter_cnt <= (others => '0');
|
||||
elsif (filter_cnt = 0) then
|
||||
filter_cnt <= clk_cnt(15 downto 2);
|
||||
else
|
||||
filter_cnt <= filter_cnt -1;
|
||||
end if;
|
||||
end if;
|
||||
end process filter_divider;
|
||||
|
||||
filter_scl_sda: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
fSCL <= (others => '1');
|
||||
fSDA <= (others => '1');
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
fSCL <= (others => '1');
|
||||
fSDA <= (others => '1');
|
||||
elsif (filter_cnt = 0) then
|
||||
fSCL <= (fSCL(1 downto 0) & cSCL(1));
|
||||
fSDA <= (fSDA(1 downto 0) & cSDA(1));
|
||||
end if;
|
||||
end if;
|
||||
end process filter_scl_sda;
|
||||
|
||||
-- generate filtered SCL and SDA signals
|
||||
scl_sda: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
sSCL <= '1';
|
||||
sSDA <= '1';
|
||||
|
||||
dSCL <= '1';
|
||||
dSDA <= '1';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
sSCL <= '1';
|
||||
sSDA <= '1';
|
||||
|
||||
dSCL <= '1';
|
||||
dSDA <= '1';
|
||||
else
|
||||
sSCL <= (fSCL(2) and fSCL(1)) or
|
||||
(fSCL(2) and fSCL(0)) or
|
||||
(fSCL(1) and fSCL(0));
|
||||
sSDA <= (fSDA(2) and fSDA(1)) or
|
||||
(fSDA(2) and fSDA(0)) or
|
||||
(fSDA(1) and fSDA(0));
|
||||
|
||||
dSCL <= sSCL;
|
||||
dSDA <= sSDA;
|
||||
end if;
|
||||
end if;
|
||||
end process scl_sda;
|
||||
|
||||
|
||||
-- detect start condition => detect falling edge on SDA while SCL is high
|
||||
-- detect stop condition => detect rising edge on SDA while SCL is high
|
||||
detect_sta_sto: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
sta_condition <= '0';
|
||||
sto_condition <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
sta_condition <= '0';
|
||||
sto_condition <= '0';
|
||||
else
|
||||
sta_condition <= (not sSDA and dSDA) and sSCL;
|
||||
sto_condition <= (sSDA and not dSDA) and sSCL;
|
||||
end if;
|
||||
end if;
|
||||
end process detect_sta_sto;
|
||||
|
||||
|
||||
-- generate i2c-bus busy signal
|
||||
gen_busy: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
ibusy <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
ibusy <= '0';
|
||||
else
|
||||
ibusy <= (sta_condition or ibusy) and not sto_condition;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_busy;
|
||||
busy <= ibusy;
|
||||
|
||||
|
||||
-- generate arbitration lost signal
|
||||
-- aribitration lost when:
|
||||
-- 1) master drives SDA high, but the i2c bus is low
|
||||
-- 2) stop detected while not requested (detect during 'idle' state)
|
||||
gen_al: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
cmd_stop <= '0';
|
||||
ial <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
cmd_stop <= '0';
|
||||
ial <= '0';
|
||||
else
|
||||
if (clk_en = '1') then
|
||||
if (cmd = I2C_CMD_STOP) then
|
||||
cmd_stop <= '1';
|
||||
else
|
||||
cmd_stop <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if (c_state = idle) then
|
||||
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
|
||||
else
|
||||
ial <= (sda_chk and not sSDA and isda_oen);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_al;
|
||||
al <= ial;
|
||||
|
||||
|
||||
-- generate dout signal, store dout on rising edge of SCL
|
||||
gen_dout: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
dout <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (sSCL = '1' and dSCL = '0') then
|
||||
dout <= sSDA;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_dout;
|
||||
end block bus_status_ctrl;
|
||||
|
||||
|
||||
-- generate statemachine
|
||||
nxt_state_decoder : process (clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
c_state <= idle;
|
||||
cmd_ack <= '0';
|
||||
iscl_oen <= '1';
|
||||
isda_oen <= '1';
|
||||
sda_chk <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1' or ial = '1') then
|
||||
c_state <= idle;
|
||||
cmd_ack <= '0';
|
||||
iscl_oen <= '1';
|
||||
isda_oen <= '1';
|
||||
sda_chk <= '0';
|
||||
else
|
||||
cmd_ack <= '0'; -- default no acknowledge
|
||||
|
||||
if (clk_en = '1') then
|
||||
case (c_state) is
|
||||
-- idle
|
||||
when idle =>
|
||||
case cmd is
|
||||
when I2C_CMD_START => c_state <= start_a;
|
||||
when I2C_CMD_STOP => c_state <= stop_a;
|
||||
when I2C_CMD_WRITE => c_state <= wr_a;
|
||||
when I2C_CMD_READ => c_state <= rd_a;
|
||||
when others => c_state <= idle; -- NOP command
|
||||
end case;
|
||||
|
||||
iscl_oen <= iscl_oen; -- keep SCL in same state
|
||||
isda_oen <= isda_oen; -- keep SDA in same state
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
-- start
|
||||
when start_a =>
|
||||
c_state <= start_b;
|
||||
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
|
||||
isda_oen <= '1'; -- set SDA high
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when start_b =>
|
||||
c_state <= start_c;
|
||||
iscl_oen <= '1'; -- set SCL high
|
||||
isda_oen <= '1'; -- keep SDA high
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when start_c =>
|
||||
c_state <= start_d;
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= '0'; -- set SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when start_d =>
|
||||
c_state <= start_e;
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= '0'; -- keep SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when start_e =>
|
||||
c_state <= idle;
|
||||
cmd_ack <= '1'; -- command completed
|
||||
iscl_oen <= '0'; -- set SCL low
|
||||
isda_oen <= '0'; -- keep SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
-- stop
|
||||
when stop_a =>
|
||||
c_state <= stop_b;
|
||||
iscl_oen <= '0'; -- keep SCL low
|
||||
isda_oen <= '0'; -- set SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when stop_b =>
|
||||
c_state <= stop_c;
|
||||
iscl_oen <= '1'; -- set SCL high
|
||||
isda_oen <= '0'; -- keep SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when stop_c =>
|
||||
c_state <= stop_d;
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= '0'; -- keep SDA low
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when stop_d =>
|
||||
c_state <= idle;
|
||||
cmd_ack <= '1'; -- command completed
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= '1'; -- set SDA high
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
-- read
|
||||
when rd_a =>
|
||||
c_state <= rd_b;
|
||||
iscl_oen <= '0'; -- keep SCL low
|
||||
isda_oen <= '1'; -- tri-state SDA
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when rd_b =>
|
||||
c_state <= rd_c;
|
||||
iscl_oen <= '1'; -- set SCL high
|
||||
isda_oen <= '1'; -- tri-state SDA
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when rd_c =>
|
||||
c_state <= rd_d;
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= '1'; -- tri-state SDA
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
when rd_d =>
|
||||
c_state <= idle;
|
||||
cmd_ack <= '1'; -- command completed
|
||||
iscl_oen <= '0'; -- set SCL low
|
||||
isda_oen <= '1'; -- tri-state SDA
|
||||
sda_chk <= '0'; -- don't check SDA
|
||||
|
||||
-- write
|
||||
when wr_a =>
|
||||
c_state <= wr_b;
|
||||
iscl_oen <= '0'; -- keep SCL low
|
||||
isda_oen <= din; -- set SDA
|
||||
sda_chk <= '0'; -- don't check SDA (SCL low)
|
||||
|
||||
when wr_b =>
|
||||
c_state <= wr_c;
|
||||
iscl_oen <= '1'; -- set SCL high
|
||||
isda_oen <= din; -- keep SDA
|
||||
sda_chk <= '0'; -- don't check SDA yet
|
||||
-- Allow some more time for SDA and SCL to settle
|
||||
|
||||
when wr_c =>
|
||||
c_state <= wr_d;
|
||||
iscl_oen <= '1'; -- keep SCL high
|
||||
isda_oen <= din; -- keep SDA
|
||||
sda_chk <= '1'; -- check SDA
|
||||
|
||||
when wr_d =>
|
||||
c_state <= idle;
|
||||
cmd_ack <= '1'; -- command completed
|
||||
iscl_oen <= '0'; -- set SCL low
|
||||
isda_oen <= din; -- keep SDA
|
||||
sda_chk <= '0'; -- don't check SDA (SCL low)
|
||||
|
||||
when others =>
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process nxt_state_decoder;
|
||||
|
||||
|
||||
-- assign outputs
|
||||
scl_o <= '0';
|
||||
scl_oen <= iscl_oen;
|
||||
sda_o <= '0';
|
||||
sda_oen <= isda_oen;
|
||||
end architecture structural;
|
||||
|
||||
@@ -1,367 +0,0 @@
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- Author: Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- www.asics.ws ----
|
||||
---- ----
|
||||
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2000 Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer.----
|
||||
---- ----
|
||||
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
||||
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
||||
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
||||
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
||||
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
||||
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
||||
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
||||
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
||||
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
||||
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
||||
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
||||
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
||||
---- POSSIBILITY OF SUCH DAMAGE. ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
|
||||
-- CVS Log
|
||||
--
|
||||
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $
|
||||
--
|
||||
-- $Date: 2004-02-18 11:41:48 $
|
||||
-- $Revision: 1.5 $
|
||||
-- $Author: rherveille $
|
||||
-- $Locker: $
|
||||
-- $State: Exp $
|
||||
--
|
||||
-- Change History:
|
||||
-- $Log: not supported by cvs2svn $
|
||||
-- Revision 1.4 2003/08/09 07:01:13 rherveille
|
||||
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
||||
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
|
||||
--
|
||||
-- Revision 1.3 2002/12/26 16:05:47 rherveille
|
||||
-- Core is now a Multimaster I2C controller.
|
||||
--
|
||||
-- Revision 1.2 2002/11/30 22:24:37 rherveille
|
||||
-- Cleaned up code
|
||||
--
|
||||
-- Revision 1.1 2001/11/05 12:02:33 rherveille
|
||||
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
|
||||
-- Code updated, is now up-to-date to doc. rev.0.4.
|
||||
-- Added headers.
|
||||
--
|
||||
|
||||
|
||||
|
||||
|
||||
--
|
||||
------------------------------------------
|
||||
-- Byte controller section
|
||||
------------------------------------------
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2c_master_byte_ctrl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
|
||||
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
|
||||
ena : in std_logic; -- core enable signal
|
||||
|
||||
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
|
||||
|
||||
-- input signals
|
||||
start,
|
||||
stop,
|
||||
read,
|
||||
write,
|
||||
ack_in : std_logic;
|
||||
din : in std_logic_vector(7 downto 0);
|
||||
|
||||
-- output signals
|
||||
cmd_ack : out std_logic; -- command done
|
||||
ack_out : out std_logic;
|
||||
i2c_busy : out std_logic; -- arbitration lost
|
||||
i2c_al : out std_logic; -- i2c bus busy
|
||||
dout : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- i2c lines
|
||||
scl_i : in std_logic; -- i2c clock line input
|
||||
scl_o : out std_logic; -- i2c clock line output
|
||||
scl_oen : out std_logic; -- i2c clock line output enable, active low
|
||||
sda_i : in std_logic; -- i2c data line input
|
||||
sda_o : out std_logic; -- i2c data line output
|
||||
sda_oen : out std_logic -- i2c data line output enable, active low
|
||||
);
|
||||
end entity i2c_master_byte_ctrl;
|
||||
|
||||
architecture structural of i2c_master_byte_ctrl is
|
||||
component i2c_master_bit_ctrl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
nReset : in std_logic;
|
||||
ena : in std_logic; -- core enable signal
|
||||
|
||||
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
||||
|
||||
cmd : in std_logic_vector(3 downto 0);
|
||||
cmd_ack : out std_logic; -- command done
|
||||
busy : out std_logic; -- i2c bus busy
|
||||
al : out std_logic; -- arbitration lost
|
||||
|
||||
din : in std_logic;
|
||||
dout : out std_logic;
|
||||
|
||||
-- i2c lines
|
||||
scl_i : in std_logic; -- i2c clock line input
|
||||
scl_o : out std_logic; -- i2c clock line output
|
||||
scl_oen : out std_logic; -- i2c clock line output enable, active low
|
||||
sda_i : in std_logic; -- i2c data line input
|
||||
sda_o : out std_logic; -- i2c data line output
|
||||
sda_oen : out std_logic -- i2c data line output enable, active low
|
||||
);
|
||||
end component i2c_master_bit_ctrl;
|
||||
|
||||
-- commands for bit_controller block
|
||||
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
|
||||
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
|
||||
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
|
||||
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
|
||||
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
|
||||
|
||||
-- signals for bit_controller
|
||||
signal core_cmd : std_logic_vector(3 downto 0);
|
||||
signal core_ack, core_txd, core_rxd : std_logic;
|
||||
signal al : std_logic;
|
||||
|
||||
-- signals for shift register
|
||||
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
|
||||
signal shift, ld : std_logic;
|
||||
|
||||
-- signals for state machine
|
||||
signal go, host_ack : std_logic;
|
||||
signal dcnt : unsigned(2 downto 0); -- data counter
|
||||
signal cnt_done : std_logic;
|
||||
|
||||
begin
|
||||
-- hookup bit_controller
|
||||
bit_ctrl: i2c_master_bit_ctrl port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
nReset => nReset,
|
||||
ena => ena,
|
||||
clk_cnt => clk_cnt,
|
||||
cmd => core_cmd,
|
||||
cmd_ack => core_ack,
|
||||
busy => i2c_busy,
|
||||
al => al,
|
||||
din => core_txd,
|
||||
dout => core_rxd,
|
||||
scl_i => scl_i,
|
||||
scl_o => scl_o,
|
||||
scl_oen => scl_oen,
|
||||
sda_i => sda_i,
|
||||
sda_o => sda_o,
|
||||
sda_oen => sda_oen
|
||||
);
|
||||
i2c_al <= al;
|
||||
|
||||
-- generate host-command-acknowledge
|
||||
cmd_ack <= host_ack;
|
||||
|
||||
-- generate go-signal
|
||||
go <= (read or write or stop) and not host_ack;
|
||||
|
||||
-- assign Dout output to shift-register
|
||||
dout <= sr;
|
||||
|
||||
-- generate shift register
|
||||
shift_register: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
sr <= (others => '0');
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
sr <= (others => '0');
|
||||
elsif (ld = '1') then
|
||||
sr <= din;
|
||||
elsif (shift = '1') then
|
||||
sr <= (sr(6 downto 0) & core_rxd);
|
||||
end if;
|
||||
end if;
|
||||
end process shift_register;
|
||||
|
||||
-- generate data-counter
|
||||
data_cnt: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
dcnt <= (others => '0');
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1') then
|
||||
dcnt <= (others => '0');
|
||||
elsif (ld = '1') then
|
||||
dcnt <= (others => '1'); -- load counter with 7
|
||||
elsif (shift = '1') then
|
||||
dcnt <= dcnt -1;
|
||||
end if;
|
||||
end if;
|
||||
end process data_cnt;
|
||||
|
||||
cnt_done <= '1' when (dcnt = 0) else '0';
|
||||
|
||||
--
|
||||
-- state machine
|
||||
--
|
||||
statemachine : block
|
||||
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
|
||||
signal c_state : states;
|
||||
begin
|
||||
--
|
||||
-- command interpreter, translate complex commands into simpler I2C commands
|
||||
--
|
||||
nxt_state_decoder: process(clk, nReset)
|
||||
begin
|
||||
if (nReset = '0') then
|
||||
core_cmd <= I2C_CMD_NOP;
|
||||
core_txd <= '0';
|
||||
shift <= '0';
|
||||
ld <= '0';
|
||||
host_ack <= '0';
|
||||
c_state <= st_idle;
|
||||
ack_out <= '0';
|
||||
elsif (clk'event and clk = '1') then
|
||||
if (rst = '1' or al = '1') then
|
||||
core_cmd <= I2C_CMD_NOP;
|
||||
core_txd <= '0';
|
||||
shift <= '0';
|
||||
ld <= '0';
|
||||
host_ack <= '0';
|
||||
c_state <= st_idle;
|
||||
ack_out <= '0';
|
||||
else
|
||||
-- initialy reset all signal
|
||||
core_txd <= sr(7);
|
||||
shift <= '0';
|
||||
ld <= '0';
|
||||
host_ack <= '0';
|
||||
|
||||
case c_state is
|
||||
when st_idle =>
|
||||
if (go = '1') then
|
||||
if (start = '1') then
|
||||
c_state <= st_start;
|
||||
core_cmd <= I2C_CMD_START;
|
||||
elsif (read = '1') then
|
||||
c_state <= st_read;
|
||||
core_cmd <= I2C_CMD_READ;
|
||||
elsif (write = '1') then
|
||||
c_state <= st_write;
|
||||
core_cmd <= I2C_CMD_WRITE;
|
||||
else -- stop
|
||||
c_state <= st_stop;
|
||||
core_cmd <= I2C_CMD_STOP;
|
||||
end if;
|
||||
|
||||
ld <= '1';
|
||||
end if;
|
||||
|
||||
when st_start =>
|
||||
if (core_ack = '1') then
|
||||
if (read = '1') then
|
||||
c_state <= st_read;
|
||||
core_cmd <= I2C_CMD_READ;
|
||||
else
|
||||
c_state <= st_write;
|
||||
core_cmd <= I2C_CMD_WRITE;
|
||||
end if;
|
||||
|
||||
ld <= '1';
|
||||
end if;
|
||||
|
||||
when st_write =>
|
||||
if (core_ack = '1') then
|
||||
if (cnt_done = '1') then
|
||||
c_state <= st_ack;
|
||||
core_cmd <= I2C_CMD_READ;
|
||||
else
|
||||
c_state <= st_write; -- stay in same state
|
||||
core_cmd <= I2C_CMD_WRITE; -- write next bit
|
||||
shift <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when st_read =>
|
||||
if (core_ack = '1') then
|
||||
if (cnt_done = '1') then
|
||||
c_state <= st_ack;
|
||||
core_cmd <= I2C_CMD_WRITE;
|
||||
else
|
||||
c_state <= st_read; -- stay in same state
|
||||
core_cmd <= I2C_CMD_READ; -- read next bit
|
||||
end if;
|
||||
|
||||
shift <= '1';
|
||||
core_txd <= ack_in;
|
||||
end if;
|
||||
|
||||
when st_ack =>
|
||||
if (core_ack = '1') then
|
||||
-- check for stop; Should a STOP command be generated ?
|
||||
if (stop = '1') then
|
||||
c_state <= st_stop;
|
||||
core_cmd <= I2C_CMD_STOP;
|
||||
else
|
||||
c_state <= st_idle;
|
||||
core_cmd <= I2C_CMD_NOP;
|
||||
|
||||
-- generate command acknowledge signal
|
||||
host_ack <= '1';
|
||||
end if;
|
||||
|
||||
-- assign ack_out output to core_rxd (contains last received bit)
|
||||
ack_out <= core_rxd;
|
||||
|
||||
core_txd <= '1';
|
||||
else
|
||||
core_txd <= ack_in;
|
||||
end if;
|
||||
|
||||
when st_stop =>
|
||||
if (core_ack = '1') then
|
||||
c_state <= st_idle;
|
||||
core_cmd <= I2C_CMD_NOP;
|
||||
|
||||
-- generate command acknowledge signal
|
||||
host_ack <= '1';
|
||||
end if;
|
||||
|
||||
when others => -- illegal states
|
||||
c_state <= st_idle;
|
||||
core_cmd <= I2C_CMD_NOP;
|
||||
report ("Byte controller entered illegal state.");
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process nxt_state_decoder;
|
||||
|
||||
end block statemachine;
|
||||
|
||||
end architecture structural;
|
||||
|
||||
@@ -1,362 +0,0 @@
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- WISHBONE revB2 compl. I2C Master Core; top level ----
|
||||
---- ----
|
||||
---- ----
|
||||
---- Author: Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- www.asics.ws ----
|
||||
---- ----
|
||||
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
---- ----
|
||||
---- Copyright (C) 2000 Richard Herveille ----
|
||||
---- richard@asics.ws ----
|
||||
---- ----
|
||||
---- This source file may be used and distributed without ----
|
||||
---- restriction provided that this copyright statement is not ----
|
||||
---- removed from the file and that any derivative work contains ----
|
||||
---- the original copyright notice and the associated disclaimer.----
|
||||
---- ----
|
||||
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
||||
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
||||
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
||||
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
||||
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
||||
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
||||
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
||||
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
||||
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
||||
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
||||
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
||||
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
||||
---- POSSIBILITY OF SUCH DAMAGE. ----
|
||||
---- ----
|
||||
---------------------------------------------------------------------
|
||||
|
||||
-- CVS Log
|
||||
--
|
||||
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
|
||||
--
|
||||
-- $Date: 2009-01-20 10:38:45 $
|
||||
-- $Revision: 1.8 $
|
||||
-- $Author: rherveille $
|
||||
-- $Locker: $
|
||||
-- $State: Exp $
|
||||
--
|
||||
-- Change History:
|
||||
-- Revision 1.7 2004/03/14 10:17:03 rherveille
|
||||
-- Fixed simulation issue when writing to CR register
|
||||
--
|
||||
-- Revision 1.6 2003/08/09 07:01:13 rherveille
|
||||
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
||||
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
|
||||
--
|
||||
-- Revision 1.5 2003/02/01 02:03:06 rherveille
|
||||
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
|
||||
--
|
||||
-- Revision 1.4 2002/12/26 16:05:47 rherveille
|
||||
-- Core is now a Multimaster I2C controller.
|
||||
--
|
||||
-- Revision 1.3 2002/11/30 22:24:37 rherveille
|
||||
-- Cleaned up code
|
||||
--
|
||||
-- Revision 1.2 2001/11/10 10:52:44 rherveille
|
||||
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
|
||||
--
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2c_master_top is
|
||||
generic(
|
||||
ARST_LVL : std_logic := '0' -- asynchronous reset level
|
||||
);
|
||||
port (
|
||||
-- wishbone signals
|
||||
wb_clk_i : in std_logic; -- master clock input
|
||||
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
|
||||
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
|
||||
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
|
||||
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
|
||||
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
|
||||
wb_we_i : in std_logic; -- Write enable input
|
||||
wb_stb_i : in std_logic; -- Strobe signals / core select signal
|
||||
wb_cyc_i : in std_logic; -- Valid bus cycle input
|
||||
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
|
||||
wb_inta_o : out std_logic; -- interrupt request output signal
|
||||
|
||||
-- i2c lines
|
||||
scl_pad_i : in std_logic; -- i2c clock line input
|
||||
scl_pad_o : out std_logic; -- i2c clock line output
|
||||
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
|
||||
sda_pad_i : in std_logic; -- i2c data line input
|
||||
sda_pad_o : out std_logic; -- i2c data line output
|
||||
sda_padoen_o : out std_logic -- i2c data line output enable, active low
|
||||
);
|
||||
end entity i2c_master_top;
|
||||
|
||||
architecture structural of i2c_master_top is
|
||||
component i2c_master_byte_ctrl is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
|
||||
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
|
||||
ena : in std_logic; -- core enable signal
|
||||
|
||||
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
|
||||
|
||||
-- input signals
|
||||
start,
|
||||
stop,
|
||||
read,
|
||||
write,
|
||||
ack_in : std_logic;
|
||||
din : in std_logic_vector(7 downto 0);
|
||||
|
||||
-- output signals
|
||||
cmd_ack : out std_logic;
|
||||
ack_out : out std_logic;
|
||||
i2c_busy : out std_logic;
|
||||
i2c_al : out std_logic;
|
||||
dout : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- i2c lines
|
||||
scl_i : in std_logic; -- i2c clock line input
|
||||
scl_o : out std_logic; -- i2c clock line output
|
||||
scl_oen : out std_logic; -- i2c clock line output enable, active low
|
||||
sda_i : in std_logic; -- i2c data line input
|
||||
sda_o : out std_logic; -- i2c data line output
|
||||
sda_oen : out std_logic -- i2c data line output enable, active low
|
||||
);
|
||||
end component i2c_master_byte_ctrl;
|
||||
|
||||
-- registers
|
||||
signal prer : unsigned(15 downto 0); -- clock prescale register
|
||||
signal ctr : std_logic_vector(7 downto 0); -- control register
|
||||
signal txr : std_logic_vector(7 downto 0); -- transmit register
|
||||
signal rxr : std_logic_vector(7 downto 0); -- receive register
|
||||
signal cr : std_logic_vector(7 downto 0); -- command register
|
||||
signal sr : std_logic_vector(7 downto 0); -- status register
|
||||
|
||||
-- internal reset signal
|
||||
signal rst_i : std_logic;
|
||||
|
||||
-- wishbone write access
|
||||
signal wb_wacc : std_logic;
|
||||
|
||||
-- internal acknowledge signal
|
||||
signal iack_o : std_logic;
|
||||
|
||||
-- done signal: command completed, clear command register
|
||||
signal done : std_logic;
|
||||
|
||||
-- command register signals
|
||||
signal sta, sto, rd, wr, ack, iack : std_logic;
|
||||
|
||||
signal core_en : std_logic; -- core enable signal
|
||||
signal ien : std_logic; -- interrupt enable signal
|
||||
|
||||
-- status register signals
|
||||
signal irxack, rxack : std_logic; -- received aknowledge from slave
|
||||
signal tip : std_logic; -- transfer in progress
|
||||
signal irq_flag : std_logic; -- interrupt pending flag
|
||||
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
|
||||
signal i2c_al, al : std_logic; -- arbitration lost
|
||||
|
||||
begin
|
||||
-- generate internal reset signal
|
||||
rst_i <= arst_i xor ARST_LVL;
|
||||
|
||||
-- generate acknowledge output signal
|
||||
gen_ack_o : process(wb_clk_i)
|
||||
begin
|
||||
if (wb_clk_i'event and wb_clk_i = '1') then
|
||||
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
|
||||
end if;
|
||||
end process gen_ack_o;
|
||||
wb_ack_o <= iack_o;
|
||||
|
||||
-- generate wishbone write access signal
|
||||
wb_wacc <= wb_we_i and wb_cyc_i and wb_stb_i;-- and iack_o;
|
||||
|
||||
-- assign wb_dat_o
|
||||
assign_dato : process(wb_clk_i)
|
||||
begin
|
||||
if (wb_clk_i'event and wb_clk_i = '1') then
|
||||
if (wb_we_i = '0') and (wb_cyc_i = '1') and (wb_stb_i = '1') then
|
||||
case wb_adr_i is
|
||||
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
|
||||
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
|
||||
when "010" => wb_dat_o <= ctr;
|
||||
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
|
||||
when "100" => wb_dat_o <= sr; -- write is command register CR
|
||||
|
||||
-- Debugging registers:
|
||||
-- These registers are not documented.
|
||||
-- Functionality could change in future releases
|
||||
when "101" => wb_dat_o <= txr;
|
||||
when "110" => wb_dat_o <= cr;
|
||||
when "111" => wb_dat_o <= (others => '0');
|
||||
when others => wb_dat_o <= (others => '0');
|
||||
end case;
|
||||
else
|
||||
wb_dat_o <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process assign_dato;
|
||||
|
||||
|
||||
-- generate registers (CR, SR see below)
|
||||
gen_regs: process(rst_i, wb_clk_i)
|
||||
begin
|
||||
if (rst_i = '0') then
|
||||
prer <= (others => '1');
|
||||
ctr <= (others => '0');
|
||||
txr <= (others => '0');
|
||||
elsif (wb_clk_i'event and wb_clk_i = '1') then
|
||||
if (wb_rst_i = '1') then
|
||||
prer <= (others => '1');
|
||||
ctr <= (others => '0');
|
||||
txr <= (others => '0');
|
||||
elsif (wb_wacc = '1') then
|
||||
case wb_adr_i is
|
||||
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
|
||||
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
|
||||
when "010" => ctr <= wb_dat_i;
|
||||
when "011" => txr <= wb_dat_i;
|
||||
when "100" => null; --write to CR, avoid executing the others clause
|
||||
|
||||
-- illegal cases, for simulation only
|
||||
when others =>
|
||||
report ("Illegal write address, setting all registers to unknown.");
|
||||
prer <= (others => 'X');
|
||||
ctr <= (others => 'X');
|
||||
txr <= (others => 'X');
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_regs;
|
||||
|
||||
|
||||
-- generate command register
|
||||
gen_cr: process(rst_i, wb_clk_i)
|
||||
begin
|
||||
if (rst_i = '0') then
|
||||
cr <= (others => '0');
|
||||
elsif (wb_clk_i'event and wb_clk_i = '1') then
|
||||
if (wb_rst_i = '1') then
|
||||
cr <= (others => '0');
|
||||
elsif (wb_wacc = '1') then
|
||||
if ( (core_en = '1') and (wb_adr_i = "100") ) then
|
||||
-- only take new commands when i2c core enabled
|
||||
-- pending commands are finished
|
||||
cr <= wb_dat_i;
|
||||
end if;
|
||||
else
|
||||
if (done = '1' or i2c_al = '1') then
|
||||
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
|
||||
end if;
|
||||
|
||||
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
|
||||
cr(0) <= '0'; -- clear IRQ_ACK bit
|
||||
end if;
|
||||
end if;
|
||||
end process gen_cr;
|
||||
|
||||
-- decode command register
|
||||
sta <= cr(7);
|
||||
sto <= cr(6);
|
||||
rd <= cr(5);
|
||||
wr <= cr(4);
|
||||
ack <= cr(3);
|
||||
iack <= cr(0);
|
||||
|
||||
-- decode control register
|
||||
core_en <= ctr(7);
|
||||
ien <= ctr(6);
|
||||
|
||||
-- hookup byte controller block
|
||||
byte_ctrl: i2c_master_byte_ctrl
|
||||
port map (
|
||||
clk => wb_clk_i,
|
||||
rst => wb_rst_i,
|
||||
nReset => rst_i,
|
||||
ena => core_en,
|
||||
clk_cnt => prer,
|
||||
start => sta,
|
||||
stop => sto,
|
||||
read => rd,
|
||||
write => wr,
|
||||
ack_in => ack,
|
||||
i2c_busy => i2c_busy,
|
||||
i2c_al => i2c_al,
|
||||
din => txr,
|
||||
cmd_ack => done,
|
||||
ack_out => irxack,
|
||||
dout => rxr,
|
||||
scl_i => scl_pad_i,
|
||||
scl_o => scl_pad_o,
|
||||
scl_oen => scl_padoen_o,
|
||||
sda_i => sda_pad_i,
|
||||
sda_o => sda_pad_o,
|
||||
sda_oen => sda_padoen_o
|
||||
);
|
||||
|
||||
|
||||
-- status register block + interrupt request signal
|
||||
st_irq_block : block
|
||||
begin
|
||||
-- generate status register bits
|
||||
gen_sr_bits: process (wb_clk_i, rst_i)
|
||||
begin
|
||||
if (rst_i = '0') then
|
||||
al <= '0';
|
||||
rxack <= '0';
|
||||
tip <= '0';
|
||||
irq_flag <= '0';
|
||||
elsif (wb_clk_i'event and wb_clk_i = '1') then
|
||||
if (wb_rst_i = '1') then
|
||||
al <= '0';
|
||||
rxack <= '0';
|
||||
tip <= '0';
|
||||
irq_flag <= '0';
|
||||
else
|
||||
al <= i2c_al or (al and not sta);
|
||||
rxack <= irxack;
|
||||
tip <= (rd or wr);
|
||||
|
||||
-- interrupt request flag is always generated
|
||||
irq_flag <= (done or i2c_al or irq_flag) and not iack;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_sr_bits;
|
||||
|
||||
-- generate interrupt request signals
|
||||
gen_irq: process (wb_clk_i, rst_i)
|
||||
begin
|
||||
if (rst_i = '0') then
|
||||
wb_inta_o <= '0';
|
||||
elsif (wb_clk_i'event and wb_clk_i = '1') then
|
||||
if (wb_rst_i = '1') then
|
||||
wb_inta_o <= '0';
|
||||
else
|
||||
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
|
||||
wb_inta_o <= irq_flag and ien;
|
||||
end if;
|
||||
end if;
|
||||
end process gen_irq;
|
||||
|
||||
-- assign status register bits
|
||||
sr(7) <= rxack;
|
||||
sr(6) <= i2c_busy;
|
||||
sr(5) <= al;
|
||||
sr(4 downto 2) <= (others => '0'); -- reserved
|
||||
sr(1) <= tip;
|
||||
sr(0) <= irq_flag;
|
||||
end block;
|
||||
|
||||
end architecture structural;
|
||||
@@ -1,25 +0,0 @@
|
||||
|
||||
|
||||
-- This code is provided for free and may be used and --
|
||||
-- distributed without restriction provided that the --
|
||||
-- copyright statement is not removed from the file and --
|
||||
-- that any derivative work contains the original --
|
||||
-- copyright notice and the associated disclaimer. --
|
||||
|
||||
-- Comments and suggestions are always welcome --
|
||||
|
||||
The i2c_master core consists of three files:
|
||||
|
||||
- i2c_master_top -- top level
|
||||
- i2c_master_byte_ctrl -- byte controller
|
||||
- i2c_master_bit_ctrl -- bit controller
|
||||
|
||||
VHDL needs to be compiled in order. The files are listed
|
||||
above in descending order.
|
||||
|
||||
I2C.VHD and tst_ds1621.vhd are not supported anymore.
|
||||
They remain mostly for historical purposes, altough they
|
||||
might prove usefull.
|
||||
|
||||
Richard Herveille
|
||||
rherveille@opencores.org
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ]
|
||||
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ]
|
||||
@@ -1,19 +0,0 @@
|
||||
derive_pll_clocks
|
||||
|
||||
#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
create_generated_clock -source [get_pins -compatibility_mode {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
|
||||
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
|
||||
|
||||
# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
|
||||
-to [get_clocks {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
-setup 2
|
||||
|
||||
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
@@ -1,494 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: sdram.vhd
|
||||
-- Created: September 2019
|
||||
-- Original Author: Stephen J. Leary 2013-2014
|
||||
-- VHDL Author: Philip Smart
|
||||
-- Description: Original module written by Stephen J. Leary 2013-2014 in Verilog for use with the
|
||||
-- MT48LC16M16 chip.
|
||||
-- It has been translated into VHDL and undergoing extensive modifications to work
|
||||
-- with the ZPU EVO processor, specifically burst tuning to enhance L2 Cache Fill
|
||||
-- performance.
|
||||
-- Credits:
|
||||
-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved.
|
||||
-- VHDL translation and enhancements (c) 2019 Philip Smart <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial module based on translaction of Stephen J. Leary's Verilog
|
||||
-- source code.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity SDRAM is
|
||||
generic (
|
||||
MAX_DATACACHE_BITS : integer := 4 -- Maximum size in addr bits of 32bit datacache for burst transactions.
|
||||
);
|
||||
port (
|
||||
-- SDRAM Interface
|
||||
SD_CLK : in std_logic; -- sdram is accessed at 100MHz
|
||||
SD_RST : in std_logic; -- reset the sdram controller.
|
||||
SD_CKE : out std_logic; -- clock enable.
|
||||
SD_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
SD_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
|
||||
SD_DQM : out std_logic_vector(1 downto 0); -- two byte masks
|
||||
SD_BA : out std_logic_vector(1 downto 0); -- two banks
|
||||
SD_CS_n : out std_logic; -- a single chip select
|
||||
SD_WE_n : out std_logic; -- write enable
|
||||
SD_RAS_n : out std_logic; -- row address select
|
||||
SD_CAS_n : out std_logic; -- columns address select
|
||||
SD_READY : out std_logic; -- sd ready.
|
||||
|
||||
-- WishBone interface.
|
||||
WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates.
|
||||
WB_DAT_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master
|
||||
WB_DAT_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master
|
||||
WB_ACK_O : out std_logic;
|
||||
WB_ADR_I : in std_logic_vector(23 downto 0); -- lower 2 bits are ignored.
|
||||
WB_SEL_I : in std_logic_vector(3 downto 0);
|
||||
WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst
|
||||
|
||||
WB_STB_I : in std_logic;
|
||||
WB_CYC_I : in std_logic; -- cpu/chipset requests cycle
|
||||
WB_WE_I : in std_logic -- cpu/chipset requests write
|
||||
);
|
||||
end SDRAM;
|
||||
|
||||
architecture Structure of SDRAM is
|
||||
|
||||
-- Constants for register access.
|
||||
--
|
||||
constant RASCAS_DELAY : integer := 3; -- tRCD=20ns -> 2 cycles@100MHz
|
||||
constant RFC_DELAY : integer := 70; -- tRFC=66ns time in nS for a autorefresh to complete.
|
||||
constant RAM_CLK : integer := 100000000;
|
||||
|
||||
-- Command table from the Micron datasheet.
|
||||
-- Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ
|
||||
-- COMMAND INHIBIT (NOP) H X X X X X X
|
||||
-- NO OPERATION (NOP) L H H H X X X
|
||||
-- ACTIVE (select bank and activate row) L L H H X Bank/row X
|
||||
-- READ (select bank and column, and start READ burst) L H L H L/H Bank/col X
|
||||
-- WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid
|
||||
-- BURST TERMINATE L H H L X X Active
|
||||
-- PRECHARGE (Deactivate row in bank or banks) L L H L X Code X
|
||||
-- AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X
|
||||
-- LOAD MODE REGISTER L L L L X Op-code X
|
||||
-- Write enable/output enable X X X X L X Active
|
||||
-- Write inhibit/output High-Z X X X X H X High-Z
|
||||
constant CMD_INHIBIT : std_logic_vector(3 downto 0) := "1111";
|
||||
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
|
||||
constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
|
||||
constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
|
||||
constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
|
||||
constant CMD_BURST_TERMINATE : std_logic_vector(3 downto 0) := "0110";
|
||||
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
|
||||
constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";
|
||||
constant CMD_LOAD_MODE : std_logic_vector(3 downto 0) := "0000";
|
||||
|
||||
-- Load Mode Register setting.
|
||||
-- 12:10 = Reserved :
|
||||
-- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
|
||||
-- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
|
||||
-- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
|
||||
-- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
|
||||
-- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
|
||||
-- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
|
||||
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
|
||||
constant WRITE_BURST_MODE : std_logic := '1';
|
||||
constant OP_MODE : std_logic_vector(1 downto 0) := "00";
|
||||
constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
|
||||
constant BURST_TYPE : std_logic := '0';
|
||||
constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000";
|
||||
constant MODE : std_logic_vector(12 downto 0) := "000" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH;
|
||||
|
||||
-- FSM Cycle States.
|
||||
constant CYCLE_PRECHARGE : integer := 0; -- 0
|
||||
constant CYCLE_RAS_START : integer := 3; -- 3
|
||||
constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4
|
||||
constant CYCLE_CAS0 : integer := CYCLE_RAS_START + RASCAS_DELAY; -- 3 + RASCAS_DELAY
|
||||
constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + RASCAS_DELAY
|
||||
constant CYCLE_CAS2 : integer := CYCLE_CAS1 + 1; -- 5 + RASCAS_DELAY
|
||||
constant CYCLE_CAS3 : integer := CYCLE_CAS2 + 1; -- 6 + RASCAS_DELAY
|
||||
constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + RASCAS_DELAY + CAS_LATENCY
|
||||
constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + RASCAS_DELAY + CAS_LATENCY
|
||||
constant CYCLE_READ2 : integer := CYCLE_READ1 + 1; -- 5 + RASCAS_DELAY + CAS_LATENCY
|
||||
constant CYCLE_READ3 : integer := CYCLE_READ2 + 1; -- 6 + RASCAS_DELAY + CAS_LATENCY
|
||||
constant CYCLE_END : integer := CYCLE_READ3 + 1; -- 9 + RASCAS_DELAY + CAS_LATENCY
|
||||
constant CYCLE_RFSH_START : integer := CYCLE_RAS_START; -- 3
|
||||
constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((RFC_DELAY/RAM_CLK) * 10000000) + 1; -- 3 + RFC_DELAY in clock ticks.
|
||||
|
||||
-- Period in clock cycles between SDRAM refresh cycles.
|
||||
constant REFRESH_PERIOD : integer := (RAM_CLK / (64 * 8192)) - CYCLE_END;
|
||||
|
||||
type BankArray is array(natural range 0 to 3) of std_logic_vector(12 downto 0);
|
||||
|
||||
-- Cache for holding burst reads to allow for differing speeds of WishBone Master.
|
||||
type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal readCache : DataCacheArray;
|
||||
attribute ramstyle : string;
|
||||
attribute ramstyle of readCache : signal is "logic";
|
||||
signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
|
||||
signal sd_dat : std_logic_vector(31 downto 0);
|
||||
signal sd_dat_nxt : std_logic_vector(31 downto 0);
|
||||
signal sd_stb : std_logic;
|
||||
signal sd_we : std_logic;
|
||||
signal sd_cyc : std_logic;
|
||||
signal sd_burst : std_logic;
|
||||
signal sd_cycle : integer range 0 to 31;
|
||||
signal sd_done : std_logic;
|
||||
signal sd_cmd : std_logic_vector(3 downto 0);
|
||||
signal sd_refresh : unsigned(3 downto 0);
|
||||
signal sd_auto_refresh : std_logic;
|
||||
signal sd_req : std_logic_vector(2 downto 0);
|
||||
|
||||
signal sd_in_rst : unsigned(7 downto 0);
|
||||
signal sd_rst_timer : unsigned(6 downto 0);
|
||||
signal sd_active_row : BankArray;
|
||||
signal sd_active_bank : std_logic_vector(1 downto 0);
|
||||
signal sd_bank : natural range 0 to 3;
|
||||
signal sd_row : std_logic_vector(12 downto 0);
|
||||
signal sd_reading : std_logic;
|
||||
signal sd_writing : std_logic;
|
||||
signal sd_rdy : std_logic;
|
||||
signal sd_mxadr : std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
|
||||
signal sd_dout : std_logic_vector(15 downto 0);
|
||||
signal sd_din : std_logic_vector(15 downto 0);
|
||||
signal sd_done_last : std_logic;
|
||||
|
||||
signal burst_mode : std_logic;
|
||||
signal can_burst : std_logic;
|
||||
|
||||
signal wb_ack : std_logic;
|
||||
signal wb_burst : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Tri-state control of the SDRAM data bus.
|
||||
process(sd_writing, SD_DQ, sd_dout)
|
||||
begin
|
||||
if (sd_writing = '0') then
|
||||
SD_DQ <= (others => 'Z');
|
||||
sd_din <= SD_DQ;
|
||||
else
|
||||
SD_DQ <= sd_dout;
|
||||
sd_din <= SD_DQ;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Main FSM for SDRAM control and refresh.
|
||||
process(SD_CLK, SD_RST)
|
||||
begin
|
||||
if (SD_RST = '1') then
|
||||
sd_rst_timer <= (others => '0'); -- 0 upto 127
|
||||
sd_in_rst <= (others => '1'); -- 255 downto 0
|
||||
sd_mxadr <= (others => '0');
|
||||
sd_auto_refresh <= '0';
|
||||
sd_active_bank <= (others => '0');
|
||||
sd_refresh <= (others => '0');
|
||||
sd_active_row <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
sd_rdy <= '0';
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
sd_stb <= '0';
|
||||
sd_cyc <= '0';
|
||||
sd_burst <= '0';
|
||||
sd_we <= '0';
|
||||
sd_cycle <= 0;
|
||||
sd_done <= '0';
|
||||
cacheWriteAddr <= (others => '0');
|
||||
|
||||
elsif rising_edge(SD_CLK) then
|
||||
|
||||
-- If no specific command given the default is NOP.
|
||||
sd_cmd <= CMD_NOP;
|
||||
|
||||
-- Initialisation on power up or reset. The SDRAM must be given at least 100uS to initialise and a fixed setup pattern applied.
|
||||
if (sd_rdy = '0') then
|
||||
sd_rst_timer <= sd_rst_timer + 1;
|
||||
|
||||
-- 1uS timer.
|
||||
if (sd_rst_timer = RAM_CLK/1000000) then
|
||||
sd_rst_timer <= (others => '0');
|
||||
sd_in_rst <= sd_in_rst - 1;
|
||||
end if;
|
||||
|
||||
-- Every 1uS check for the next init action.
|
||||
if (sd_rst_timer = 0) then
|
||||
|
||||
-- 100uS wait, no action as the SDRAM starts up.
|
||||
-- ie. 255 downto 155
|
||||
|
||||
-- Precharge all banks
|
||||
if(sd_in_rst = 155) then
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
sd_mxadr(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- Load the Mode register with our parameters.
|
||||
if(sd_in_rst = 148 or sd_in_rst = 147) then
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
sd_mxadr <= MODE;
|
||||
end if;
|
||||
|
||||
-- 2 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sd_in_rst = 145 or sd_in_rst = 140) then
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- SDRAM ready.
|
||||
if(sd_in_rst = 135) then
|
||||
sd_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
|
||||
-- bring the wishbone bus signal into the ram clock domain.
|
||||
sd_we <= WB_WE_I;
|
||||
if (sd_req = "111") then
|
||||
sd_stb <= WB_STB_I;
|
||||
sd_cyc <= WB_CYC_I;
|
||||
end if;
|
||||
|
||||
sd_refresh <= sd_refresh + 1;
|
||||
|
||||
-- Auto refresh. On timeout it kicks in so that 8192 auto refreshes are
|
||||
-- issued in a 64ms period. Other bus operations are stalled during this period.
|
||||
if ((sd_refresh > REFRESH_PERIOD) and (sd_cycle = 0)) then
|
||||
sd_auto_refresh <= '1';
|
||||
sd_refresh <= (others => '0');
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
sd_mxadr(10) <= '1';
|
||||
sd_active_bank <= (others => '0');
|
||||
|
||||
-- In auto refresh period.
|
||||
elsif (sd_auto_refresh = '1') then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sd_cycle <= sd_cycle + 1;
|
||||
case (sd_cycle) is
|
||||
when CYCLE_RFSH_START =>
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
|
||||
when CYCLE_RFSH_END =>
|
||||
-- reset the count.
|
||||
sd_auto_refresh <= '0';
|
||||
sd_cycle <= 0;
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif (sd_cyc = '1' or (sd_cycle /= 0) or (sd_cycle = 0 and sd_req = "111")) then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sd_cycle <= sd_cycle + 1;
|
||||
case (sd_cycle) is
|
||||
|
||||
when CYCLE_PRECHARGE =>
|
||||
-- If the bank is not open then no need to precharge, move onto RAS.
|
||||
if (sd_active_bank(sd_bank) = '0') then
|
||||
sd_cycle <= CYCLE_RAS_START;
|
||||
--The active row isnt being reset
|
||||
-- If the requested row is already active, go to CAS for immediate access to this row.
|
||||
elsif (sd_active_row(sd_bank) = sd_row) then
|
||||
sd_cycle <= CYCLE_CAS0; -- - 1; -- FIXME: Why doesn't work without -1?
|
||||
|
||||
-- Otherwise we close out the open bank by issuing a PRECHARGE.
|
||||
else
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
sd_mxadr(10) <= '0';
|
||||
SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length));
|
||||
sd_active_bank(sd_bank) <= '0'; -- Store flag to indicate which bank is being made active.
|
||||
end if;
|
||||
|
||||
-- Open the requested row.
|
||||
when CYCLE_RAS_START =>
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
--sd_mxadr <= '0' & sd_row; -- 0 & Addr[20:9] presented to SDRAM as row address.
|
||||
sd_mxadr <= sd_row; -- Addr[21:9] presented to SDRAM as row address.
|
||||
SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length)); -- Addr[23:22]
|
||||
sd_active_row(sd_bank) <= sd_row; -- Store number of row being made active
|
||||
sd_active_bank(sd_bank) <= '1'; -- Store flag to indicate which bank is being made active.
|
||||
|
||||
when CYCLE_RAS_NEXT =>
|
||||
sd_mxadr(12 downto 11) <= "11"; -- Set DQ to tri--state.
|
||||
|
||||
-- this is the first CAS cycle
|
||||
when CYCLE_CAS0 =>
|
||||
-- Process on a 32bit boundary, as this is a 16bit chip we need 2 accesses for a 32bit alignment.
|
||||
--sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 2) & '0'; -- CAS address = Addr[23,8:2] accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
sd_mxadr <= "0000" & WB_ADR_I(8 downto 1) & '0'; -- CAS address = Addr[23,8:2] accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
SD_BA <= std_logic_vector(to_unsigned(sd_bank, SD_BA'length)); -- Ensure bank is the correct one opened.
|
||||
|
||||
if (sd_reading = '1') then
|
||||
sd_cmd <= CMD_READ;
|
||||
elsif (sd_writing = '1') then
|
||||
sd_cmd <= CMD_WRITE;
|
||||
sd_mxadr(12 downto 11)<= not WB_SEL_I(1 downto 0); -- For writing, set DQM to the negated WB_SEL values, indicating which bytes to process.
|
||||
sd_dout <= wb_dat_i(15 downto 0); -- Assign corresponding data to the SDRAM databus.
|
||||
end if;
|
||||
|
||||
when CYCLE_CAS1 =>
|
||||
--sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 2) & '1'; -- As per CAS0 except we now access second 16bit location within the 32bit external alignment.
|
||||
sd_mxadr <= "0000" & WB_ADR_I(8 downto 1) & '1'; -- As per CAS0 except we now access second 16bit location within the 32bit external alignment.
|
||||
if (sd_reading = '1') then
|
||||
sd_cmd <= CMD_READ;
|
||||
if (burst_mode = '1' and can_burst = '1') then
|
||||
sd_burst <= '1';
|
||||
end if;
|
||||
elsif (sd_writing = '1') then
|
||||
sd_cmd <= CMD_WRITE;
|
||||
sd_mxadr(12 downto 11)<= not WB_SEL_I(3 downto 2);
|
||||
sd_done <= not sd_done;
|
||||
sd_dout <= wb_dat_i(31 downto 16);
|
||||
-- sd_cycle <= CYCLE_END;
|
||||
end if;
|
||||
|
||||
|
||||
-- CAS2/3 ... are to handle burst transfers according to programmed Mode register word.
|
||||
when CYCLE_CAS2 =>
|
||||
if (sd_burst = '1') then
|
||||
--sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 3) & "10"; -- no auto precharge
|
||||
sd_mxadr <= "0000" & WB_ADR_I(8 downto 2) & "10"; -- no auto precharge
|
||||
if (sd_reading = '1') then
|
||||
sd_cmd <= CMD_READ;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when CYCLE_CAS3 =>
|
||||
if (sd_burst = '1') then
|
||||
--sd_mxadr <= "0000" & WB_ADR_I(23) & WB_ADR_I(8 downto 3) & "11"; -- no auto precharge
|
||||
sd_mxadr <= "0000" & WB_ADR_I(8 downto 2) & "11"; -- no auto precharge
|
||||
if (sd_reading = '1') then
|
||||
sd_cmd <= CMD_READ;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Data is available CAS Latency clocks after the read request, so these read operations operate in parallel to the CAS
|
||||
-- cycles requesting the data. ie. CL=2 then CYCLE_READ0 will be processed same time as CYCLE_CAS2.
|
||||
when CYCLE_READ0 =>
|
||||
if (sd_reading = '1') then
|
||||
sd_dat(15 downto 0) <= sd_din;
|
||||
else
|
||||
if (sd_writing = '1') then
|
||||
sd_cycle <= CYCLE_END;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ1 =>
|
||||
if (sd_reading = '1') then
|
||||
sd_dat(31 downto 16) <= sd_din;
|
||||
sd_done <= not sd_done;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ2 =>
|
||||
if (sd_reading = '1') then
|
||||
sd_dat_nxt(15 downto 0)<= sd_din;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ3 =>
|
||||
if (sd_reading = '1') then
|
||||
sd_dat_nxt(31 downto 16)<= sd_din;
|
||||
end if;
|
||||
|
||||
when CYCLE_END =>
|
||||
sd_burst <= '0';
|
||||
sd_cyc <= '0';
|
||||
sd_stb <= '0';
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
sd_cycle <= 0;
|
||||
sd_burst <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- WishBone interface for sending received data and setting up the correct ACK signal for any read/write activity.
|
||||
process(SD_RST, WB_CLK, sd_rdy)
|
||||
begin
|
||||
if (SD_RST = '1') then
|
||||
sd_done_last <= '0';
|
||||
wb_ack <= '0';
|
||||
wb_burst <= '0';
|
||||
|
||||
-- If the SDRAM isnt ready, we can only wait.
|
||||
elsif sd_rdy = '0' then
|
||||
|
||||
elsif rising_edge(WB_CLK) then
|
||||
|
||||
-- Note SDRAM activity via a previous/last signal.
|
||||
sd_done_last <= sd_done;
|
||||
|
||||
-- If there has been a change in the SDRAM activity and it hasnt been acknowleged, send the ACK else cancel any previous ACK.
|
||||
if (sd_done xor sd_done_last) = '1' and wb_ack = '0' then
|
||||
wb_ack <= '1';
|
||||
else
|
||||
wb_ack <= '0';
|
||||
end if;
|
||||
|
||||
-- If we are in an active Cycle and the Strobe is activated, assign any read data to the WB bus.
|
||||
if (WB_STB_I = '1' and WB_CYC_I = '1') then
|
||||
|
||||
-- If there has been a change in the SDRAM activity and it hasnt been acknowledged, send the current data held to the WB Bus.
|
||||
if ((sd_done xor sd_done_last) = '1' and wb_ack = '0') then
|
||||
wb_dat_o <= sd_dat;
|
||||
wb_burst <= burst_mode;
|
||||
end if;
|
||||
|
||||
-- If there has been an acknowledge due to sending of the first data word and we are in burst mode, then send the 2nd read value
|
||||
-- whilst maintaining the ack.
|
||||
if (wb_ack = '1' and wb_burst = '1') then
|
||||
wb_ack <= '1';
|
||||
wb_burst <= '0';
|
||||
wb_dat_o <= sd_dat_nxt;
|
||||
end if;
|
||||
else
|
||||
wb_burst <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sd_req <= WB_STB_I & WB_CYC_I & not wb_ack;
|
||||
sd_bank <= to_integer(unsigned(WB_ADR_I(23 downto 22)));
|
||||
sd_row <= WB_ADR_I(21 downto 9);
|
||||
|
||||
burst_mode <= '1' when WB_CTI_I = "010" else '0';
|
||||
can_burst <= '1' when WB_ADR_I(2) = '0' else '0';
|
||||
sd_reading <= '1' when sd_stb = '1' and sd_cyc = '1' and sd_we = '0' else '0';
|
||||
sd_writing <= '1' when sd_stb = '1' and sd_cyc = '1' and sd_we = '1' else '0';
|
||||
|
||||
-- drive control signals according to current command
|
||||
SD_CS_n <= sd_cmd(3);
|
||||
SD_RAS_n <= sd_cmd(2);
|
||||
SD_CAS_n <= sd_cmd(1);
|
||||
SD_WE_n <= sd_cmd(0);
|
||||
SD_CKE <= '1';
|
||||
SD_DQM <= sd_mxadr(12 downto 11);
|
||||
SD_ADDR <= sd_mxadr;
|
||||
|
||||
WB_ACK_O <= wb_ack;
|
||||
SD_READY <= sd_rdy;
|
||||
|
||||
end Structure;
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram.vhd ]
|
||||
#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ]
|
||||
@@ -1,90 +0,0 @@
|
||||
# ------------------------------------------------------------------------------
|
||||
# Constraints definition original author:
|
||||
# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu)
|
||||
# Adapted and enhanced for the Micron 48LC16M16 SDRAM by Philip Smart Dec 2019.
|
||||
# ------------------------------------------------------------------------------
|
||||
derive_pll_clocks
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM Clock
|
||||
# Set these variables to the system and memory clock PLL paths for
|
||||
# your board.
|
||||
# -----------------------------------------------------------------
|
||||
set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk"
|
||||
set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk"
|
||||
create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}]
|
||||
derive_clock_uncertainty
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM Constraints
|
||||
# -----------------------------------------------------------------
|
||||
#
|
||||
# SDRAM timing parameters
|
||||
#
|
||||
# Generally, the command/address/data all have the same setup/hold
|
||||
# time.
|
||||
#
|
||||
# SDRAM clock can lead System clock by min:
|
||||
# tlead = tcoutmin(FPGA) – th(SDRAM)
|
||||
#
|
||||
# SDRAM clock can lag System clock by min:
|
||||
# tlag = toh(SDRAM) – th(FPGA)
|
||||
#
|
||||
# tSU = Data Setup time (ie. tDS, tAS) on falling edge.
|
||||
# tH = Hold time (ie. tDH, tAH) for SDRAM.
|
||||
# tCOUT (min) = Data out hold time (ie. tOH)
|
||||
# tCOUT (max) = Access time for CL in use (ie. tAC3).
|
||||
#
|
||||
set sdram_tsu 1.5
|
||||
set sdram_th 0.8
|
||||
set sdram_tco_min 3.0
|
||||
set sdram_tco_max 5.4
|
||||
|
||||
# FPGA timing constraints
|
||||
set sdram_input_delay_min $sdram_tco_min
|
||||
set sdram_input_delay_max $sdram_tco_max
|
||||
set sdram_output_delay_min -$sdram_th
|
||||
set sdram_output_delay_max $sdram_tsu
|
||||
|
||||
# PLL to FPGA output (clear the unconstrained path warning)
|
||||
#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1
|
||||
#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6
|
||||
|
||||
# FPGA Outputs
|
||||
set sdram_outputs [get_ports {
|
||||
SDRAM_CKE
|
||||
SDRAM_CS
|
||||
SDRAM_RAS
|
||||
SDRAM_CAS
|
||||
SDRAM_WE
|
||||
SDRAM_DQM[*]
|
||||
SDRAM_BA[*]
|
||||
SDRAM_ADDR[*]
|
||||
SDRAM_DQ[*]
|
||||
}]
|
||||
set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs
|
||||
set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs
|
||||
|
||||
# FPGA Inputs
|
||||
set sdram_inputs [get_ports {
|
||||
SDRAM_DQ[*]
|
||||
}]
|
||||
set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs
|
||||
set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM-to-FPGA multi-cycle constraint
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
# The PLL is configured so that SDRAM clock leads the system
|
||||
# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock).
|
||||
# This will need changing for different clocks, in the PLL
|
||||
# RTL file and the SoC contraints file.
|
||||
|
||||
# The following multi-cycle constraint declares to TimeQuest that
|
||||
# the path between the SDRAM_CLK and the System Clock can be an
|
||||
# extra clock period to the read path to ensure that the latch
|
||||
# clock that occurs 1.25 periods after the launch clock is used in
|
||||
# the timing analysis.
|
||||
#
|
||||
set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram_cached.vhd ]
|
||||
#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) 48LC16M16.sdc ]
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram.vhd ]
|
||||
#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ]
|
||||
@@ -1,90 +0,0 @@
|
||||
# ------------------------------------------------------------------------------
|
||||
# Constraints definition original author:
|
||||
# 8/19/2014 D. W. Hawkings (dwh@ovro.caltech.edu)
|
||||
# Adapted and enhanced for the Winbond W9864G6 SDRAM by Philip Smart Dec 2019.
|
||||
# ------------------------------------------------------------------------------
|
||||
derive_pll_clocks
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM Clock
|
||||
# Set these variables to the system and memory clock PLL paths for
|
||||
# your board.
|
||||
# -----------------------------------------------------------------
|
||||
set sysclk_pll "mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk"
|
||||
set memclk_pll "mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk"
|
||||
create_generated_clock -name SDRAM_CLK -source $memclk_pll [get_ports {SDRAM_CLK}]
|
||||
derive_clock_uncertainty
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM Constraints
|
||||
# -----------------------------------------------------------------
|
||||
#
|
||||
# SDRAM timing parameters
|
||||
#
|
||||
# Generally, the command/address/data all have the same setup/hold
|
||||
# time.
|
||||
#
|
||||
# SDRAM clock can lead System clock by min:
|
||||
# tlead = tcoutmin(FPGA) – th(SDRAM)
|
||||
#
|
||||
# SDRAM clock can lag System clock by min:
|
||||
# tlag = toh(SDRAM) – th(FPGA)
|
||||
#
|
||||
# tSU = Data Setup time (ie. tDS, tAS) on falling edge.
|
||||
# tH = Hold time (ie. tDH, tAH) for SDRAM.
|
||||
# tCOUT (min) = Data out hold time (ie. tOH)
|
||||
# tCOUT (max) = Access time for CL in use (ie. tAC3).
|
||||
#
|
||||
set sdram_tsu 1.5
|
||||
set sdram_th 0.8
|
||||
set sdram_tco_min 3.0
|
||||
set sdram_tco_max 5.0
|
||||
|
||||
# FPGA timing constraints
|
||||
set sdram_input_delay_min $sdram_tco_min
|
||||
set sdram_input_delay_max $sdram_tco_max
|
||||
set sdram_output_delay_min -$sdram_th
|
||||
set sdram_output_delay_max $sdram_tsu
|
||||
|
||||
# PLL to FPGA output (clear the unconstrained path warning)
|
||||
#set_min_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 1
|
||||
#set_max_delay -from $memclk_pll -to [get_ports {SDRAM_CLK}] 6
|
||||
|
||||
# FPGA Outputs
|
||||
set sdram_outputs [get_ports {
|
||||
SDRAM_CKE
|
||||
SDRAM_CS
|
||||
SDRAM_RAS
|
||||
SDRAM_CAS
|
||||
SDRAM_WE
|
||||
SDRAM_DQM[*]
|
||||
SDRAM_BA[*]
|
||||
SDRAM_ADDR[*]
|
||||
SDRAM_DQ[*]
|
||||
}]
|
||||
set_output_delay -clock SDRAM_CLK -min $sdram_output_delay_min $sdram_outputs
|
||||
set_output_delay -clock SDRAM_CLK -max $sdram_output_delay_max $sdram_outputs
|
||||
|
||||
# FPGA Inputs
|
||||
set sdram_inputs [get_ports {
|
||||
SDRAM_DQ[*]
|
||||
}]
|
||||
set_input_delay -clock SDRAM_CLK -min $sdram_input_delay_min $sdram_inputs
|
||||
set_input_delay -clock SDRAM_CLK -max $sdram_input_delay_max $sdram_inputs
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# SDRAM-to-FPGA multi-cycle constraint
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
# The PLL is configured so that SDRAM clock leads the system
|
||||
# clock by ~90-degrees (0.25 period or 2.5ns for 100MHz clock).
|
||||
# This will need changing for different clocks, in the PLL
|
||||
# RTL file and the SoC contraints file.
|
||||
|
||||
# The following multi-cycle constraint declares to TimeQuest that
|
||||
# the path between the SDRAM_CLK and the System Clock can be an
|
||||
# extra clock period to the read path to ensure that the latch
|
||||
# clock that occurs 1.25 periods after the launch clock is used in
|
||||
# the timing analysis.
|
||||
#
|
||||
set_multicycle_path -setup -end -from SDRAM_CLK -to $sysclk_pll 2
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) wbsdram_cached.vhd ]
|
||||
#set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) W9864G6.sdc ]
|
||||
@@ -1,504 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: wbsdram.vhd
|
||||
-- Created: September 2019
|
||||
-- Author: Philip Smart
|
||||
-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC.
|
||||
-- The module is instantiated with the parameters to describe the underlying SDRAM chip
|
||||
-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM
|
||||
-- standard.
|
||||
-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on
|
||||
-- the verilog MT48LC16M16 chip controller written by Stephen.
|
||||
-- Copyright: (c) 2019-2020 Philip Smart <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog
|
||||
-- source code.
|
||||
-- November 2019 - Adapted for the system bus for use when no Wishbone interface is
|
||||
-- instantiated in the ZPU Evo.
|
||||
-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing
|
||||
-- and parameterisation.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity WBSDRAM is
|
||||
generic (
|
||||
MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions.
|
||||
SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM.
|
||||
SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row).
|
||||
SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM.
|
||||
SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32).
|
||||
SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz.
|
||||
SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns).
|
||||
SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns).
|
||||
SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
|
||||
SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms).
|
||||
);
|
||||
port (
|
||||
-- SDRAM Interface
|
||||
SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK.
|
||||
SDRAM_RST : in std_logic; -- Reset the sdram controller.
|
||||
SDRAM_CKE : out std_logic; -- Clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks.
|
||||
SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM
|
||||
SDRAM_CS_n : out std_logic; -- Single chip select
|
||||
SDRAM_WE_n : out std_logic; -- Write enable
|
||||
SDRAM_RAS_n : out std_logic; -- Row address select
|
||||
SDRAM_CAS_n : out std_logic; -- Columns address select
|
||||
SDRAM_READY : out std_logic; -- SD ready.
|
||||
|
||||
-- WishBone interface.
|
||||
WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates.
|
||||
WB_RST_I : in std_logic; -- high active sync reset
|
||||
WB_DATA_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master
|
||||
WB_DATA_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master
|
||||
WB_ACK_O : out std_logic;
|
||||
WB_ADR_I : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0);
|
||||
WB_SEL_I : in std_logic_vector(3 downto 0);
|
||||
WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst
|
||||
WB_STB_I : in std_logic;
|
||||
WB_CYC_I : in std_logic; -- cpu/chipset requests cycle
|
||||
WB_WE_I : in std_logic; -- cpu/chipset requests write
|
||||
WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag
|
||||
WB_HALT_O : out std_logic; -- throttle master
|
||||
WB_ERR_O : out std_logic -- abnormal cycle termination
|
||||
);
|
||||
end WBSDRAM;
|
||||
|
||||
architecture Structure of WBSDRAM is
|
||||
|
||||
-- Constants to define the structure of the SDRAM in bits for provisioning of signals.
|
||||
constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS);
|
||||
constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS);
|
||||
constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS);
|
||||
constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS);
|
||||
constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8));
|
||||
|
||||
-- Command table for a standard SDRAM.
|
||||
--
|
||||
-- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ
|
||||
-- COMMAND INHIBIT (NOP) H H X X X X X X
|
||||
-- NO OPERATION (NOP) H L H H H X X X
|
||||
-- ACTIVE (select bank and activate row) H L L H H X Bank/row X
|
||||
-- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X
|
||||
-- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid
|
||||
-- BURST TERMINATE H L H H L X X Active
|
||||
-- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X
|
||||
-- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X
|
||||
-- LOAD MODE REGISTER H L L L L X Op-code X
|
||||
-- Write enable/output enable H X X X X L X Active
|
||||
-- Write inhibit/output High-Z H X X X X H X High-Z
|
||||
-- Self Refresh Entry L L L L H X X X
|
||||
-- Self Refresh Exit (Device is idle) H H X X X X X X
|
||||
-- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X
|
||||
-- Clock suspend mode Entry L X X X X X X X
|
||||
-- Clock suspend mode Exit H X X X X X X X
|
||||
-- Power down mode Entry (Device is idle) L H X X X X X X
|
||||
-- Power down mode Entry (Device is Active) L L H H X X X X
|
||||
-- Power down mode Exit (Any state) H H X X X X X X
|
||||
-- Power down mode Exit (Device is powered down) H L H H X X X X
|
||||
|
||||
constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111";
|
||||
constant CMD_NOP : std_logic_vector(4 downto 0) := "10111";
|
||||
constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011";
|
||||
constant CMD_READ : std_logic_vector(4 downto 0) := "10101";
|
||||
constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100";
|
||||
constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010";
|
||||
constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001";
|
||||
constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001";
|
||||
constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000";
|
||||
constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000";
|
||||
constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100";
|
||||
|
||||
-- Load Mode Register setting for a standard SDRAM.
|
||||
--
|
||||
-- xx:10 = Reserved :
|
||||
-- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
|
||||
-- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
|
||||
-- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
|
||||
-- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
|
||||
-- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
|
||||
-- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
|
||||
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
|
||||
constant WRITE_BURST_MODE : std_logic := '1';
|
||||
constant OP_MODE : std_logic_vector(1 downto 0) := "00";
|
||||
constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
|
||||
constant BURST_TYPE : std_logic := '0';
|
||||
constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000";
|
||||
constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS));
|
||||
|
||||
-- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time.
|
||||
--
|
||||
constant CYCLE_PRECHARGE : integer := 0; -- ~0
|
||||
constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3
|
||||
constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD
|
||||
constant CYCLE_CAS_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD
|
||||
constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP
|
||||
constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks.
|
||||
|
||||
-- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is
|
||||
-- the time it takes when a refresh starts until completion.
|
||||
constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000;
|
||||
|
||||
-- Array of row addresses, one per bank, to indicate the row in use per bank.
|
||||
type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
|
||||
-- SDRAM domain signals.
|
||||
signal sdBusy : std_logic;
|
||||
signal sdCycle : integer range 0 to 31;
|
||||
signal sdDataOut : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal sdDone : std_logic;
|
||||
shared variable sdCmd : std_logic_vector(4 downto 0);
|
||||
signal sdRefreshCount : unsigned(11 downto 0);
|
||||
signal sdAutoRefresh : std_logic;
|
||||
signal sdResetTimer : unsigned(WORD_8BIT_RANGE);
|
||||
signal sdInResetCounter : unsigned(WORD_8BIT_RANGE);
|
||||
signal sdIsReady : std_logic;
|
||||
signal sdActiveRow : BankArray;
|
||||
signal sdActiveBank : std_logic_vector(1 downto 0);
|
||||
|
||||
-- CPU domain signals.
|
||||
signal cpuBusy : std_logic;
|
||||
signal cpuDQM : std_logic_vector(3 downto 0);
|
||||
signal cpuDoneLast : std_logic;
|
||||
signal cpuBank : natural range 0 to SDRAM_BANKS-1;
|
||||
signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0);
|
||||
signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal cpuIsWriting : std_logic;
|
||||
signal cpuDoneAck : std_logic;
|
||||
signal wbACK : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Main FSM for SDRAM control and refresh.
|
||||
process(ALL)
|
||||
begin
|
||||
|
||||
if (SDRAM_RST = '1') then
|
||||
sdResetTimer <= (others => '0'); -- 0 upto 255
|
||||
sdInResetCounter <= (others => '1'); -- 255 downto 0
|
||||
sdAutoRefresh <= '0';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
sdIsReady <= '0';
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
SDRAM_DQM <= (others => '1');
|
||||
sdCycle <= 0;
|
||||
sdDone <= '0';
|
||||
|
||||
elsif rising_edge(SDRAM_CLK) then
|
||||
|
||||
-- Tri-state control of the SDRAM databus, when reading, the output drivers are disabled.
|
||||
if (cpuIsWriting = '0') then
|
||||
SDRAM_DQ <= (others => 'Z');
|
||||
end if;
|
||||
|
||||
-- If no specific command given the default is NOP.
|
||||
sdCmd := CMD_NOP;
|
||||
|
||||
-- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied.
|
||||
if (sdIsReady = '0') then
|
||||
sdResetTimer <= sdResetTimer + 1;
|
||||
|
||||
-- 1uS timer.
|
||||
if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then
|
||||
sdResetTimer <= (others => '0');
|
||||
sdInResetCounter <= sdInResetCounter - 1;
|
||||
end if;
|
||||
|
||||
-- Every 1uS check for the next init action.
|
||||
if (sdResetTimer = 0) then
|
||||
|
||||
-- 200uS wait, no action as the SDRAM starts up.
|
||||
-- ie. 255 downto 55
|
||||
|
||||
-- Precharge all banks
|
||||
if(sdInResetCounter = 55) then
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- Load the Mode register with our parameters.
|
||||
if(sdInResetCounter = 39) then
|
||||
sdCmd := CMD_LOAD_MODE;
|
||||
SDRAM_ADDR <= MODE;
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- SDRAM ready.
|
||||
if(sdInResetCounter = 20) then
|
||||
sdIsReady <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
-- Counter to time periods between autorefresh.
|
||||
sdRefreshCount <= sdRefreshCount + 1;
|
||||
|
||||
-- This mechanism is used to reduce the possibility of metastability issues due to differing clocks.
|
||||
-- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high.
|
||||
sdBusy <= cpuBusy;
|
||||
|
||||
-- If the SDRAM has completed its transaction and the CPU has acknowledged it, remove the signals.
|
||||
if (sdDone = '1' and cpuDoneAck = '1') then
|
||||
sdDone <= '0';
|
||||
end if;
|
||||
|
||||
-- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are
|
||||
-- issued in a tRFC period. Other bus operations are stalled during this period.
|
||||
if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then
|
||||
sdAutoRefresh <= '1';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
|
||||
-- In auto refresh period.
|
||||
elsif (sdAutoRefresh = '1') then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
when CYCLE_RFSH_START =>
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
|
||||
when CYCLE_RFSH_END =>
|
||||
-- reset the count.
|
||||
sdAutoRefresh <= '0';
|
||||
sdCycle <= 0;
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif (((cpuBusy = '1' and sdBusy = '1') and sdCycle = 0) or sdCycle /= 0) then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
|
||||
when CYCLE_PRECHARGE =>
|
||||
-- If the bank is not open then no need to precharge, move onto RAS.
|
||||
if (sdActiveBank(cpuBank) = '0') then
|
||||
sdCycle <= CYCLE_RAS_START;
|
||||
|
||||
-- If the requested row is already active, go to CAS for immediate access to this row.
|
||||
elsif (sdActiveRow(cpuBank) = cpuRow) then
|
||||
sdCycle <= CYCLE_CAS_START;
|
||||
|
||||
-- Otherwise we close out the open bank by issuing a PRECHARGE.
|
||||
else
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '0';
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length));
|
||||
sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active.
|
||||
end if;
|
||||
|
||||
-- Open the requested row.
|
||||
when CYCLE_RAS_START =>
|
||||
sdCmd := CMD_ACTIVE;
|
||||
SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address.
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select.
|
||||
sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active
|
||||
sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active.
|
||||
|
||||
-- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words.
|
||||
when CYCLE_CAS_START =>
|
||||
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (cpuIsWriting = '1') then
|
||||
|
||||
if SDRAM_DATAWIDTH = 32 then
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge
|
||||
SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus.
|
||||
SDRAM_DQM <= not cpuDQM(3 downto 0);
|
||||
sdCycle <= CYCLE_END;
|
||||
|
||||
elsif SDRAM_DATAWIDTH = 16 then
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus.
|
||||
SDRAM_DQM <= not cpuDQM(3 downto 2);
|
||||
else
|
||||
report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error;
|
||||
end if;
|
||||
sdCmd := CMD_WRITE;
|
||||
|
||||
else
|
||||
-- Setup for a read.
|
||||
sdCmd := CMD_READ;
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
SDRAM_DQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
when CYCLE_CAS_END =>
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge
|
||||
|
||||
-- When writing, setup for a write with preset mask with the correct word.
|
||||
if (cpuIsWriting = '1') then
|
||||
SDRAM_DQM <= not cpuDQM(1 downto 0);
|
||||
SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0);
|
||||
sdDone <= '1';
|
||||
sdCycle <= CYCLE_END;
|
||||
sdCmd := CMD_WRITE;
|
||||
else
|
||||
-- Setup for a read, change to write if flag set.
|
||||
sdCmd := CMD_READ;
|
||||
SDRAM_DQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
-- Data is available CAS Latency clocks after the read request. For 32bit chips, only 1 cycle is needed, for 16bit we need 2 read cycles of
|
||||
-- 16 bits each.
|
||||
when CYCLE_READ_START =>
|
||||
|
||||
if SDRAM_DATAWIDTH = 32 then
|
||||
sdDataOut <= SDRAM_DQ;
|
||||
sdCycle <= CYCLE_END;
|
||||
|
||||
elsif SDRAM_DATAWIDTH = 16 then
|
||||
sdDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= SDRAM_DQ;
|
||||
else
|
||||
report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error;
|
||||
end if;
|
||||
|
||||
-- Second and final read cycle for 16bit SDRAM chips to create a 32bit word.
|
||||
when CYCLE_READ_END =>
|
||||
sdDataOut(SDRAM_DATAWIDTH-1 downto 0) <= SDRAM_DQ;
|
||||
|
||||
when CYCLE_END =>
|
||||
sdDone <= '1';
|
||||
sdCycle <= 0;
|
||||
|
||||
-- Other states are wait states, waiting for the correct time slot for SDRAM access.
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
sdCycle <= 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- drive control signals according to current command
|
||||
SDRAM_CKE <= sdCmd(4);
|
||||
SDRAM_CS_n <= sdCmd(3);
|
||||
SDRAM_RAS_n <= sdCmd(2);
|
||||
SDRAM_CAS_n <= sdCmd(1);
|
||||
SDRAM_WE_n <= sdCmd(0);
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- CPU/WishBone side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent
|
||||
-- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know
|
||||
-- when the transation is complete and data read.
|
||||
--
|
||||
process(ALL)
|
||||
begin
|
||||
if (WB_RST_I = '1') then
|
||||
cpuDoneLast <= '0';
|
||||
cpuBusy <= '0';
|
||||
cpuBank <= 0;
|
||||
cpuRow <= (others => '0');
|
||||
cpuCol <= (others => '0');
|
||||
cpuDQM <= (others => '1');
|
||||
cpuDoneAck <= '0';
|
||||
cpuIsWriting <= '0';
|
||||
wbACK <= '0';
|
||||
|
||||
-- Wait for the SDRAM to become ready by holding the CPU in a wait state.
|
||||
elsif sdIsReady = '0' then
|
||||
cpuBusy <= '1';
|
||||
|
||||
elsif rising_edge(WB_CLK) then
|
||||
|
||||
-- Detect a Wishbone cycle and commence an SDRAM access.
|
||||
if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '0') then
|
||||
cpuBusy <= '1';
|
||||
cpuBank <= to_integer(unsigned(WB_ADR_I(SDRAM_ADDR_BITS-1 downto SDRAM_ARRAY_BITS+1)));
|
||||
cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(WB_ADR_I(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS));
|
||||
cpuCol <= WB_ADR_I(SDRAM_COLUMN_BITS downto 2) & '0';
|
||||
cpuDQM <= WB_SEL_I;
|
||||
cpuDataIn <= WB_DATA_I;
|
||||
end if;
|
||||
|
||||
if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '1') then
|
||||
cpuIsWriting <= WB_WE_I;
|
||||
end if;
|
||||
|
||||
-- Note SDRAM activity via a previous/last signal.
|
||||
cpuDoneLast <= sdDone;
|
||||
|
||||
-- If there has been a change in the SDRAM activity and it hasnt been acknowleged, send the ACK and use the cycle to latch the retrieved data.
|
||||
if (cpuDoneLast = '0' and sdDone = '1') then
|
||||
cpuDoneAck <= '1';
|
||||
WB_DATA_O <= sdDataOut;
|
||||
end if;
|
||||
|
||||
-- If we are at the end of an active Cycle and the acknowledge to the sdram fsm has been sent, clear all signals and assert the Wishbone Ack to
|
||||
-- complete.
|
||||
if (cpuDoneLast = '1' and sdDone = '0' and cpuDoneAck = '1' and wbACK = '0') then
|
||||
cpuBusy <= '0';
|
||||
cpuDoneAck <= '0';
|
||||
cpuIsWriting <= '0';
|
||||
wbACK <= '1';
|
||||
else
|
||||
wbACK <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- System bus control signals.
|
||||
SDRAM_READY <= sdIsReady;
|
||||
|
||||
-- Wishbone bus control signals.
|
||||
WB_ACK_O <= wbACK;
|
||||
|
||||
--- Throttle not needed.
|
||||
WB_HALT_O <= '0';
|
||||
|
||||
--- Error not yet implemented.
|
||||
WB_ERR_O <= '0';
|
||||
|
||||
end Structure;
|
||||
@@ -1,712 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: wbsdram_cached.vhd
|
||||
-- Created: September 2019
|
||||
-- Author: Philip Smart
|
||||
-- Description: A configurable cached sdram controller for use with the ZPU EVO Processor and SoC.
|
||||
-- The module is instantiated with the parameters to describe the underlying SDRAM chip
|
||||
-- and in theory should work with most 16/32 bit SDRAM chips if they adhere to the SDRAM
|
||||
-- standard.
|
||||
-- Credits: Stephen J. Leary 2013-2014 - Basic sdram cycle structure of this module was based on
|
||||
-- the verilog MT48LC16M16 chip controller written by Stephen.
|
||||
-- Copyright: (c) 2019-2020 Philip Smart <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog
|
||||
-- source code.
|
||||
-- November 2019 - Adapted for the system bus for use when no Wishbone interface is
|
||||
-- instantiated in the ZPU Evo.
|
||||
-- December 2019 - Extensive changes, metability stability, autorefresh to ACTIVE timing
|
||||
-- and parameterisation.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity WBSDRAM is
|
||||
generic (
|
||||
MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions.
|
||||
SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM.
|
||||
SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row).
|
||||
SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM.
|
||||
SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (16, 32).
|
||||
SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz.
|
||||
SDRAM_tRCD : integer := 20; -- tRCD - RAS to CAS minimum period (in ns).
|
||||
SDRAM_tRP : integer := 20; -- tRP - Precharge delay, min time for a precharge command to complete (in ns).
|
||||
SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
|
||||
SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms).
|
||||
);
|
||||
port (
|
||||
-- SDRAM Interface
|
||||
SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK.
|
||||
SDRAM_RST : in std_logic; -- Reset the sdram controller.
|
||||
SDRAM_CKE : out std_logic; -- Clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks.
|
||||
SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM
|
||||
SDRAM_CS_n : out std_logic; -- Single chip select
|
||||
SDRAM_WE_n : out std_logic; -- Write enable
|
||||
SDRAM_RAS_n : out std_logic; -- Row address select
|
||||
SDRAM_CAS_n : out std_logic; -- Columns address select
|
||||
SDRAM_READY : out std_logic; -- SD ready.
|
||||
|
||||
-- WishBone interface.
|
||||
WB_CLK : in std_logic; -- Master clock at which the Wishbone interface operates.
|
||||
WB_RST_I : in std_logic; -- high active sync reset
|
||||
WB_DATA_I : in std_logic_vector(WORD_32BIT_RANGE); -- Data input from Master
|
||||
WB_DATA_O : out std_logic_vector(WORD_32BIT_RANGE); -- Data output to Master
|
||||
WB_ACK_O : out std_logic;
|
||||
WB_ADR_I : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0);
|
||||
WB_SEL_I : in std_logic_vector(3 downto 0);
|
||||
WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst
|
||||
WB_STB_I : in std_logic;
|
||||
WB_CYC_I : in std_logic; -- cpu/chipset requests cycle
|
||||
WB_WE_I : in std_logic; -- cpu/chipset requests write
|
||||
WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag
|
||||
WB_HALT_O : out std_logic; -- throttle master
|
||||
WB_ERR_O : out std_logic -- abnormal cycle termination
|
||||
);
|
||||
end WBSDRAM;
|
||||
|
||||
architecture Structure of WBSDRAM is
|
||||
|
||||
-- Constants to define the structure of the SDRAM in bits for provisioning of signals.
|
||||
constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS);
|
||||
constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS);
|
||||
constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS);
|
||||
constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS);
|
||||
constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS * (SDRAM_DATAWIDTH/8));
|
||||
|
||||
-- Command table for a standard SDRAM.
|
||||
--
|
||||
-- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ
|
||||
-- COMMAND INHIBIT (NOP) H H X X X X X X
|
||||
-- NO OPERATION (NOP) H L H H H X X X
|
||||
-- ACTIVE (select bank and activate row) H L L H H X Bank/row X
|
||||
-- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X
|
||||
-- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid
|
||||
-- BURST TERMINATE H L H H L X X Active
|
||||
-- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X
|
||||
-- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X
|
||||
-- LOAD MODE REGISTER H L L L L X Op-code X
|
||||
-- Write enable/output enable H X X X X L X Active
|
||||
-- Write inhibit/output High-Z H X X X X H X High-Z
|
||||
-- Self Refresh Entry L L L L H X X X
|
||||
-- Self Refresh Exit (Device is idle) H H X X X X X X
|
||||
-- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X
|
||||
-- Clock suspend mode Entry L X X X X X X X
|
||||
-- Clock suspend mode Exit H X X X X X X X
|
||||
-- Power down mode Entry (Device is idle) L H X X X X X X
|
||||
-- Power down mode Entry (Device is Active) L L H H X X X X
|
||||
-- Power down mode Exit (Any state) H H X X X X X X
|
||||
-- Power down mode Exit (Device is powered down) H L H H X X X X
|
||||
|
||||
constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111";
|
||||
constant CMD_NOP : std_logic_vector(4 downto 0) := "10111";
|
||||
constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011";
|
||||
constant CMD_READ : std_logic_vector(4 downto 0) := "10101";
|
||||
constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100";
|
||||
constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010";
|
||||
constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001";
|
||||
constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001";
|
||||
constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110";
|
||||
constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000";
|
||||
constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000";
|
||||
constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000";
|
||||
constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100";
|
||||
|
||||
-- Load Mode Register setting for a standard SDRAM.
|
||||
--
|
||||
-- xx:10 = Reserved :
|
||||
-- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
|
||||
-- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
|
||||
-- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
|
||||
-- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
|
||||
-- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
|
||||
-- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
|
||||
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
|
||||
constant WRITE_BURST_MODE : std_logic := '1';
|
||||
constant OP_MODE : std_logic_vector(1 downto 0) := "00";
|
||||
constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
|
||||
constant BURST_TYPE : std_logic := '0';
|
||||
constant BURST_LENGTH : std_logic_vector(2 downto 0) := "111";
|
||||
constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS));
|
||||
|
||||
-- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time.
|
||||
--
|
||||
constant CYCLE_PRECHARGE : integer := 0; -- ~0
|
||||
constant CYCLE_RAS_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~3
|
||||
constant CYCLE_CAS_START : integer := CYCLE_RAS_START + clockTicks(SDRAM_tRCD, SDRAM_CLK_FREQ); -- ~3 + tRCD
|
||||
constant CYCLE_WRITE_END : integer := CYCLE_CAS_START + 1; -- ~4 + tRCD
|
||||
constant CYCLE_READ_START : integer := CYCLE_CAS_START + to_integer(unsigned(CAS_LATENCY)) + 1; -- ~3 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_READ_END : integer := CYCLE_READ_START + 1; -- ~4 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_END : integer := CYCLE_READ_END + 1; -- ~9 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_RFSH_START : integer := clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ); -- ~tRP
|
||||
constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + clockTicks(SDRAM_tRFC, SDRAM_CLK_FREQ) + clockTicks(SDRAM_tRP, SDRAM_CLK_FREQ) + 1; -- ~tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks.
|
||||
|
||||
-- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is
|
||||
-- the time it takes when a refresh starts until completion.
|
||||
constant REFRESH_PERIOD : integer := (((SDRAM_tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (SDRAM_tRFC * 1000)) / 1000;
|
||||
|
||||
-- Array of row addresses, one per bank, to indicate the row in use per bank.
|
||||
type BankArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
type BankCacheArray is array(natural range 0 to SDRAM_BANKS-1) of std_logic_vector(((SDRAM_ROW_BITS-1)+SDRAM_BANK_BITS) downto 0);
|
||||
|
||||
-- SDRAM domain signals.
|
||||
signal sdBusy : std_logic;
|
||||
signal sdCycle : integer range 0 to 31;
|
||||
signal sdDone : std_logic;
|
||||
shared variable sdCmd : std_logic_vector(4 downto 0);
|
||||
signal sdRefreshCount : unsigned(11 downto 0);
|
||||
signal sdAutoRefresh : std_logic;
|
||||
signal sdResetTimer : unsigned(WORD_8BIT_RANGE);
|
||||
signal sdInResetCounter : unsigned(WORD_8BIT_RANGE);
|
||||
signal sdIsReady : std_logic;
|
||||
signal sdActiveRow : BankArray;
|
||||
signal sdActiveBank : std_logic_vector(1 downto 0);
|
||||
signal sdWriteColumnAddr : unsigned(SDRAM_COLUMN_BITS-1 downto 0); -- Address at byte level as bit 0 is used as part of the fifo write enable.
|
||||
signal sdWriteCnt : integer range 0 to SDRAM_COLUMNS-1;
|
||||
|
||||
-- CPU domain signals.
|
||||
signal cpuBusy : std_logic;
|
||||
signal cpuDQM : std_logic_vector(3 downto 0);
|
||||
signal cpuBank : natural range 0 to SDRAM_BANKS-1;
|
||||
signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0);
|
||||
signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal cpuDoneLast : std_logic;
|
||||
signal cpuIsWriting : std_logic;
|
||||
signal cpuLastEN : std_logic;
|
||||
signal cpuCachedBank : std_logic_vector(SDRAM_BANK_BITS-1 downto 0);
|
||||
signal cpuCachedRow : BankCacheArray;
|
||||
signal wbACK : std_logic;
|
||||
|
||||
-- Infer a BRAM array for 4 banks of 16bit words. 32bit is created by 2 arrays.
|
||||
type ramArray is array(natural range 0 to ((SDRAM_COLUMNS/2)*4)-1) of std_logic_vector(WORD_8BIT_RANGE);
|
||||
|
||||
-- Declare the BRAM arrays for 32bit as a set of 4 x 8bit banks.
|
||||
shared variable fifoCache_3 : ramArray :=
|
||||
(
|
||||
others => X"00"
|
||||
);
|
||||
shared variable fifoCache_2 : ramArray :=
|
||||
(
|
||||
others => X"00"
|
||||
);
|
||||
shared variable fifoCache_1 : ramArray :=
|
||||
(
|
||||
others => X"00"
|
||||
);
|
||||
shared variable fifoCache_0 : ramArray :=
|
||||
(
|
||||
others => X"00"
|
||||
);
|
||||
|
||||
-- Fifo control signals.
|
||||
signal fifoDataOutHi : std_logic_vector(WORD_16BIT_RANGE);
|
||||
signal fifoDataOutLo : std_logic_vector(WORD_16BIT_RANGE);
|
||||
signal fifoDataInHi : std_logic_vector(WORD_16BIT_RANGE);
|
||||
signal fifoDataInLo : std_logic_vector(WORD_16BIT_RANGE);
|
||||
signal fifoSdWREN_1 : std_logic;
|
||||
signal fifoSdWREN_0 : std_logic;
|
||||
signal fifoCPUWREN_3 : std_logic;
|
||||
signal fifoCPUWREN_2 : std_logic;
|
||||
signal fifoCPUWREN_1 : std_logic;
|
||||
signal fifoCPUWREN_0 : std_logic;
|
||||
begin
|
||||
|
||||
-- Main FSM for SDRAM control and refresh.
|
||||
process(ALL)
|
||||
begin
|
||||
|
||||
if (SDRAM_RST = '1') then
|
||||
sdResetTimer <= (others => '0'); -- 0 upto 127
|
||||
sdInResetCounter <= (others => '1'); -- 255 downto 0
|
||||
sdAutoRefresh <= '0';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
sdIsReady <= '0';
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
SDRAM_DQM <= (others => '1');
|
||||
sdCycle <= 0;
|
||||
sdDone <= '0';
|
||||
fifoSdWREN_0 <= '0';
|
||||
fifoSdWREN_1 <= '0';
|
||||
sdWriteColumnAddr <= (others => '0');
|
||||
|
||||
elsif rising_edge(SDRAM_CLK) then
|
||||
|
||||
-- Write Enables are only 1 clock wide, clear on each cycle.
|
||||
fifoSdWREN_1 <= '0';
|
||||
fifoSdWREN_0 <= '0';
|
||||
|
||||
-- Tri-state control, set the SDRAM databus to tri-state if we are not in write mode.
|
||||
if (cpuIsWriting = '0') then
|
||||
SDRAM_DQ <= (others => 'Z');
|
||||
end if;
|
||||
|
||||
-- If no specific command given the default is NOP.
|
||||
sdCmd := CMD_NOP;
|
||||
|
||||
-- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied.
|
||||
if (sdIsReady = '0') then
|
||||
sdResetTimer <= sdResetTimer + 1;
|
||||
|
||||
-- 1uS timer.
|
||||
if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then
|
||||
sdResetTimer <= (others => '0');
|
||||
sdInResetCounter <= sdInResetCounter - 1;
|
||||
end if;
|
||||
|
||||
-- Every 1uS check for the next init action.
|
||||
if (sdResetTimer = 0) then
|
||||
|
||||
-- 200uS wait, no action as the SDRAM starts up.
|
||||
-- ie. 255 downto 55
|
||||
|
||||
-- Precharge all banks
|
||||
if(sdInResetCounter = 55) then
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- Load the Mode register with our parameters.
|
||||
if(sdInResetCounter = 39) then
|
||||
sdCmd := CMD_LOAD_MODE;
|
||||
SDRAM_ADDR <= MODE;
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- SDRAM ready.
|
||||
if(sdInResetCounter = 20) then
|
||||
sdIsReady <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
-- Counter to time periods between autorefresh.
|
||||
sdRefreshCount <= sdRefreshCount + 1;
|
||||
|
||||
-- This mechanism is used to reduce the possibility of metastability issues due to differing clocks.
|
||||
-- We only act after both Busy signals are high, thus one SDRAM clock after cpuBusy goes high.
|
||||
sdBusy <= cpuBusy;
|
||||
|
||||
-- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are
|
||||
-- issued in a tRFC period. Other bus operations are stalled during this period.
|
||||
if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then
|
||||
sdAutoRefresh <= '1';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '1';
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
|
||||
-- In auto refresh period.
|
||||
elsif (sdAutoRefresh = '1') then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
when CYCLE_RFSH_START =>
|
||||
sdCmd := CMD_AUTO_REFRESH;
|
||||
|
||||
when CYCLE_RFSH_END =>
|
||||
-- reset the count.
|
||||
sdAutoRefresh <= '0';
|
||||
sdCycle <= 0;
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
|
||||
when CYCLE_PRECHARGE =>
|
||||
-- If the bank is not open then no need to precharge, move onto RAS.
|
||||
if (sdActiveBank(cpuBank) = '0') then
|
||||
sdCycle <= CYCLE_RAS_START;
|
||||
|
||||
-- If the requested row is already active, go to CAS for immediate access to this row.
|
||||
elsif (sdActiveRow(cpuBank) = cpuRow) then
|
||||
sdCycle <= CYCLE_CAS_START;
|
||||
|
||||
-- Otherwise we close out the open bank by issuing a PRECHARGE.
|
||||
else
|
||||
sdCmd := CMD_PRECHARGE;
|
||||
SDRAM_ADDR(10) <= '0';
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length));
|
||||
sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active.
|
||||
end if;
|
||||
|
||||
-- Open the requested row.
|
||||
when CYCLE_RAS_START =>
|
||||
sdCmd := CMD_ACTIVE;
|
||||
SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address.
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select.
|
||||
sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active
|
||||
sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active.
|
||||
|
||||
-- CAS start, for 32 bit chips, only 1 CAS cycle is needed, for 16bit chips we need 2 to read/write 2x16bit words.
|
||||
when CYCLE_CAS_START =>
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (cpuIsWriting = '1') then
|
||||
sdCmd := CMD_WRITE;
|
||||
if SDRAM_DATAWIDTH = 32 then
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 2) & '0' & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing 32bit data with no auto precharge
|
||||
SDRAM_DQ <= cpuDataIn; -- Assign corresponding data to the SDRAM databus.
|
||||
SDRAM_DQM <= not cpuDQM(3 downto 0);
|
||||
sdDone <= '1';
|
||||
sdCycle <= CYCLE_END;
|
||||
|
||||
-- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers.
|
||||
fifoDataInHi <= fifoDataOutHi;
|
||||
fifoDataInLo <= fifoDataOutLo;
|
||||
|
||||
elsif SDRAM_DATAWIDTH = 16 then
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
SDRAM_DQ <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus.
|
||||
SDRAM_DQM <= not cpuDQM(3 downto 2);
|
||||
|
||||
-- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers.
|
||||
fifoDataInHi <= fifoDataOutHi;
|
||||
else
|
||||
report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error;
|
||||
end if;
|
||||
|
||||
else
|
||||
-- Setup for a read.
|
||||
sdCmd := CMD_READ;
|
||||
SDRAM_ADDR <= (others => '0');
|
||||
SDRAM_DQM <= "00"; -- For reads dont mask the data output.
|
||||
sdWriteCnt <= SDRAM_COLUMNS-1;
|
||||
sdWriteColumnAddr <= (others => '1');
|
||||
end if;
|
||||
|
||||
-- For writes, this state writes out the second word of a 32bit word if we have a 16bit wide SDRAM chip.
|
||||
--
|
||||
when CYCLE_WRITE_END =>
|
||||
-- When writing, setup for a write with preset mask with the correct word.
|
||||
if (cpuIsWriting = '1') then
|
||||
SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge
|
||||
sdCmd := CMD_WRITE;
|
||||
SDRAM_DQM <= not cpuDQM(1 downto 0);
|
||||
SDRAM_DQ <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0);
|
||||
sdDone <= '1';
|
||||
sdCycle <= CYCLE_END;
|
||||
|
||||
-- A fake statement used to convince Quartus Prime to infer block ram for the fifo and not use registers.
|
||||
fifoDataInLo <= fifoDataOutLo;
|
||||
end if;
|
||||
|
||||
-- Data is available after CAS Latency (2 or 3) clocks after the read request.
|
||||
-- The data is read as a full page burst, 1 clock per word.
|
||||
when CYCLE_READ_START =>
|
||||
|
||||
if SDRAM_DATAWIDTH = 32 then
|
||||
fifoSdWREN_1 <= '1';
|
||||
fifoSdWREN_0 <= '1';
|
||||
sdWriteCnt <= sdWriteCnt - 2;
|
||||
sdWriteColumnAddr <= sdWriteColumnAddr + 2;
|
||||
fifoDataInHi <= SDRAM_DQ(WORD_UPPER_16BIT_RANGE);
|
||||
fifoDataInLo <= SDRAM_DQ(WORD_LOWER_16BIT_RANGE);
|
||||
|
||||
if sdWriteCnt > 1 then
|
||||
sdCycle <= CYCLE_READ_START;
|
||||
end if;
|
||||
|
||||
elsif SDRAM_DATAWIDTH = 16 then
|
||||
if fifoSdWREN_1 = '0' then
|
||||
fifoSdWREN_1 <= '1';
|
||||
fifoDataInHi <= SDRAM_DQ;
|
||||
else
|
||||
fifoSdWREN_0 <= '1';
|
||||
fifoDataInLo <= SDRAM_DQ;
|
||||
end if;
|
||||
sdWriteCnt <= sdWriteCnt - 1;
|
||||
sdWriteColumnAddr <= sdWriteColumnAddr + 1;
|
||||
|
||||
if sdWriteCnt > 0 then
|
||||
sdCycle <= CYCLE_READ_START;
|
||||
end if;
|
||||
|
||||
else
|
||||
report "SDRAM datawidth parameter invalid, should be 16 or 32!" severity error;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ_END =>
|
||||
sdDone <= '1';
|
||||
|
||||
when CYCLE_END =>
|
||||
sdCycle <= 0;
|
||||
sdDone <= '0';
|
||||
|
||||
-- Other states are wait states, waiting for the correct time slot for SDRAM access.
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
sdCycle <= 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- drive control signals according to current command
|
||||
SDRAM_CKE <= sdCmd(4);
|
||||
SDRAM_CS_n <= sdCmd(3);
|
||||
SDRAM_RAS_n <= sdCmd(2);
|
||||
SDRAM_CAS_n <= sdCmd(1);
|
||||
SDRAM_WE_n <= sdCmd(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent
|
||||
-- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know
|
||||
-- when the transation is complete and data read.
|
||||
--
|
||||
process(ALL)
|
||||
variable bank : std_logic_vector(1 downto 0);
|
||||
variable row : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
variable writeThru : std_logic;
|
||||
begin
|
||||
|
||||
-- Setup the bank and row as variables to make code reading easier.
|
||||
bank := WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1));
|
||||
row := WB_ADR_I(SDRAM_ADDR_BITS-2 downto (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS));
|
||||
|
||||
-- For write operations, if the cached page row for the current bank is the same as the row given by the cpu then we write to both the SDRAM and to the cache.
|
||||
if cpuCachedBank(to_integer(unsigned(bank))) = '1' and cpuCachedRow(to_integer(unsigned(bank))) = WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then
|
||||
writeThru := '1';
|
||||
else
|
||||
writeThru := '0';
|
||||
end if;
|
||||
|
||||
-- Setup signals to initial state, critical they start at the right values.
|
||||
if (WB_RST_I = '1') then
|
||||
cpuDoneLast <= '0';
|
||||
cpuBusy <= '0';
|
||||
cpuBank <= 0;
|
||||
cpuRow <= (others => '0');
|
||||
cpuCol <= (others => '0');
|
||||
cpuDQM <= (others => '1');
|
||||
cpuLastEN <= '0';
|
||||
cpuCachedBank <= (others => '0');
|
||||
cpuCachedRow <= ( others => (others => '0') );
|
||||
cpuIsWriting <= '0';
|
||||
fifoCPUWREN_3 <= '0';
|
||||
fifoCPUWREN_2 <= '0';
|
||||
fifoCPUWREN_1 <= '0';
|
||||
fifoCPUWREN_0 <= '0';
|
||||
wbACK <= '0';
|
||||
|
||||
-- Wait for the SDRAM to become ready by holding the CPU in a wait state.
|
||||
elsif sdIsReady = '0' then
|
||||
cpuBusy <= '1';
|
||||
|
||||
elsif rising_edge(WB_CLK) then
|
||||
|
||||
-- CPU Cache writes are only 1 cycle wide, so clear any asserted write.
|
||||
fifoCPUWREN_3 <= '0';
|
||||
fifoCPUWREN_2 <= '0';
|
||||
fifoCPUWREN_1 <= '0';
|
||||
fifoCPUWREN_0 <= '0';
|
||||
|
||||
if wbACK = '1' then
|
||||
wbACK <= '0';
|
||||
end if;
|
||||
|
||||
-- Detect a Wishbone cycle and commence an SDRAM access.
|
||||
if (WB_STB_I = '1' and WB_CYC_I = '1' and cpuBusy = '0' and wbACK = '0') then
|
||||
|
||||
-- Organisation of the memory is as follows:
|
||||
--
|
||||
-- Bank: [(SDRAM_ADDR_BITS-1) .. (SDRAM_ADDR_BITS-1)] & [((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) .. (SDRAM_COLUMN_BITS+1)]
|
||||
-- Row: [(SDRAM_ADDR_BITS-2) .. (SDRAM_COLUMN_BITS+SDRAM_BANK_BITS)]
|
||||
-- Column: [(SDRAM_COLUMN_BITS downto 2)]
|
||||
-- The bank is split so that the Bank MSB splits the SDRAM in 2, upper and lower segment, this is because Stack normally resides in the top upper
|
||||
-- segment and code in the bottom lower segment. The remaining bank bits are split at the page level such that 2 or more pages residing in different
|
||||
-- banks are contiguous, hoping to gain a little performance benefit through having a wider spread for code caching and stack caching and write thru.
|
||||
--
|
||||
cpuBank <= to_integer(unsigned(bank));
|
||||
cpuRow <= row;
|
||||
cpuCol <= WB_ADR_I(SDRAM_COLUMN_BITS downto 2) & '0';
|
||||
cpuDQM <= WB_SEL_I;
|
||||
cpuDataIn <= WB_DATA_I;
|
||||
|
||||
-- For write operations, we write direct to memory. If the data is in cache then a write-thru is performed to preserve the cached bank.
|
||||
if WB_WE_I = '1' then
|
||||
|
||||
-- If we are writing to a cached page, update the changed bytes in cache.
|
||||
if writeThru = '1' then
|
||||
if WB_SEL_I(0) then
|
||||
fifoCPUWREN_0 <= '1';
|
||||
end if;
|
||||
if WB_SEL_I(1) then
|
||||
fifoCPUWREN_1 <= '1';
|
||||
end if;
|
||||
if WB_SEL_I(2) then
|
||||
fifoCPUWREN_2 <= '1';
|
||||
end if;
|
||||
if WB_SEL_I(3) then
|
||||
fifoCPUWREN_3 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation.
|
||||
cpuIsWriting <= WB_WE_I;
|
||||
cpuBusy <= '1';
|
||||
|
||||
-- For reads, if the row is cached then we just fall through to perform a read operation from cache otherwise the
|
||||
-- SDRAM needs to be instructed to read a page into cache before reading.
|
||||
--
|
||||
elsif cpuCachedBank(to_integer(unsigned(bank))) = '0' or cpuCachedRow(to_integer(unsigned(bank))) /= WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row then
|
||||
|
||||
cpuCachedBank(to_integer(unsigned(bank))) <= '1';
|
||||
cpuCachedRow (to_integer(unsigned(bank))) <= WB_ADR_I(SDRAM_ADDR_BITS-1) & WB_ADR_I((SDRAM_COLUMN_BITS+SDRAM_BANK_BITS-1) downto (SDRAM_COLUMN_BITS+1)) & row;
|
||||
|
||||
-- Set the flags, cpuBusy indicates to the SDRAM FSM to perform an operation.
|
||||
cpuBusy <= '1';
|
||||
|
||||
else
|
||||
wbACK <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Note SDRAM activity via a previous/last signal.
|
||||
cpuDoneLast <= sdDone;
|
||||
|
||||
-- A change in the Done signal then we end the SDRAM request and release the CPU.
|
||||
if cpuDoneLast = '1' and sdDone = '0' then
|
||||
cpuBusy <= '0';
|
||||
cpuIsWriting <= '0';
|
||||
wbACK <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- System bus control signals.
|
||||
SDRAM_READY <= sdIsReady;
|
||||
|
||||
-- Wishbone bus control signals.
|
||||
WB_ACK_O <= wbACK;
|
||||
|
||||
--- Throttle not needed.
|
||||
WB_HALT_O <= '0';
|
||||
|
||||
--- Error not yet implemented.
|
||||
WB_ERR_O <= '0';
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
-- Inferred Dual Port RAM.
|
||||
--
|
||||
-- The dual port ram is used to buffer a full page within the SDRAM, one buffer for each bank. The addressing is such
|
||||
-- that half of the banks appear in the lower segment of the address space and half in the top segment, the MSB of the
|
||||
-- SDRAM address is used for the split. This is to cater for stack where typically, on the ZPU, the stack would reside
|
||||
-- in the very top of memory working down and the applications would reside at the bottom of the memory working up.
|
||||
--
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- SDRAM Side of dual port RAM.
|
||||
-- For Read: fifoDataOutHi <= fifoCache_3(sdWriteColumnAddr)
|
||||
-- fifoDataOutLo <= fifoCache_0(sdWriteColumnAddr)
|
||||
-- For Write: fifoCache_3 _1 <= fifoDataIn when sdWriteColumnAddr(0) = '0'
|
||||
-- fifoCache_2 _0 <= fifoDataIn when sdWriteColumnAddr(0) = '1'
|
||||
-- fifoSdWREN must be asserted ('1') for write operations.
|
||||
process(ALL)
|
||||
variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0);
|
||||
begin
|
||||
-- Setup the address based on the index (sdWriteColumnAddr) and the bank (cpuBank) as the cache is linear for 4 banks.
|
||||
--
|
||||
cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & sdWriteColumnAddr(SDRAM_COLUMN_BITS-1 downto 1);
|
||||
|
||||
if rising_edge(SDRAM_CLK) then
|
||||
if fifoSdWREN_1 = '1' then
|
||||
fifoCache_3(to_integer(cacheAddr)) := fifoDataInHi(WORD_UPPER_16BIT_RANGE);
|
||||
fifoCache_2(to_integer(cacheAddr)) := fifoDataInHi(WORD_LOWER_16BIT_RANGE);
|
||||
else
|
||||
fifoDataOutHi(WORD_UPPER_16BIT_RANGE) <= fifoCache_3(to_integer(cacheAddr));
|
||||
fifoDataOutHi(WORD_LOWER_16BIT_RANGE) <= fifoCache_2(to_integer(cacheAddr));
|
||||
end if;
|
||||
|
||||
if fifoSdWREN_0 = '1' then
|
||||
fifoCache_1(to_integer(cacheAddr)) := fifoDataInLo(WORD_UPPER_16BIT_RANGE);
|
||||
fifoCache_0(to_integer(cacheAddr)) := fifoDataInLo(WORD_LOWER_16BIT_RANGE);
|
||||
else
|
||||
fifoDataOutLo(WORD_UPPER_16BIT_RANGE) <= fifoCache_1(to_integer(cacheAddr));
|
||||
fifoDataOutLo(WORD_LOWER_16BIT_RANGE) <= fifoCache_0(to_integer(cacheAddr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- CPU Side of dual port RAM, byte addressable.
|
||||
-- For Read: DATA_OUT <= fifoCache(bank + ADDR(COLUMN_BITS .. 2))
|
||||
-- For Write: fifoCache(0..3) <= cpuDataIn
|
||||
process(ALL)
|
||||
variable cacheAddr : unsigned(SDRAM_COLUMN_BITS-2+SDRAM_BANK_BITS downto 0);
|
||||
begin
|
||||
-- Setup the address based on the column address bits, 32 bit aligned and the bank (cpuBank) as the cache is linear for 4 banks.
|
||||
--
|
||||
cacheAddr := to_unsigned(cpuBank, SDRAM_BANK_BITS) & unsigned(WB_ADR_I(SDRAM_COLUMN_BITS downto 2));
|
||||
|
||||
if rising_edge(WB_CLK) then
|
||||
if fifoCPUWREN_3 = '1' then
|
||||
fifoCache_3(to_integer(cacheAddr)) := cpuDataIn(31 downto 24);
|
||||
else
|
||||
WB_DATA_O((SDRAM_DATAWIDTH*2)-1 downto ((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2)))<= fifoCache_3(to_integer(unsigned(cacheAddr)));
|
||||
end if;
|
||||
|
||||
if fifoCPUWREN_2 = '1' then
|
||||
fifoCache_2(to_integer(cacheAddr)) := cpuDataIn(23 downto 16);
|
||||
else
|
||||
WB_DATA_O(((SDRAM_DATAWIDTH*2)-(SDRAM_DATAWIDTH/2))-1 downto SDRAM_DATAWIDTH) <= fifoCache_2(to_integer(unsigned(cacheAddr)));
|
||||
end if;
|
||||
|
||||
if fifoCPUWREN_1 = '1' then
|
||||
fifoCache_1(to_integer(cacheAddr)) := cpuDataIn(15 downto 8);
|
||||
else
|
||||
WB_DATA_O(SDRAM_DATAWIDTH-1 downto SDRAM_DATAWIDTH/2) <= fifoCache_1(to_integer(unsigned(cacheAddr)));
|
||||
end if;
|
||||
|
||||
if fifoCPUWREN_0 = '1' then
|
||||
fifoCache_0(to_integer(cacheAddr)) := cpuDataIn(7 downto 0);
|
||||
else
|
||||
WB_DATA_O((SDRAM_DATAWIDTH/2)-1 downto 0) <= fifoCache_0(to_integer(unsigned(cacheAddr)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Structure;
|
||||
@@ -1,159 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: sram.vhd
|
||||
-- Created: September 2019
|
||||
-- Author(s): Philip Smart
|
||||
-- Description: WishBone encapsulation of BRAM memory.
|
||||
--
|
||||
-- Credits:
|
||||
-- Copyright: (c) 2019 Philip Smart <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial creation.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity SRAM is
|
||||
generic (
|
||||
addrbits : integer := 16 -- Size, in bits (representing bytes), of total memory to allocate.
|
||||
);
|
||||
port (
|
||||
-- Wishbone Bus --
|
||||
WB_CLK_I : in std_logic; -- WishBone master clock
|
||||
WB_RST_I : in std_logic; -- high active sync reset
|
||||
WB_CYC_I : in std_logic;
|
||||
WB_TGC_I : in std_logic_vector(06 downto 0); -- cycle tag
|
||||
WB_ADR_I : in std_logic_vector(addrbits-1 downto 0); -- adr in
|
||||
WB_DATA_I : in std_logic_vector(31 downto 0); -- write data
|
||||
WB_DATA_O : out std_logic_vector(31 downto 0); -- read data
|
||||
WB_SEL_I : in std_logic_vector(03 downto 0); -- data quantity
|
||||
WB_WE_I : in std_logic; -- write enable
|
||||
WB_STB_I : in std_logic; -- valid cycle
|
||||
WB_ACK_O : out std_logic; -- acknowledge
|
||||
WB_CTI_I : in std_logic_vector(2 downto 0); -- 000 Classic cycle, 001 Constant address burst cycle, 010 Incrementing burst cycle, 111 End-of-Burst
|
||||
WB_HALT_O : out std_logic; -- throttle master
|
||||
WB_ERR_O : out std_logic -- abnormal cycle termination
|
||||
);
|
||||
end SRAM;
|
||||
|
||||
architecture Behavioral of SRAM is
|
||||
|
||||
--- Muxed ACK signal.
|
||||
signal WB_ACK_O_INT : std_logic;
|
||||
|
||||
-- Define memory as an array of 4x8bit blocks to allow for individual byte write/read.
|
||||
type ramArray is array(natural range 0 to (2**(addrbits-2))-1) of std_logic_vector(7 downto 0);
|
||||
|
||||
shared variable RAM0 : ramArray :=
|
||||
(
|
||||
others => x"AA"
|
||||
);
|
||||
shared variable RAM1 : ramArray :=
|
||||
(
|
||||
others => x"55"
|
||||
);
|
||||
shared variable RAM2 : ramArray :=
|
||||
(
|
||||
others => x"AA"
|
||||
);
|
||||
shared variable RAM3 : ramArray :=
|
||||
(
|
||||
others => x"55"
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
-- RAM Byte 0 - bits 7 to 0
|
||||
process(WB_CLK_I)
|
||||
begin
|
||||
if rising_edge(WB_CLK_I) then
|
||||
if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(0) = '1' then
|
||||
RAM0(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(7 downto 0);
|
||||
else
|
||||
WB_DATA_O(7 downto 0) <= RAM0(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2))));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- RAM Byte 1 - bits 15 to 8
|
||||
process(WB_CLK_I)
|
||||
begin
|
||||
if rising_edge(WB_CLK_I) then
|
||||
if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(1) = '1' then
|
||||
RAM1(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(15 downto 8);
|
||||
else
|
||||
WB_DATA_O(15 downto 8) <= RAM1(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2))));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- RAM Byte 2 - bits 23 to 16
|
||||
process(WB_CLK_I)
|
||||
begin
|
||||
if rising_edge(WB_CLK_I) then
|
||||
if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(2) = '1' then
|
||||
RAM2(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(23 downto 16);
|
||||
else
|
||||
WB_DATA_O(23 downto 16) <= RAM2(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2))));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- RAM Byte 3 - bits 31 to 24
|
||||
process(WB_CLK_I)
|
||||
begin
|
||||
if rising_edge(WB_CLK_I) then
|
||||
if WB_WE_I = '1' and WB_STB_I = '1' and WB_SEL_I(3) = '1' then
|
||||
RAM3(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2)))) := WB_DATA_I(31 downto 24);
|
||||
else
|
||||
WB_DATA_O(31 downto 24) <= RAM3(to_integer(unsigned(WB_ADR_I(addrbits-1 downto 2))));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- WishBone control.
|
||||
WISHBONECTL: process(WB_CLK_I)
|
||||
begin
|
||||
if rising_edge(WB_CLK_I) then
|
||||
|
||||
--- ACK Control
|
||||
if (WB_RST_I = '1') then
|
||||
WB_ACK_O_INT <= '0';
|
||||
elsif (WB_CTI_I = "000") or (WB_CTI_I = "111") then
|
||||
WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT);
|
||||
else
|
||||
WB_ACK_O_INT <= WB_STB_I;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--- ACK Signal
|
||||
WB_ACK_O <= WB_ACK_O_INT;
|
||||
|
||||
--- Throttle
|
||||
WB_HALT_O <= '0';
|
||||
|
||||
--- Error
|
||||
WB_ERR_O <= '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,50 +0,0 @@
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
entity oddrff is
|
||||
port (
|
||||
CLK: in std_ulogic;
|
||||
D0: in std_logic;
|
||||
D1: in std_logic;
|
||||
O: out std_ulogic
|
||||
);
|
||||
|
||||
end entity oddrff;
|
||||
|
||||
architecture behave of oddrff is
|
||||
signal D0_v, D1_v, O_v: std_logic_vector(0 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
ALTDDIO_OUT_component : ALTDDIO_OUT
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "OFF",
|
||||
intended_device_family => "Cyclone IV E",
|
||||
invert_output => "OFF",
|
||||
lpm_hint => "UNUSED",
|
||||
lpm_type => "altddio_out",
|
||||
oe_reg => "UNREGISTERED",
|
||||
power_up_high => "OFF",
|
||||
width => 1
|
||||
)
|
||||
PORT MAP (
|
||||
datain_h => D1_v,
|
||||
datain_l => D0_v,
|
||||
outclock => CLK,
|
||||
dataout => O_v
|
||||
);
|
||||
|
||||
D1_v(0) <= D0;
|
||||
D0_v(0) <= D1;
|
||||
O <= O_v(0);
|
||||
|
||||
end behave;
|
||||
@@ -1,2 +0,0 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sdram.vhd ]
|
||||
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ]
|
||||
@@ -1,26 +0,0 @@
|
||||
derive_pll_clocks
|
||||
|
||||
#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
#{*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
|
||||
#create_generated_clock -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] \
|
||||
# -name MEMCLK [get_ports {MEMCLK}]
|
||||
#create_generated_clock -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] -multiply_by 1 \
|
||||
# -name MEMCLK [get_ports {MEMCLK}]
|
||||
#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 2 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
|
||||
#create_generated_clock -name {MEMCLK} -source [get_pins -compatibility_mode {mypll|altpll_component|pll|clk[1]}] -master_clock {MEMCLK} [get_ports {MEMCLK}]
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
|
||||
set_input_delay -max -clock MEMCLK 6.4ns [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -min -clock MEMCLK 3.7ns [get_ports SDRAM_DQ[*]]
|
||||
|
||||
# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
#set_multicycle_path -from [get_clocks {MEMCLK}] \
|
||||
# -to [get_clocks {SYSCLK}] \
|
||||
# -setup 2
|
||||
|
||||
|
||||
set_output_delay -max -clock MEMCLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
set_output_delay -min -clock MEMCLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
@@ -1,19 +0,0 @@
|
||||
derive_pll_clocks
|
||||
|
||||
#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
create_generated_clock -source [get_pins -compatibility_mode {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
|
||||
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
|
||||
|
||||
# -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
|
||||
# -to [get_clocks {*mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] \
|
||||
# -setup 2
|
||||
|
||||
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_ADDR* SDRAM_BA* SDRAM_CS SDRAM_WE SDRAM_RAS SDRAM_CAS SDRAM_CKE}]
|
||||
@@ -1,488 +0,0 @@
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Name: sdram.vhd
|
||||
-- Created: September 2019
|
||||
-- Original Author: Stephen J. Leary 2013-2014
|
||||
-- VHDL Author: Philip Smart
|
||||
-- Description: Original Wishbone module written by Stephen J. Leary 2013-2014 in Verilog for use
|
||||
-- with the MT48LC16M16 chip.
|
||||
-- It has been translated into VHDL and adapted for the system bus and undergoing
|
||||
-- extensive modifications to work with the ZPU EVO processor, specifically burst
|
||||
-- tuning to enhance L2 Cache Fill performance.
|
||||
-- Credits:
|
||||
-- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved.
|
||||
-- VHDL translation, sysbus adaptation and enhancements (c) 2019 Philip Smart
|
||||
-- <philip.smart@net2net.org>
|
||||
--
|
||||
-- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog
|
||||
-- source code.
|
||||
-- November 2019 - Adapted for the system bus for use when no Wishbone interface is
|
||||
-- instantiated in the ZPU Evo.
|
||||
--
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
-- This source file is free software: you can redistribute it and-or modify
|
||||
-- it under the terms of the GNU General Public License as published
|
||||
-- by the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This source file is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http:--www.gnu.org-licenses->.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity SDRAM is
|
||||
generic (
|
||||
MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions.
|
||||
SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row).
|
||||
SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM.
|
||||
SDRAM_BANKS : integer := 4 -- Number of banks in the SDRAM.
|
||||
);
|
||||
port (
|
||||
-- SDRAM Interface
|
||||
SDRAM_CLK : in std_logic; -- sdram is accessed at 100MHz
|
||||
SDRAM_RST : in std_logic; -- reset the sdram controller.
|
||||
SDRAM_CKE : out std_logic; -- clock enable.
|
||||
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
|
||||
SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus
|
||||
SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks.
|
||||
SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM
|
||||
SDRAM_CS_n : out std_logic; -- Single chip select
|
||||
SDRAM_WE_n : out std_logic; -- write enable
|
||||
SDRAM_RAS_n : out std_logic; -- row address select
|
||||
SDRAM_CAS_n : out std_logic; -- columns address select
|
||||
SDRAM_READY : out std_logic; -- sd ready.
|
||||
|
||||
-- CPU Interface
|
||||
CLK : in std_logic; -- System master clock
|
||||
RESET : in std_logic; -- high active sync reset
|
||||
ADDR : in std_logic_vector(21 downto 0);
|
||||
DATA_IN : in std_logic_vector(31 downto 0); -- write data
|
||||
DATA_OUT : out std_logic_vector(31 downto 0); -- read data
|
||||
WRITE_BYTE : in std_logic; -- write a single byte as specified in A1:A0
|
||||
WRITE_HWORD : in std_logic; -- write a 16bit word as specified in A1
|
||||
CS : in std_logic; -- Chip Select.
|
||||
WREN : in std_logic; -- Write enable.
|
||||
RDEN : in std_logic; -- Read enable.
|
||||
BUSY : out std_logic -- Memory is busy, hold CPU.
|
||||
);
|
||||
end SDRAM;
|
||||
|
||||
architecture Structure of SDRAM is
|
||||
|
||||
-- Constants to define the structure of the SDRAM in bits for provisioning of signals.
|
||||
constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS);
|
||||
constant SDRAM_COLUMN_BITS: integer := log2ceil(SDRAM_COLUMNS);
|
||||
constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS);
|
||||
constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS);
|
||||
constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS);
|
||||
|
||||
-- Constants for correct operation of the SDRAM, these values are taken from the datasheet of the target device.
|
||||
--
|
||||
constant tRCD : integer := 4; -- tRCD - RAS to CAS minimum period, ie. 20ns -> 2 cycles@100MHz
|
||||
constant tRP : integer := 4; -- tRP - Precharge delay, min time for a precharge command to complete, ie. 15ns -> 2 cycles@100MHz
|
||||
constant tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete, ie. 66ns
|
||||
constant tREF : integer := 64; -- tREF - period of time a complete refresh of all rows is made within.
|
||||
constant RAM_CLK : integer := 50000000; -- SDRAM Clock in Hertz
|
||||
|
||||
-- Command table for a standard SDRAM.
|
||||
--
|
||||
-- Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ
|
||||
-- COMMAND INHIBIT (NOP) H X X X X X X
|
||||
-- NO OPERATION (NOP) L H H H X X X
|
||||
-- ACTIVE (select bank and activate row) L L H H X Bank/row X
|
||||
-- READ (select bank and column, and start READ burst) L H L H L/H Bank/col X
|
||||
-- WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid
|
||||
-- BURST TERMINATE L H H L X X Active
|
||||
-- PRECHARGE (Deactivate row in bank or banks) L L H L X Code X
|
||||
-- AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X
|
||||
-- LOAD MODE REGISTER L L L L X Op-code X
|
||||
-- Write enable/output enable X X X X L X Active
|
||||
-- Write inhibit/output High-Z X X X X H X High-Z
|
||||
constant CMD_INHIBIT : std_logic_vector(3 downto 0) := "1111";
|
||||
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
|
||||
constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
|
||||
constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
|
||||
constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
|
||||
constant CMD_BURST_TERMINATE : std_logic_vector(3 downto 0) := "0110";
|
||||
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
|
||||
constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";
|
||||
constant CMD_LOAD_MODE : std_logic_vector(3 downto 0) := "0000";
|
||||
|
||||
-- Load Mode Register setting for a standard SDRAM.
|
||||
--
|
||||
-- xx:10 = Reserved :
|
||||
-- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
|
||||
-- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
|
||||
-- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
|
||||
-- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
|
||||
-- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
|
||||
-- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
|
||||
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
|
||||
constant WRITE_BURST_MODE : std_logic := '1';
|
||||
constant OP_MODE : std_logic_vector(1 downto 0) := "00";
|
||||
constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
|
||||
constant BURST_TYPE : std_logic := '0';
|
||||
constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000";
|
||||
constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS));
|
||||
|
||||
-- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time.
|
||||
--
|
||||
constant CYCLE_PRECHARGE : integer := 0; -- 0
|
||||
constant CYCLE_RAS_START : integer := tRP; -- 3
|
||||
constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4
|
||||
constant CYCLE_CAS0 : integer := CYCLE_RAS_START + tRCD; -- 3 + tRCD
|
||||
constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + tRCD
|
||||
constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_END : integer := CYCLE_READ1 + 4; -- 9 + tRCD + CAS_LATENCY
|
||||
constant CYCLE_RFSH_START : integer := CYCLE_RAS_START; -- 3
|
||||
constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((tRFC/RAM_CLK) * 10000000) + 1; -- 3 + tRFC in clock ticks.
|
||||
|
||||
-- Period in clock cycles between SDRAM refresh cycles.
|
||||
constant REFRESH_PERIOD : integer := (RAM_CLK / (tREF * SDRAM_ROWS)) - CYCLE_END;
|
||||
|
||||
type BankArray is array(natural range 0 to 3) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
|
||||
-- Cache for holding burst reads to allow for differing speeds of WishBone Master.
|
||||
type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE);
|
||||
signal readCache : DataCacheArray;
|
||||
attribute ramstyle : string;
|
||||
attribute ramstyle of readCache : signal is "logic";
|
||||
signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
|
||||
|
||||
signal sbBusy : std_logic;
|
||||
signal sdCycle : integer range 0 to 31;
|
||||
signal sdDone : std_logic;
|
||||
signal sdCmd : std_logic_vector(3 downto 0);
|
||||
signal sdRefreshCount : unsigned(9 downto 0);
|
||||
signal sdAutoRefresh : std_logic;
|
||||
|
||||
signal sdResetTimer : unsigned(7 downto 0);
|
||||
signal sdMuxAddr : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); -- 12 bit multiplexed address bus
|
||||
signal sdDoneLast : std_logic;
|
||||
signal sdInResetCounter : unsigned(7 downto 0);
|
||||
signal sdIsWriting : std_logic;
|
||||
signal isReady : std_logic;
|
||||
signal sdDataOut : std_logic_vector(15 downto 0);
|
||||
signal sdDataIn : std_logic_vector(15 downto 0);
|
||||
signal sdActiveRow : BankArray;
|
||||
signal sdActiveBank : std_logic_vector(1 downto 0);
|
||||
signal sdBank : natural range 0 to 3;
|
||||
signal sdRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
|
||||
signal sdCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0);
|
||||
signal sdDQM : std_logic_vector(1 downto 0);
|
||||
signal sdCKE : std_logic;
|
||||
|
||||
signal cpuDQM : std_logic_vector(3 downto 0);
|
||||
|
||||
signal dout : std_logic_vector(31 downto 0);
|
||||
signal cpuDataIn : std_logic_vector(31 downto 0);
|
||||
begin
|
||||
|
||||
-- Tri-state control of the SDRAM data bus.
|
||||
process(sdIsWriting, SDRAM_DQ, sdDataOut)
|
||||
begin
|
||||
if (sdIsWriting = '1') then
|
||||
SDRAM_DQ <= sdDataOut;
|
||||
sdDataIn <= SDRAM_DQ;
|
||||
else
|
||||
SDRAM_DQ <= (others => 'Z');
|
||||
sdDataIn <= SDRAM_DQ;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Main FSM for SDRAM control and refresh.
|
||||
process(SDRAM_CLK, SDRAM_RST)
|
||||
begin
|
||||
if (SDRAM_RST = '1') then
|
||||
sdResetTimer <= (others => '0'); -- 0 upto 127
|
||||
sdInResetCounter <= (others => '1'); -- 255 downto 0
|
||||
sdMuxAddr <= (others => '0');
|
||||
sdAutoRefresh <= '0';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
isReady <= '0';
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
sdCKE <= '1';
|
||||
sdDQM <= (others => '1');
|
||||
sdCycle <= 0;
|
||||
sdDone <= '0';
|
||||
cacheWriteAddr <= (others => '0');
|
||||
|
||||
elsif rising_edge(SDRAM_CLK) then
|
||||
|
||||
-- If no specific command given the default is NOP.
|
||||
sdCmd <= CMD_NOP;
|
||||
|
||||
-- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied.
|
||||
if (isReady = '0') then
|
||||
sdResetTimer <= sdResetTimer + 1;
|
||||
|
||||
-- 1uS timer.
|
||||
if (sdResetTimer = RAM_CLK/1000000) then
|
||||
sdResetTimer <= (others => '0');
|
||||
sdInResetCounter <= sdInResetCounter - 1;
|
||||
end if;
|
||||
|
||||
-- Every 1uS check for the next init action.
|
||||
if (sdResetTimer = 0) then
|
||||
|
||||
-- 200uS wait, no action as the SDRAM starts up.
|
||||
-- ie. 255 downto 55
|
||||
|
||||
-- Precharge all banks
|
||||
if(sdInResetCounter = 55) then
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
sdMuxAddr(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- Load the Mode register with our parameters.
|
||||
if(sdInResetCounter = 39) then
|
||||
sdCmd <= CMD_LOAD_MODE;
|
||||
sdMuxAddr <= MODE;
|
||||
end if;
|
||||
|
||||
-- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
|
||||
-- the other.
|
||||
if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
end if;
|
||||
|
||||
-- SDRAM ready.
|
||||
if(sdInResetCounter = 20) then
|
||||
isReady <= '1';
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
|
||||
sdRefreshCount <= sdRefreshCount + 1;
|
||||
|
||||
-- Auto refresh. On timeout it kicks in so that 8192 auto refreshes are
|
||||
-- issued in a 64ms period. Other bus operations are stalled during this period.
|
||||
if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then
|
||||
sdAutoRefresh <= '1';
|
||||
sdRefreshCount <= (others => '0');
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
sdMuxAddr(10) <= '1';
|
||||
sdActiveBank <= (others => '0');
|
||||
sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
|
||||
|
||||
-- In auto refresh period.
|
||||
elsif (sdAutoRefresh = '1') then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
when CYCLE_RFSH_START =>
|
||||
sdCmd <= CMD_AUTO_REFRESH;
|
||||
|
||||
when CYCLE_RFSH_END =>
|
||||
-- reset the count.
|
||||
sdAutoRefresh <= '0';
|
||||
sdCycle <= 0;
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif ((sbBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then
|
||||
|
||||
-- while the cycle is active count.
|
||||
sdCycle <= sdCycle + 1;
|
||||
case (sdCycle) is
|
||||
|
||||
when CYCLE_PRECHARGE =>
|
||||
-- If the bank is not open then no need to precharge, move onto RAS.
|
||||
if (sdActiveBank(sdBank) = '0') then
|
||||
sdCycle <= CYCLE_RAS_START;
|
||||
|
||||
-- If the requested row is already active, go to CAS for immediate access to this row.
|
||||
elsif (sdActiveRow(sdBank) = sdRow) then
|
||||
sdCycle <= CYCLE_CAS0;
|
||||
|
||||
-- Otherwise we close out the open bank by issuing a PRECHARGE.
|
||||
else
|
||||
sdCmd <= CMD_PRECHARGE;
|
||||
sdMuxAddr(10) <= '0';
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length));
|
||||
sdActiveBank(sdBank) <= '0'; -- Store flag to indicate which bank is being made active.
|
||||
end if;
|
||||
|
||||
-- Open the requested row.
|
||||
when CYCLE_RAS_START =>
|
||||
sdCmd <= CMD_ACTIVE;
|
||||
sdMuxAddr <= sdRow; -- Addr presented to SDRAM as row address.
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select.
|
||||
sdActiveRow(sdBank) <= sdRow; -- Store number of row being made active
|
||||
sdActiveBank(sdBank) <= '1'; -- Store flag to indicate which bank is being made active.
|
||||
|
||||
when CYCLE_RAS_NEXT =>
|
||||
sdDQM <= "11"; -- Set DQ to tri--state.
|
||||
|
||||
-- this is the first CAS cycle
|
||||
when CYCLE_CAS0 =>
|
||||
-- Process on a 32bit boundary, as this is a 16bit chip we need 2 accesses for a 32bit alignment.
|
||||
sdMuxAddr <= std_logic_vector(to_unsigned(to_integer(unsigned(sdCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
|
||||
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (sdIsWriting = '1') then
|
||||
sdCmd <= CMD_WRITE;
|
||||
sdDQM <= not cpuDQM(3 downto 2);
|
||||
sdDataOut <= cpuDataIn(31 downto 16); -- Assign corresponding data to the SDRAM databus.
|
||||
else
|
||||
-- Setup for a read.
|
||||
sdCmd <= CMD_READ;
|
||||
sdDQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
when CYCLE_CAS1 =>
|
||||
sdMuxAddr <= std_logic_vector(to_unsigned(to_integer(unsigned(sdCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge
|
||||
SDRAM_BA <= std_logic_vector(to_unsigned(sdBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
|
||||
|
||||
-- If writing, setup for a write with preset mask.
|
||||
if (sdIsWriting = '1') then
|
||||
sdCmd <= CMD_WRITE;
|
||||
sdDQM <= not cpuDQM(1 downto 0);
|
||||
sdDone <= not sdDone;
|
||||
sdDataOut <= cpuDataIn(15 downto 0);
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
-- Setup for a read, change to write if flag set.
|
||||
sdCmd <= CMD_READ;
|
||||
sdDQM <= "00"; -- For reads dont mask the data output.
|
||||
end if;
|
||||
|
||||
-- Data is available CAS Latency clocks after the read request.
|
||||
when CYCLE_READ0 =>
|
||||
-- If writing, then we are complete, exit else read the first word.
|
||||
if (sdIsWriting = '1') then
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
dout(31 downto 16) <= sdDataIn;
|
||||
end if;
|
||||
|
||||
when CYCLE_READ1 =>
|
||||
-- If writing, then we are complete, exit else read the first word.
|
||||
if (sdIsWriting = '1') then
|
||||
sdCycle <= CYCLE_END;
|
||||
else
|
||||
dout(15 downto 0) <= sdDataIn;
|
||||
sdDone <= not sdDone;
|
||||
end if;
|
||||
|
||||
when CYCLE_END =>
|
||||
|
||||
when others =>
|
||||
end case;
|
||||
else
|
||||
sdCycle <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent
|
||||
-- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know
|
||||
-- when the transation is complete and data read.
|
||||
--
|
||||
process(RESET, CLK, CS, WRITE_BYTE, WRITE_HWORD, ADDR, WREN, RDEN, isReady)
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
sdDoneLast <= '0';
|
||||
sbBusy <= '0';
|
||||
sdBank <= 0;
|
||||
sdRow <= (others => '0');
|
||||
sdCol <= (others => '0');
|
||||
cpuDQM <= (others => '1');
|
||||
sdIsWriting <= '0';
|
||||
|
||||
-- If the SDRAM isnt ready, we can only wait.
|
||||
elsif isReady = '0' then
|
||||
|
||||
elsif rising_edge(CLK) then
|
||||
|
||||
-- Detect a Chip Select state change signalling access.
|
||||
if CS = '1' and (WREN='1' or RDEN='1') then
|
||||
sbBusy <= '1';
|
||||
sdIsWriting <= WREN;
|
||||
sdBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS-1 downto SDRAM_ARRAY_BITS)));
|
||||
sdRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS + 1 - SDRAM_BANK_BITS downto SDRAM_COLUMN_BITS))), SDRAM_ROW_BITS));
|
||||
sdCol <= ADDR(SDRAM_COLUMN_BITS-1 downto 0);
|
||||
|
||||
-- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values.
|
||||
if(WRITE_BYTE = '1') then
|
||||
case ADDR(1 downto 0) is
|
||||
when "00" => cpuDQM <= "1000";
|
||||
cpuDataIn <= DATA_IN(7 downto 0) & X"000000";
|
||||
when "01" => cpuDQM <= "0100";
|
||||
cpuDataIn <= X"00" & DATA_IN(7 downto 0) & X"0000";
|
||||
when "10" => cpuDQM <= "0010";
|
||||
cpuDataIn <= X"0000" & DATA_IN(7 downto 0) & X"00";
|
||||
when "11" => cpuDQM <= "0001";
|
||||
cpuDataIn <= X"000000" & DATA_IN(7 downto 0);
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
elsif(WRITE_HWORD = '1') then
|
||||
|
||||
case ADDR(1) is
|
||||
when '0' => cpuDQM <= "1100";
|
||||
cpuDataIn <= DATA_IN(15 downto 0) & X"0000";
|
||||
when '1' => cpuDQM <= "0011";
|
||||
cpuDataIn <= X"0000" & DATA_IN(15 downto 0);
|
||||
end case;
|
||||
|
||||
else
|
||||
-- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit.
|
||||
cpuDataIn <= DATA_IN(31 downto 0);
|
||||
cpuDQM <= "1111";
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Note SDRAM activity via a previous/last signal.
|
||||
sdDoneLast <= sdDone;
|
||||
|
||||
-- If there has been a change in the SDRAM activity reset the signals as initiated transaction is complete.
|
||||
if (sdDone xor sdDoneLast) = '1' then
|
||||
sbBusy <= '0';
|
||||
sdIsWriting <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DATA_OUT <= dout;
|
||||
|
||||
-- drive control signals according to current command
|
||||
SDRAM_CS_n <= sdCmd(3);
|
||||
SDRAM_RAS_n <= sdCmd(2);
|
||||
SDRAM_CAS_n <= sdCmd(1);
|
||||
SDRAM_WE_n <= sdCmd(0);
|
||||
SDRAM_CKE <= sdCKE;
|
||||
SDRAM_DQM <= sdDQM;
|
||||
SDRAM_ADDR <= sdMuxAddr;
|
||||
|
||||
-- System bus control signals.
|
||||
BUSY <= sbBusy;
|
||||
SDRAM_READY <= isReady;
|
||||
|
||||
end Structure;
|
||||
@@ -1,728 +0,0 @@
|
||||
------------------------------------------------------
|
||||
-- FSM for a SDRAM controller
|
||||
--
|
||||
-- Version 0.1 - Ready to simulate
|
||||
--
|
||||
-- Authors: Mike Field (hamster@snap.net.nz)
|
||||
-- Alvaro Lopes (alvieboy@alvie.com)
|
||||
--
|
||||
-- Feel free to use it however you would like, but
|
||||
-- just drop us an email to say thanks.
|
||||
-------------------------------------------------------
|
||||
library ieee;
|
||||
library pkgs;
|
||||
library work;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.zpu_soc_pkg.all;
|
||||
use work.zpu_pkg.all;
|
||||
|
||||
entity sdram_controller is
|
||||
generic (
|
||||
HIGH_BIT: integer := 24;
|
||||
MHZ: integer := 96;
|
||||
REFRESH_CYCLES: integer := 4096;
|
||||
ADDRESS_BITS: integer := 12
|
||||
);
|
||||
PORT (
|
||||
clock_100: in std_logic;
|
||||
clock_100_delayed_3ns: in std_logic;
|
||||
rst: in std_logic;
|
||||
|
||||
-- Signals to/from the SDRAM chip
|
||||
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
|
||||
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
|
||||
DRAM_CAS_N : OUT STD_LOGIC;
|
||||
DRAM_CKE : OUT STD_LOGIC;
|
||||
DRAM_CLK : OUT STD_LOGIC;
|
||||
DRAM_CS_N : OUT STD_LOGIC;
|
||||
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
|
||||
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
|
||||
DRAM_RAS_N : OUT STD_LOGIC;
|
||||
DRAM_WE_N : OUT STD_LOGIC;
|
||||
|
||||
pending: out std_logic;
|
||||
|
||||
--- Inputs from rest of the system
|
||||
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
|
||||
req_read : IN STD_LOGIC;
|
||||
req_write : IN STD_LOGIC;
|
||||
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
|
||||
data_out_valid : OUT STD_LOGIC;
|
||||
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
|
||||
data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
||||
architecture rtl of sdram_controller is
|
||||
|
||||
type reg is record
|
||||
address : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
bank : std_logic_vector( 1 downto 0);
|
||||
init_counter : unsigned(14 downto 0);
|
||||
rf_counter : integer;
|
||||
rf_pending : std_logic;
|
||||
rd_pending : std_logic;
|
||||
wr_pending : std_logic;
|
||||
act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
act_ba : std_logic_vector(1 downto 0);
|
||||
data_out_low : std_logic_vector(15 downto 0);
|
||||
req_addr_q : std_logic_vector(HIGH_BIT downto 2);
|
||||
req_data_write: std_logic_vector(31 downto 0);
|
||||
req_mask : std_logic_vector(3 downto 0);
|
||||
data_out_valid: std_logic;
|
||||
dq_masks : std_logic_vector(1 downto 0);
|
||||
tristate : std_logic;
|
||||
end record;
|
||||
|
||||
signal r : reg;
|
||||
signal n : reg;
|
||||
|
||||
signal rstate : std_logic_vector(8 downto 0);
|
||||
signal nstate : std_logic_vector(8 downto 0);
|
||||
signal rdata_write : std_logic_vector(15 downto 0);
|
||||
signal ndata_write : std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
-- Vectors for each SDRAM 'command'
|
||||
--- CS_N, RAS_N, CAS_N, WE_N
|
||||
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
|
||||
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
|
||||
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
|
||||
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
|
||||
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
|
||||
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
|
||||
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
|
||||
|
||||
-- State assignments
|
||||
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
|
||||
|
||||
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
|
||||
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
|
||||
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
|
||||
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
|
||||
|
||||
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
|
||||
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
|
||||
|
||||
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
|
||||
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
|
||||
|
||||
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
|
||||
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
|
||||
|
||||
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
|
||||
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
|
||||
|
||||
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
|
||||
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
|
||||
|
||||
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
|
||||
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
|
||||
|
||||
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
|
||||
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
|
||||
|
||||
|
||||
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
|
||||
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
|
||||
|
||||
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
|
||||
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
|
||||
|
||||
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
|
||||
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
|
||||
|
||||
|
||||
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
|
||||
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
|
||||
|
||||
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
|
||||
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
|
||||
|
||||
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
|
||||
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
|
||||
|
||||
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
|
||||
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
|
||||
|
||||
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
|
||||
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
|
||||
|
||||
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
|
||||
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
|
||||
|
||||
|
||||
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
|
||||
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
|
||||
|
||||
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
|
||||
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
|
||||
|
||||
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
|
||||
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
|
||||
|
||||
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
|
||||
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
|
||||
|
||||
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
|
||||
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
|
||||
|
||||
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
|
||||
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
|
||||
|
||||
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
|
||||
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
|
||||
|
||||
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
|
||||
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
|
||||
|
||||
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
|
||||
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
|
||||
|
||||
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
|
||||
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
|
||||
|
||||
|
||||
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
|
||||
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
|
||||
|
||||
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
|
||||
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
|
||||
|
||||
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
|
||||
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
|
||||
|
||||
signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
signal addr_bank: std_logic_vector(1 downto 0);
|
||||
|
||||
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
|
||||
|
||||
|
||||
signal addr_col : std_logic_vector(7 downto 0);
|
||||
signal captured : std_logic_vector(15 downto 0);
|
||||
signal busy: std_logic;
|
||||
|
||||
constant tOPD: time := 1.4 ns;
|
||||
constant tHZ: time := 8 ns;
|
||||
|
||||
signal dram_dq_dly : std_logic_vector(15 downto 0);
|
||||
|
||||
-- Debug only
|
||||
signal debug_cmd: std_logic_vector(3 downto 0);
|
||||
|
||||
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
|
||||
|
||||
attribute IOB: string;
|
||||
|
||||
signal i_DRAM_CS_N: std_logic;
|
||||
attribute IOB of i_DRAM_CS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_RAS_N: std_logic;
|
||||
attribute IOB of i_DRAM_RAS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_CAS_N: std_logic;
|
||||
attribute IOB of i_DRAM_CAS_N: signal is "true";
|
||||
|
||||
signal i_DRAM_WE_N: std_logic;
|
||||
attribute IOB of i_DRAM_WE_N: signal is "true";
|
||||
|
||||
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
|
||||
attribute IOB of i_DRAM_ADDR: signal is "true";
|
||||
|
||||
signal i_DRAM_BA: std_logic_vector(1 downto 0);
|
||||
attribute IOB of i_DRAM_BA: signal is "true";
|
||||
|
||||
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
|
||||
attribute IOB of i_DRAM_DQM: signal is "true";
|
||||
|
||||
attribute IOB of rdata_write: signal is "true";
|
||||
attribute IOB of captured: signal is "true";
|
||||
|
||||
signal i_DRAM_CLK: std_logic;
|
||||
|
||||
attribute fsm_encoding: string;
|
||||
attribute fsm_encoding of nstate: signal is "user";
|
||||
attribute fsm_encoding of rstate: signal is "user";
|
||||
|
||||
begin
|
||||
|
||||
debug_cmd <= rstate(3 downto 0);
|
||||
|
||||
-- Addressing is in 32 bit words - twice that of the DRAM width,
|
||||
-- so each burst of four access two system words.
|
||||
--addr_row <= address(23 downto 11);
|
||||
--addr_bank <= address(10 downto 9);
|
||||
process(r.req_addr_q)
|
||||
begin
|
||||
addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
|
||||
-- (24-2) downto (24-2 - 2 - 13 - 1)
|
||||
-- 22 downto 6
|
||||
addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
|
||||
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
|
||||
addr_col <= (others => '0');
|
||||
|
||||
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
|
||||
r.req_addr_q(8 downto 2) & "0";
|
||||
end process;
|
||||
|
||||
clock: entity work.oddrff
|
||||
port map (
|
||||
D0 => '0',
|
||||
D1 => '1',
|
||||
O => i_DRAM_CLK,
|
||||
CLK => clock_100
|
||||
);
|
||||
|
||||
DRAM_CKE <= '1';
|
||||
|
||||
DRAM_CLK <= clock_100; -- transport i_DRAM_CLK after tOPD;
|
||||
|
||||
i_DRAM_CS_N <= transport rstate(3) after tOPD;
|
||||
DRAM_CS_N <= i_DRAM_CS_N;
|
||||
|
||||
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
|
||||
DRAM_RAS_N <= i_DRAM_RAS_N;
|
||||
|
||||
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
|
||||
DRAM_CAS_N <= i_DRAM_CAS_N;
|
||||
|
||||
i_DRAM_WE_N <= transport rstate(0) after tOPD;
|
||||
DRAM_WE_N <= i_DRAM_WE_N;
|
||||
|
||||
i_DRAM_ADDR <= transport r.address after tOPD;
|
||||
DRAM_ADDR <= i_DRAM_ADDR;
|
||||
|
||||
i_DRAM_BA <= transport r.bank after tOPD;
|
||||
DRAM_BA <= i_DRAM_BA;
|
||||
|
||||
i_DRAM_DQM <= transport r.dq_masks after tOPD;
|
||||
DRAM_DQM <= i_DRAM_DQM;
|
||||
|
||||
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
|
||||
data_out_valid <= r.data_out_valid;
|
||||
|
||||
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
|
||||
|
||||
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
|
||||
|
||||
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
|
||||
begin
|
||||
-- copy the existing values
|
||||
n <= r;
|
||||
nstate <= rstate;
|
||||
ndata_write <= rdata_write;
|
||||
|
||||
if req_read = '1' then
|
||||
n.rd_pending <= '1';
|
||||
if r.rd_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if req_write = '1' then
|
||||
n.wr_pending <= '1';
|
||||
if r.wr_pending='0' then
|
||||
n.req_addr_q <= address;
|
||||
-- Queue data here
|
||||
n.req_data_write <= data_in;
|
||||
n.req_mask <= data_mask;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
n.dq_masks <= "11";
|
||||
|
||||
-- first off, do we need to perform a refresh cycle ASAP?
|
||||
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
|
||||
n.rf_counter <= 0;
|
||||
n.rf_pending <= '1';
|
||||
else
|
||||
-- only start looking for refreshes outside of the initialisation state.
|
||||
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
|
||||
n.rf_counter <= r.rf_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Set the data bus into HIZ, high and low bytes masked
|
||||
--DRAM_DQ <= (others => 'Z');
|
||||
n.tristate <= '0';
|
||||
|
||||
n.init_counter <= r.init_counter - 1;
|
||||
|
||||
--ndata_write <= (others => DontCareValue);
|
||||
|
||||
n.data_out_valid <= '0'; -- alvie- here, no ?
|
||||
|
||||
-- Process the FSM
|
||||
case rstate(8 downto 4) is
|
||||
when s_init_nop_id => --s_init_nop(8 downto 4) =>
|
||||
nstate <= s_init_nop;
|
||||
n.address <= (others => '0');
|
||||
n.bank <= (others => '0');
|
||||
n.act_ba <= (others => '0');
|
||||
n.rf_counter <= 0;
|
||||
-- n.data_out_valid <= '1'; -- alvie- not here
|
||||
|
||||
-- T-130, precharge all banks.
|
||||
if r.init_counter = "000000010000010" then
|
||||
nstate <= s_init_pre;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
|
||||
|
||||
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
|
||||
nstate <= s_init_ref;
|
||||
end if;
|
||||
|
||||
-- T-3, the load mode register
|
||||
if r.init_counter = 3 then
|
||||
nstate <= s_init_mrs;
|
||||
-- Mode register is as follows:
|
||||
-- resvd wr_b OpMd CAS=3 Seq bust=1
|
||||
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
|
||||
-- resvd
|
||||
n.bank <= "00";
|
||||
end if;
|
||||
|
||||
-- T-1 The switch to the FSM (first command will be a NOP
|
||||
if r.init_counter = 1 then
|
||||
nstate <= s_idle;
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Idle section
|
||||
------------------------------
|
||||
when s_idle_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
-- do we have to activate a row?
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
-- refreshes take priority over everything
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
n.rf_pending <= '0';
|
||||
end if;
|
||||
------------------------------
|
||||
-- Row activation
|
||||
-- s_ra2 is also the "idle with active row" state and provides
|
||||
-- a resting point between operations on the same row
|
||||
------------------------------
|
||||
when s_ra0_id =>
|
||||
nstate <= s_ra1;
|
||||
when s_ra1_id =>
|
||||
nstate <= s_ra2;
|
||||
|
||||
|
||||
when s_ra2_id=>
|
||||
-- we can stay in this state until we have something to do
|
||||
nstate <= s_ra2;
|
||||
n.tristate<='0';
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
else
|
||||
|
||||
-- If there is a read pending, deactivate the row
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
-- unless we have a read to perform on the same row? do that instead
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_rd0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks <= "00";
|
||||
n.rd_pending <= '0';
|
||||
--n.tristate<='1';
|
||||
end if;
|
||||
|
||||
-- unless we have a write on the same row? writes take priroty over reads
|
||||
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
|
||||
nstate <= s_wr0;
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
ndata_write <= r.req_data_write(31 downto 16);
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= not r.req_mask(3 downto 2);
|
||||
n.wr_pending <= '0';
|
||||
--n.tristate <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
end if;
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending;
|
||||
-- n.wr_pending <= r.wr_pending;
|
||||
--n.tristate <= '0';
|
||||
--end if;
|
||||
|
||||
------------------------------------------------------
|
||||
-- Deactivate the current row and return to idle state
|
||||
------------------------------------------------------
|
||||
when s_dr0_id =>
|
||||
nstate <= s_dr1;
|
||||
when s_dr1_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
------------------------------
|
||||
-- The Refresh section
|
||||
------------------------------
|
||||
when s_rf0_id =>
|
||||
nstate <= s_rf1;
|
||||
when s_rf1_id =>
|
||||
nstate <= s_rf2;
|
||||
when s_rf2_id =>
|
||||
nstate <= s_rf3;
|
||||
when s_rf3_id =>
|
||||
nstate <= s_rf4;
|
||||
when s_rf4_id =>
|
||||
nstate <= s_rf5;
|
||||
when s_rf5_id =>
|
||||
nstate <= s_idle;
|
||||
------------------------------
|
||||
-- The Write section
|
||||
------------------------------
|
||||
when s_wr0_id =>
|
||||
nstate <= s_wr3;
|
||||
n.bank <= addr_bank;
|
||||
n.address(0) <= '1';
|
||||
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.dq_masks<= not r.req_mask(1 downto 0);
|
||||
n.tristate <= '0';
|
||||
|
||||
when s_wr1_id => null;
|
||||
when s_wr2_id =>
|
||||
nstate <= s_dr0;
|
||||
n.address(10) <= '1';
|
||||
|
||||
|
||||
when s_wr3_id =>
|
||||
-- Default to the idle+row active state
|
||||
nstate <= s_ra2;
|
||||
--DRAM_DQ <= rdata_write;
|
||||
n.data_out_valid<='1'; -- alvie- ack write
|
||||
n.tristate <= '0';
|
||||
n.dq_masks<= "11";
|
||||
|
||||
-- If there is a read or write then deactivate the row
|
||||
--if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
-- nstate <= s_dr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
-- But if there is a read pending in the same row, do that
|
||||
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_rd0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
-- --n.act_ba <= addr_bank;
|
||||
-- n.dq_masks <= "00";
|
||||
-- n.rd_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- unless there is a write pending in the same row, do that
|
||||
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
|
||||
-- nstate <= s_wr0;
|
||||
-- n.address <= (others => '0');
|
||||
-- n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
-- n.bank <= addr_bank;
|
||||
--n.act_ba <= addr_bank;
|
||||
-- n.dq_masks<= "00";
|
||||
-- n.wr_pending <= '0';
|
||||
--end if;
|
||||
|
||||
-- But always try and refresh if one is pending!
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_wr2; --dr0;
|
||||
--n.address(10) <= '1';
|
||||
end if;
|
||||
|
||||
------------------------------
|
||||
-- The Read section
|
||||
------------------------------
|
||||
when s_rd0_id => -- 10001
|
||||
nstate <= s_rd1;
|
||||
n.tristate<='1';
|
||||
n.dq_masks <= "00";
|
||||
n.address(0)<='1';
|
||||
|
||||
when s_rd1_id => -- 10010
|
||||
nstate <= s_rd2;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
|
||||
nstate <= s_rd3; -- Another request came, and we can pipeline -
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
end if;
|
||||
|
||||
when s_rd2_id => -- 10011
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
when s_rd3_id => -- 10100
|
||||
|
||||
nstate <= s_rd4;
|
||||
n.dq_masks <= "00";
|
||||
n.address(0) <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
|
||||
-- Data is still not ready...
|
||||
|
||||
when s_rd4_id => -- 10101
|
||||
nstate <= s_rd5;
|
||||
n.dq_masks <= "00";
|
||||
--n.address(0)<='1';
|
||||
n.tristate<='1';
|
||||
|
||||
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
|
||||
nstate <= s_rd5; -- Another request came, and we can pipeline -
|
||||
|
||||
n.address <= (others => '0');
|
||||
n.address(addr_col'HIGH downto 0) <= addr_col;
|
||||
n.bank <= addr_bank;
|
||||
n.act_ba <= addr_bank;
|
||||
n.dq_masks<= "00";
|
||||
n.rd_pending <= '0';
|
||||
|
||||
else
|
||||
nstate <= s_rd6; -- NOTE: not correct
|
||||
end if;
|
||||
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
-- n.rd_pending <= r.rd_pending; -- Keep request
|
||||
--end if;
|
||||
|
||||
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
|
||||
|
||||
when s_rd5_id =>
|
||||
-- If a refresh is pending then always deactivate the row
|
||||
--if r.rf_pending = '1' then
|
||||
-- nstate <= s_drdr0;
|
||||
-- n.address(10) <= '1';
|
||||
--end if;
|
||||
|
||||
n.address(0) <= '1';
|
||||
nstate <= s_rd4; -- Another request came, and we can pipeline -
|
||||
n.dq_masks <= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd6_id =>
|
||||
nstate <= s_rd7;
|
||||
n.dq_masks<= "00";
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd7_id =>
|
||||
nstate <= s_ra2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
n.tristate<='1';
|
||||
|
||||
when s_rd8_id => null;
|
||||
|
||||
when s_rd9_id => null;
|
||||
|
||||
-- The Deactivate row during read section
|
||||
------------------------------
|
||||
when s_drdr0_id =>
|
||||
nstate <= s_drdr1;
|
||||
when s_drdr1_id =>
|
||||
nstate <= s_drdr2;
|
||||
n.data_out_low <= captured;
|
||||
n.data_out_valid <= '1';
|
||||
when s_drdr2_id =>
|
||||
nstate <= s_idle;
|
||||
|
||||
if r.rf_pending = '1' then
|
||||
nstate <= s_rf0;
|
||||
end if;
|
||||
|
||||
if r.rd_pending = '1' or r.wr_pending = '1' then
|
||||
nstate <= s_ra0;
|
||||
n.address <= addr_row;
|
||||
n.act_row <= addr_row;
|
||||
n.bank <= addr_bank;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
nstate <= s_init_nop;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
--- The clock driven logic
|
||||
process (clock_100, n)
|
||||
begin
|
||||
if clock_100'event and clock_100 = '1' then
|
||||
if rst='1' then
|
||||
rstate <= (others => '0');
|
||||
r.address <= (others => '0');
|
||||
r.bank <= (others => '0');
|
||||
r.init_counter <= "100000000000000";
|
||||
-- synopsys translate_off
|
||||
r.init_counter <= "000000100000000";
|
||||
-- synopsys translate_on
|
||||
r.rf_counter <= 0;
|
||||
r.rf_pending <= '0';
|
||||
r.rd_pending <= '0';
|
||||
r.wr_pending <= '0';
|
||||
r.act_row <= (others => '0');
|
||||
r.data_out_low <= (others => '0');
|
||||
r.data_out_valid <= '0';
|
||||
r.dq_masks <= "11";
|
||||
r.tristate<='1';
|
||||
else
|
||||
r <= n;
|
||||
rstate <= nstate;
|
||||
rdata_write <= ndata_write;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dram_dq_dly <= transport dram_dq after 3.6 ns;--1.9 ns;
|
||||
|
||||
-- process (clock_100_delayed_3ns, dram_dq_dly)
|
||||
-- begin
|
||||
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
|
||||
-- captured <= dram_dq_dly;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process (clock_100_delayed_3ns)
|
||||
begin
|
||||
if falling_edge(clock_100_delayed_3ns) then
|
||||
captured <= dram_dq_dly;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
Reference in New Issue
Block a user