Initial commit
This commit is contained in:
Philip Smart
4
common/submodules/pll_pll_0.qip
Normal file
4
common/submodules/pll_pll_0.qip
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@@ -0,0 +1,4 @@
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set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_0*|altera_pll:altera_pll_i*|*"
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108
common/submodules/pll_pll_0.v
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108
common/submodules/pll_pll_0.v
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@@ -0,0 +1,108 @@
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`timescale 1ns/10ps
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module pll_pll_0(
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// interface 'refclk'
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input wire refclk,
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// interface 'reset'
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input wire rst,
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// interface 'outclk0'
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output wire outclk_0,
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// interface 'outclk1'
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output wire outclk_1,
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// interface 'outclk2'
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output wire outclk_2,
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// interface 'outclk3'
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output wire outclk_3,
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// interface 'outclk4'
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output wire outclk_4,
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// interface 'outclk5'
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output wire outclk_5,
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// interface 'outclk6'
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output wire outclk_6,
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// interface 'outclk7'
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output wire outclk_7,
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// interface 'locked'
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output wire locked
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);
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altera_pll #(
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.fractional_vco_multiplier("true"),
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.reference_clock_frequency("50.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(8),
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.output_clock_frequency0("255.999872 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("109.714257 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("63.999981 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("31.999989 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("15.999994 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("7.999996 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("3.999998 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("1.999999 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_7, outclk_6, outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
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.locked (locked),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (refclk)
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);
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endmodule
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4
common/submodules/pll_pll_1.qip
Normal file
4
common/submodules/pll_pll_1.qip
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@@ -0,0 +1,4 @@
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set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_1*|altera_pll:altera_pll_i*|*"
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99
common/submodules/pll_pll_1.v
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99
common/submodules/pll_pll_1.v
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@@ -0,0 +1,99 @@
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`timescale 1ns/10ps
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module pll_pll_1(
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// interface 'refclk'
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input wire refclk,
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// interface 'reset'
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input wire rst,
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// interface 'outclk0'
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output wire outclk_0,
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// interface 'outclk1'
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output wire outclk_1,
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// interface 'outclk2'
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output wire outclk_2,
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// interface 'outclk3'
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output wire outclk_3,
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// interface 'outclk4'
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output wire outclk_4,
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// interface 'locked'
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output wire locked
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);
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altera_pll #(
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.fractional_vco_multiplier("false"),
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.reference_clock_frequency("256.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(5),
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.output_clock_frequency0("56.748768 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("28.374384 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("14.187192 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("7.093596 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("3.546798 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
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.locked (locked),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (refclk)
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);
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endmodule
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4
common/submodules/pll_pll_2.qip
Normal file
4
common/submodules/pll_pll_2.qip
Normal file
@@ -0,0 +1,4 @@
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set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
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set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pll_2*|altera_pll:altera_pll_i*|*"
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96
common/submodules/pll_pll_2.v
Normal file
96
common/submodules/pll_pll_2.v
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@@ -0,0 +1,96 @@
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`timescale 1ns/10ps
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module pll_pll_2(
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// interface 'refclk'
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input wire refclk,
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// interface 'reset'
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input wire rst,
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// interface 'outclk0'
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output wire outclk_0,
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// interface 'outclk1'
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output wire outclk_1,
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// interface 'outclk2'
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output wire outclk_2,
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// interface 'outclk3'
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output wire outclk_3,
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// interface 'locked'
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output wire locked
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);
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altera_pll #(
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.fractional_vco_multiplier("true"),
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.reference_clock_frequency("256.0 MHz"),
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.operation_mode("normal"),
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.number_of_clocks(4),
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.output_clock_frequency0("31.099998 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("25.176188 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("17.821346 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("8.860892 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
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.locked (locked),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (refclk)
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);
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endmodule
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