14 Commits

Author	SHA1	Message	Date
Robert Peip	09fcf84765	Instruction Fetch path improved: ... - bypass prefetch fifo - don't request TLB if not required - stop cache burst when jump happened	2020-08-04 20:08:12 +02:00
Robert Peip	7431d4b433	fixed shared memory	2020-08-01 14:32:01 +02:00
Robert Peip	aa65f9e698	bypass aligned reads directly into CPU	2020-08-01 12:02:30 +02:00
Robert Peip	087914ebb6	L2 Cache: 2 times size, LRU exchange stategy, reduced dirtyflag ressource usage	2020-07-31 21:38:19 +02:00
Robert Peip	9015e2cf31	L1 Cache: 4 times size, LRU exchange stategy, reduced dirtyflag ressource usage	2020-07-28 18:58:55 +02:00
Robert Peip	0ee2f22b7d	trim unused upper 32bit from prefetch fifo and cleanup, prevent RRB in Caches to use BRAM	2020-07-26 07:54:24 +02:00
Robert Peip	8ea1579330	revert 64bit prefetch because of regression	2020-07-25 09:56:52 +02:00
sorgelig	8e5d8be9d3	vga: impement SVGA 8/16/24 bit modes.	2020-07-25 09:21:42 +08:00
sorgelig	8cd34b3aba	l2_cache: fix region unlocking.	2020-07-25 07:03:35 +08:00
Robert Peip	c9c2944484	timing improvements	2020-07-24 09:21:11 +02:00
Robert Peip	c5457d13db	use 64bit instead of 32bit for prefetch to decode pipeline	2020-07-24 08:12:54 +02:00
sorgelig	83c530748d	256MB RAM.	2020-07-19 04:36:18 +08:00
sorgelig	e2536bed98	Tweak to make single memory size parameter.	2020-07-19 00:44:38 +08:00
sorgelig	4f43f7edce	cache: convert to verilog, some optimizations.	2020-07-18 10:31:54 +08:00