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Update sys.

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sorgelig
2021-02-16 21:24:14 +08:00
parent 1ae19f0701
commit 8ee9a1bbe0
5 changed files with 104 additions and 16 deletions
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4
sys/ascal.vhd
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@@ -429,7 +429,7 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic;
SIGNAL o_copyv : unsigned(0 TO 8);
SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address
SIGNAL o_adrs_pre : natural RANGE 0 TO 2**23-1;
SIGNAL o_adrs_pre : natural RANGE 0 TO 2**24-1;
SIGNAL o_stride : unsigned(13 DOWNTO 0);
SIGNAL o_adrsa,o_adrsb,o_rline : std_logic;
SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1;
@@ -1519,7 +1519,7 @@ BEGIN
avl_read_sync<=o_read; -- <ASYNC>
avl_read_sync2<=avl_read_sync;
avl_read_pulse<=avl_read_sync XOR avl_read_sync2;
avl_radrs <=o_adrs AND (RAMSIZE - 1); -- <ASYNC>
avl_radrs <=o_adrs; -- <ASYNC>
avl_rline <=o_rline; -- <ASYNC>
--------------------------------------------

1
sys/sys.qip
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@@ -9,6 +9,7 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_crop.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]

2
sys/sys_top.sdc
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@@ -32,7 +32,7 @@ set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {width[*] height[*]}
set_false_path -to {hdmi_width[*] hdmi_height[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1

34
sys/sys_top.v
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@@ -430,6 +430,7 @@ always@(posedge clk_sys) begin
6: LFB_HMAX <= io_din[11:0];
7: LFB_VMIN <= io_din[11:0];
8: LFB_VMAX <= io_din[11:0];
9: LFB_STRIDE <= io_din[13:0];
endcase
end
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
@@ -747,6 +748,7 @@ reg [11:0] LFB_HMAX = 0;
reg [11:0] LFB_VMIN = 0;
reg [11:0] LFB_VMAX = 0;
reg [31:0] LFB_BASE = 0;
reg [13:0] LFB_STRIDE = 0;
reg FB_EN = 0;
reg [5:0] FB_FMT = 0;
@@ -762,7 +764,7 @@ always @(posedge clk_sys) begin
FB_WIDTH <= LFB_WIDTH;
FB_HEIGHT <= LFB_HEIGHT;
FB_BASE <= LFB_BASE;
FB_STRIDE <= 0;
FB_STRIDE <= LFB_STRIDE;
end
else begin
FB_FMT <= fb_fmt;
@@ -782,6 +784,8 @@ reg [11:0] hmin;
reg [11:0] hmax;
reg [11:0] vmin;
reg [11:0] vmax;
reg [11:0] hdmi_height;
reg [11:0] hdmi_width;
always @(posedge clk_vid) begin
reg [31:0] wcalc;
@@ -789,14 +793,12 @@ always @(posedge clk_vid) begin
reg [2:0] state;
reg [11:0] videow;
reg [11:0] videoh;
reg [11:0] height;
reg [11:0] width;
reg [11:0] arx;
reg [11:0] ary;
height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
hdmi_height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
hdmi_width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
if(!ARY) begin
if(ARX == 1) begin
arx <= arc1x;
@@ -826,17 +828,17 @@ always @(posedge clk_vid) begin
state<= 0;
end
else if(FREESCALE || !arx || !ary) begin
wcalc <= width;
hcalc <= height;
wcalc <= hdmi_width;
hcalc <= hdmi_height;
end
else begin
wcalc <= (height*arx)/ary;
hcalc <= (width*ary)/arx;
wcalc <= (hdmi_height*arx)/ary;
hcalc <= (hdmi_width*ary)/arx;
end
6: begin
videow <= (wcalc > width) ? width : wcalc[11:0];
videoh <= (hcalc > height) ? height : hcalc[11:0];
videow <= (wcalc > hdmi_width) ? hdmi_width : wcalc[11:0];
videoh <= (hcalc > hdmi_height) ? hdmi_height : hcalc[11:0];
end
7: begin
@@ -1483,7 +1485,10 @@ emu emu
(
.CLK_50M(FPGA_CLK2_50),
.RESET(reset),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_ihdmi, ce_hpix, hde_emu, hhs_fix, hvs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.HPS_BUS({f1, HDMI_TX_VS,
clk_100m, clk_ihdmi,
ce_hpix, hde_emu, hhs_fix, hvs_fix,
io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.VGA_R(r_out),
.VGA_G(g_out),
@@ -1494,6 +1499,9 @@ emu emu
.VGA_F1(f1),
.VGA_SCALER(vga_force_scaler),
.HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width),
.HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.VGA_SL(scanlines),

79
sys/video_crop.sv Normal file
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@@ -0,0 +1,79 @@
//
//
// Copyright (c) 2020 Grabulosaure
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
// Modified version to display specific vertical size. // Sorgelig
module video_crop
(
input CLK_VIDEO,
input CE_PIXEL,
input VGA_VS,
input VGA_DE_IN,
input [11:0] ARX,
input [11:0] ARY,
input [9:0] CROP_SIZE,
input [4:0] CROP_OFF,
output VGA_DE,
output reg [11:0] VIDEO_ARX,
output reg [11:0] VIDEO_ARY
);
reg vde;
always @(posedge CLK_VIDEO) begin
reg old_de, old_vs,vcalc;
reg [9:0] vcpt,vsize,vcrop,voff;
reg [11:0] vadj;
reg [21:0] ARXI,ARYI,ARXG,ARYG,arx,ary;
if (CE_PIXEL) begin
old_de <= VGA_DE_IN;
old_vs <= VGA_VS;
if (VGA_VS & ~old_vs) begin
vcpt <= 0;
vsize <= vcpt;
vcalc <= 1;
vcrop <= ((CROP_SIZE >= vcpt) || !CROP_SIZE) ? 10'd0 : CROP_SIZE;
end
if (~VGA_DE_IN & old_de) vcpt <= vcpt + 1'd1;
end
arx <= ARX;
ary <= ARY;
if(!vcrop || !ary) begin
VIDEO_ARX <= arx[11:0];
VIDEO_ARY <= ary[11:0];
end
else if (vcalc) begin
ARXG <= arx * vsize;
ARYG <= ary * vcrop;
vcalc <= 0;
end
else if (ARXG[21] | ARYG[21]) begin
VIDEO_ARX <= ARXG[21:10];
VIDEO_ARY <= ARYG[21:10];
end
else begin
ARXG <= ARXG << 1;
ARYG <= ARYG << 1;
end
vadj <= {2'b0,vsize-vcrop} + {{6{CROP_OFF[4]}},CROP_OFF,1'b0};
voff <= vadj[11] ? 10'd0 : ((vadj[11:1] + vcrop) > vsize) ? vsize-vcrop : vadj[10:1];
vde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;
end
assign VGA_DE = vde & VGA_DE_IN;
endmodule