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Update sys. New scaler.

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This commit is contained in:
sorgelig
2018-12-27 18:21:19 +08:00
parent 9f98d49125
commit 577dbea6a1
31 changed files with 3476 additions and 1081 deletions
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3
zxspectrum.qpf → ZX-Spectrum-vip.qpf
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@@ -9,5 +9,4 @@ DATE = "23:13:02 April 27, 2017"
# Revisions
PROJECT_REVISION = "zxspectrum"
PROJECT_REVISION = "zxspectrum-lite"
PROJECT_REVISION = "ZX-Spectrum-vip"

0
zxspectrum.qsf → ZX-Spectrum-vip.qsf
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0
zxspectrum.srf → ZX-Spectrum-vip.srf
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12
ZX-Spectrum.qpf Normal file
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@@ -0,0 +1,12 @@
#
# please keep this file read-only!
# Quartus changes this file everytime revision is switched,
# and it will be marked as changed with every commit.
#
QUARTUS_VERSION = "16.1"
DATE = "23:13:02 April 27, 2017"
# Revisions
PROJECT_REVISION = "ZX-Spectrum"

17
zxspectrum-lite.qsf → ZX-Spectrum.qsf
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@@ -30,7 +30,7 @@ set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
@@ -358,7 +358,7 @@ set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QIP_FILE t80/T80.qip
set_global_assignment -name QIP_FILE jt12/jt12.qip
set_global_assignment -name SDC_FILE zxspectrum.sdc
set_global_assignment -name SDC_FILE ZX-Spectrum.sdc
set_global_assignment -name SYSTEMVERILOG_FILE saa1099.sv
set_global_assignment -name SYSTEMVERILOG_FILE turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE ym2149.sv
@@ -375,5 +375,16 @@ set_global_assignment -name VERILOG_FILE dpram.v
set_global_assignment -name SYSTEMVERILOG_FILE tape.sv
set_global_assignment -name VERILOG_FILE mouse.v
set_global_assignment -name SYSTEMVERILOG_FILE keyboard.sv
set_global_assignment -name SYSTEMVERILOG_FILE zxspectrum.sv
set_global_assignment -name SYSTEMVERILOG_FILE ZX-Spectrum.sv
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
zxspectrum.sdc → ZX-Spectrum.sdc
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0
zxspectrum-lite.srf → ZX-Spectrum.srf
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69
zxspectrum.sv → ZX-Spectrum.sv
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@@ -47,6 +47,8 @@ module emu
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output LED_USER, // 1 - ON, 0 - OFF.
@@ -93,9 +95,18 @@ module emu
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR
);
assign VGA_F1 = 0;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign AUDIO_S = 1;
@@ -146,16 +157,14 @@ localparam CONF_STR1 = {
localparam CONF_STR2 = {
"0,Reset & apply;",
"J,Fire 1,Fire 2;",
"V,v3.91.",`BUILD_DATE
"V,v",`BUILD_DATE
};
//////////////////// CLOCKS ///////////////////
assign CLK_VIDEO = clk_sys;
wire locked;
wire clk_sys;
wire clk_sys, clk_vid;
pll pll
(
@@ -163,6 +172,7 @@ pll pll
.rst(0),
.outclk_0(clk_sys),
.outclk_1(SDRAM_CLK),
.outclk_2(clk_vid),
.locked(locked)
);
@@ -753,7 +763,54 @@ always_comb begin
endcase
end
video video(.*, .ce_pix(CE_PIXEL), .din(cpu_dout), .page_ram(page_ram[2:0]), .scale(status[16:15]), .wide(status[5]));
wire [1:0] scale = status[16:15];
assign VGA_SL = {scale == 3, scale == 2};
video video
(
.*,
.ce_pix(ce_vid1),
.VGA_R(r2),
.VGA_G(g2),
.VGA_B(b2),
.VGA_HS(hs2),
.VGA_VS(vs2),
.VGA_DE(de2),
.din(cpu_dout),
.page_ram(page_ram[2:0]),
.scale(scale == 1),
.forced_scandoubler(forced_scandoubler || scale),
.wide(status[5])
);
wire ce_vid1;
reg ce_vid2;
always @(posedge clk_sys) ce_vid2 <= ce_vid1;
wire ce_vid = ce_vid2 | ce_vid1;
reg ce_pix, ce_pix1;
reg [7:0] r,r1,r2,g,g1,g2,b,b1,b2;
reg hs,hs1,hs2,vs,vs1,vs2,de,de1,de2;
always @(posedge clk_vid) begin
ce_pix1 <= ce_vid;
ce_pix <= ce_pix1;
{r1,g1,b1} <= {r2,g2,b2};
{r,g,b} <= {r1,g1,b1};
{hs1,vs1,de1} <= {hs2,vs2,de2};
{hs,vs,de} <= {hs1,vs1,de1};
end
assign {VGA_R,VGA_G,VGA_B} = {r,g,b};
assign {VGA_HS,VGA_VS,VGA_DE} = {hs,vs,de};
assign CE_PIXEL = ce_pix;
assign CLK_VIDEO = clk_vid;
reg new_vmode = 0;
always @(posedge clk_sys) begin

2
zxspectrum_Q13.qpf → ZX-Spectrum_Q13.qpf
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@@ -9,4 +9,4 @@ DATE = "23:13:02 April 27, 2017"
# Revisions
PROJECT_REVISION = "zxspectrum_Q13"
PROJECT_REVISION = "ZX-Spectrum_Q13"

4
zxspectrum_Q13.qsf → ZX-Spectrum_Q13.qsf
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@@ -361,7 +361,7 @@ set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys_q13.qip
set_global_assignment -name QIP_FILE t80/T80.qip
set_global_assignment -name QIP_FILE jt12/jt12.qip
set_global_assignment -name SDC_FILE zxspectrum.sdc
set_global_assignment -name SDC_FILE ZX-Spectrum.sdc
set_global_assignment -name SYSTEMVERILOG_FILE saa1099.sv
set_global_assignment -name SYSTEMVERILOG_FILE turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE ym2149.sv
@@ -378,5 +378,5 @@ set_global_assignment -name VERILOG_FILE dpram.v
set_global_assignment -name SYSTEMVERILOG_FILE tape.sv
set_global_assignment -name VERILOG_FILE mouse.v
set_global_assignment -name SYSTEMVERILOG_FILE keyboard.sv
set_global_assignment -name SYSTEMVERILOG_FILE zxspectrum.sv
set_global_assignment -name SYSTEMVERILOG_FILE ZX-Spectrum.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
zxspectrum_Q13.srf → ZX-Spectrum_Q13.srf
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@@ -19,7 +19,9 @@
{ "" "" "" "Design contains 4 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "24 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Following 5 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { } { } 0 169064 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

2505
sys/ascal.vhd Normal file
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File diff suppressed because it is too large Load Diff

71
sys/coeff.mif Normal file
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@@ -0,0 +1,71 @@
DEPTH = 256;
WIDTH = 9;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
000: 1E8 0B0 1E8 000;
004: 1EC 0AE 1E6 000;
008: 1F0 0A9 1E6 001;
00C: 1F5 0A0 1E9 002;
010: 1FA 093 1F0 003;
014: 1FF 081 1FC 004;
018: 002 06D 00B 006;
01C: 005 054 020 007;
020: 006 03A 03A 006;
024: 006 016 060 004;
028: 005 003 077 001;
02C: 004 1F4 08C 1FC;
030: 002 1EC 09A 1F8;
034: 001 1E7 0A5 1F3;
038: 000 1E6 0AC 1EE;
03C: 000 1E7 0AF 1EA;
040: 000 080 000 000;
044: 1FC 07E 006 000;
048: 1F8 07C 00D 1FF;
04C: 1F6 077 014 1FF;
050: 1F5 06F 01E 1FE;
054: 1F5 067 028 1FC;
058: 1F6 05D 032 1FB;
05C: 1F7 052 03D 1FA;
060: 1F8 048 048 1F8;
064: 1FA 038 058 1F6;
068: 1FC 02D 062 1F5;
06C: 1FD 023 06B 1F5;
070: 1FE 019 073 1F6;
074: 1FF 011 079 1F7;
078: 000 009 07D 1FA;
07C: 000 003 07F 1FE;
080: 000 080 000 000;
084: 000 080 000 000;
088: 000 080 000 000;
08C: 000 080 000 000;
090: 000 080 000 000;
094: 000 080 000 000;
098: 000 080 000 000;
09C: 000 080 000 000;
0A0: 000 080 000 000;
0A4: 000 080 000 000;
0A8: 000 080 000 000;
0AC: 000 080 000 000;
0B0: 000 080 000 000;
0B4: 000 080 000 000;
0B8: 000 080 000 000;
0BC: 000 080 000 000;
0C0: 000 080 000 000;
0C4: 000 080 000 000;
0C8: 000 080 000 000;
0CC: 000 080 000 000;
0D0: 000 080 000 000;
0D4: 000 080 000 000;
0D8: 000 080 000 000;
0DC: 000 080 000 000;
0E0: 000 080 000 000;
0E4: 000 080 000 000;
0E8: 000 080 000 000;
0EC: 000 080 000 000;
0F0: 000 080 000 000;
0F4: 000 080 000 000;
0F8: 000 080 000 000;
0FC: 000 080 000 000;
END;

4
sys/hdmi_config.sv
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@@ -142,9 +142,9 @@ wire [15:0] init_data[58] =
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
{8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [4]=0 Current frame is unencrypted
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!

395
sys/hdmi_lite.sv
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@@ -1,395 +0,0 @@
//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

1
sys/hps_io.v
View File

@@ -312,6 +312,7 @@ always@(posedge clk_sys) begin
'h17,
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
endcase
sd_buff_addr <= 0;

4
sys/lpf48k.sv
View File

@@ -76,7 +76,7 @@ always @(posedge RESET or posedge CLK) begin
end
end
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * $signed(IDATA);
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_INTEG <= 0;
@@ -84,7 +84,7 @@ always @(posedge RESET or posedge CLK) begin
begin
if (CE) begin
if (W_ADDR_END) FF_INTEG <= 0;
else FF_INTEG <= FF_INTEG + W_DATA;
else FF_INTEG <= $signed(FF_INTEG) + $signed(W_DATA);
end
end
end

125
sys/osd.v
View File

@@ -23,21 +23,24 @@ parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096];
reg osd_enable;
reg [7:0] osd_buffer[4096];
reg highres = 0;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infoy;
reg [21:0] hrheight;
always@(posedge clk_sys) begin
reg [11:0] bcnt;
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
reg highres = 0;
hrheight <= info ? infoh : (OSD_HEIGHT<<highres);
old_strobe <= io_strobe;
@@ -54,8 +57,8 @@ always@(posedge clk_sys) begin
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4) begin
if(!io_din[0]) highres <= 0;
info <= io_din[2];
bcnt <= 0;
else info <= io_din[2];
bcnt <= 0;
end
// command 0x20: OSDCMDWRITE
if(io_din[7:4] == 2) begin
@@ -101,98 +104,90 @@ always @(negedge clk_video) begin
end
end
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] dsp_height;
reg [7:0] osd_byte;
reg [21:0] osd_vcnt;
reg [21:0] fheight;
reg [21:0] finfoy;
wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
reg [2:0] osd_de;
reg osd_pixel;
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] osd_vcnt;
reg [21:0] h_osd_start;
reg [21:0] v_osd_start;
reg [21:0] osd_hcnt;
reg osd_de1,osd_de2;
reg [1:0] osd_en;
if(ce_pix) begin
deD <= de_in;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if (h_cnt == h_osd_start) begin
osd_de[0] <= osd_en[1] && hrheight && (osd_vcnt < hrheight);
osd_hcnt <= 0;
end
if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
// falling edge of de
if(!de_in && deD) dsp_width <= h_cnt[21:0];
// rising edge of de
if(de_in && !deD) begin
h_cnt <= 0;
v_cnt <= v_cnt + 1'd1;
h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 0;
dsp_height <= v_cnt;
if(osd_enable) begin
if(v_cnt<320) begin
multiscan <= 0;
fheight <= hrheight;
finfoy <= infoy;
end
else if(v_cnt<640) begin
multiscan <= 1;
fheight <= hrheight << 1;
finfoy <= infoy << 1;
end
else if(v_cnt<960) begin
multiscan <= 2;
fheight <= hrheight + (hrheight<<1);
finfoy <= infoy + (infoy << 1);
end
else begin
multiscan <= 3;
fheight <= hrheight << 2;
finfoy <= infoy << 2;
end
osd_en <= (osd_en << 1) | osd_enable;
if(~osd_enable) osd_en <= 0;
if(v_cnt<320) begin
multiscan <= 0;
v_osd_start <= info ? infoy : (((v_cnt-hrheight)>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<640) begin
multiscan <= 1;
v_osd_start <= info ? (infoy<<1) : (((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<960) begin
multiscan <= 2;
v_osd_start <= info ? (infoy + (infoy << 1)) : (((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET);
end
else begin
fheight <= 0;
multiscan <= 3;
v_osd_start <= info ? (infoy<<2) : (((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET);
end
end
h_cnt <= 0;
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
osd_vcnt <= osd_vcnt + 1'd1;
if(~&osd_vcnt) osd_vcnt <= osd_vcnt + 1'd1;
end
if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
end
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[osd_vcnt[2:0]];
osd_de[2:1] <= osd_de[1:0];
end
end
// area in which OSD is being displayed
wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
wire [21:0] v_osd_end = v_osd_start + fheight;
wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
wire osd_de = osd_enable && fheight &&
(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
wire osd_pixel = osd_byte[osd_vcnt[2:0]];
reg [23:0] rdout;
assign dout = rdout;
always @(posedge clk_video) begin
rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
rdout <= ~osd_de[2] ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
de_out <= de_in;
end

120
sys/pattern_vg.v
View File

@@ -1,120 +0,0 @@
module pattern_vg
#(
parameter B=8, // number of bits per channel
X_BITS=13,
Y_BITS=13,
FRACTIONAL_BITS = 12
)
(
input reset, clk_in,
input wire [X_BITS-1:0] x,
input wire [Y_BITS-1:0] y,
input wire vn_in, hn_in, dn_in,
input wire [B-1:0] r_in, g_in, b_in,
output reg vn_out, hn_out, den_out,
output reg [B-1:0] r_out, g_out, b_out,
input wire [X_BITS-1:0] total_active_pix,
input wire [Y_BITS-1:0] total_active_lines,
input wire [7:0] pattern,
input wire [B+FRACTIONAL_BITS-1:0] ramp_step
);
reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
//wire bar_0 = y<90;
wire bar_1 = y>=90 & y<180;
wire bar_2 = y>=180 & y<270;
wire bar_3 = y>=270 & y<360;
wire bar_4 = y>=360 & y<450;
wire bar_5 = y>=450 & y<540;
wire bar_6 = y>=540 & y<630;
wire bar_7 = y>=630 & y<720;
wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
always @(posedge clk_in)
begin
vn_out <= vn_in;
hn_out <= hn_in;
den_out <= dn_in;
if (reset)
ramp_values <= 0;
else if (pattern == 8'b0) // no pattern
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
else if (pattern == 8'b1) // border
begin
if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else // Double-border (OzOnE)...
if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
begin
r_out <= 8'hD0;
g_out <= 8'hB0;
b_out <= 8'hB0;
end
else
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
end
else if (pattern == 8'd2) // moireX
begin
if ((dn_in) && x[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd3) // moireY
begin
if ((dn_in) && y[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd4) // Simple RAMP
begin
r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
if ((x == total_active_pix - 1) && (dn_in))
ramp_values <= 0;
else if ((x == 0) && (dn_in))
ramp_values <= ramp_step;
else if (dn_in)
ramp_values <= ramp_values + ramp_step;
end
end
endmodule

16
sys/pll.qip
View File

@@ -35,8 +35,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
@@ -65,11 +65,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
@@ -262,7 +262,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTIgcHM=::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMCwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

10
sys/pll.v
View File

@@ -2,7 +2,7 @@
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 598
// Generated using ACDS version 17.0 602
`timescale 1 ps / 1 ps
module pll (
@@ -10,6 +10,7 @@ module pll (
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire outclk_2, // outclk2.clk
output wire locked // locked.export
);
@@ -18,6 +19,7 @@ module pll (
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.outclk_2 (outclk_2), // outclk2.clk
.locked (locked) // locked.export
);
@@ -28,7 +30,7 @@ endmodule
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
@@ -63,7 +65,7 @@ endmodule
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_number_of_clocks" value="3" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
@@ -86,7 +88,7 @@ endmodule
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="14.0" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="56.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />

9
sys/pll/pll_0002.v
View File

@@ -13,6 +13,9 @@ module pll_0002(
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
@@ -21,14 +24,14 @@ module pll_0002(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.number_of_clocks(3),
.output_clock_frequency0("112.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("112.000000 MHz"),
.phase_shift1("-4352 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.output_clock_frequency2("56.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
@@ -80,7 +83,7 @@ module pll_0002(
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.outclk ({outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),

50
sys/reset_source.v Normal file
View File

@@ -0,0 +1,50 @@
// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire reset_vip, // .reset_vip
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
wire reset_m = sys_reset | reset_hps | reset_req;
assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

52
sys/scanlines.v Normal file
View File

@@ -0,0 +1,52 @@
module scanlines #(parameter v2=0)
(
input clk,
input [1:0] scanlines,
input [23:0] din,
output reg [23:0] dout,
input hs,vs
);
reg [1:0] scanline;
always @(posedge clk) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) begin
if(v2) begin
scanline <= scanline + 1'd1;
if (scanline == scanlines) scanline <= 0;
end
else scanline <= scanline ^ scanlines;
end
if(old_vs && ~vs) scanline <= 0;
end
wire [7:0] r,g,b;
assign {r,g,b} = din;
always @(*) begin
case(scanline)
1: // reduce 25% = 1/2 + 1/4
dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
{1'b0, g[7:1]} + {2'b00, g[7:2]},
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
2: // reduce 50% = 1/2
dout = {{1'b0, r[7:1]},
{1'b0, g[7:1]},
{1'b0, b[7:1]}};
3: // reduce 75% = 1/4
dout = {{2'b00, r[7:2]},
{2'b00, g[7:2]},
{2'b00, b[7:2]}};
default: dout = {r,g,b};
endcase
end
endmodule

78
sys/sync_vg.v
View File

@@ -1,78 +0,0 @@
module sync_vg
#(
parameter X_BITS=12, Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire [Y_BITS-1:0] v_total,
input wire [Y_BITS-1:0] v_fp,
input wire [Y_BITS-1:0] v_bp,
input wire [Y_BITS-1:0] v_sync,
input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync,
input wire [X_BITS-1:0] hv_offset,
output reg vs_out,
output reg hs_out,
output reg hde_out,
output reg vde_out,
output reg [Y_BITS-1:0] v_count_out,
output reg [X_BITS-1:0] h_count_out,
output reg [X_BITS-1:0] x_out,
output reg [Y_BITS-1:0] y_out
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
/* horizontal counter */
always @(posedge clk)
if (reset)
h_count <= 0;
else
if (h_count < h_total - 1)
h_count <= h_count + 1'd1;
else
h_count <= 0;
/* vertical counter */
always @(posedge clk)
if (reset)
v_count <= 0;
else
if (h_count == h_total - 1)
begin
if (v_count == v_total - 1)
v_count <= 0;
else
v_count <= v_count + 1'd1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, hde_out, vde_out } <= 0;
else begin
hs_out <= ((h_count < h_sync));
hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
if ((v_count == 0) && (h_count == hv_offset))
vs_out <= 1'b1;
else if ((v_count == v_sync) && (h_count == hv_offset))
vs_out <= 1'b0;
/* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count;
v_count_out <= v_count;
/* X and Y coords for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp);
y_out <= v_count - (v_sync + v_bp);
end
endmodule

50
sys/sys.qip
View File

@@ -1,25 +1,25 @@
set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name QIP_FILE sys/pll.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_cleaner.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
set_global_assignment -name VERILOG_FILE sys/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
set_global_assignment -name VERILOG_FILE sys/sync_vg.v
set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
set_global_assignment -name VERILOG_FILE sys/i2c.v
set_global_assignment -name VERILOG_FILE sys/i2s.v
set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name VERILOG_FILE sys/sd_card.v
set_global_assignment -name VERILOG_FILE sys/hps_io.v
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1

58
sys/sys_q13.qip
View File

@@ -1,29 +1,29 @@
set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name VERILOG_FILE sys/pll.v
set_global_assignment -name VERILOG_FILE sys/pll/pll_0002.v
set_global_assignment -name QIP_FILE sys/pll/pll_0002.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi_q13.qip
set_global_assignment -name VERILOG_FILE sys/pll_hdmi_cfg.v
set_global_assignment -name VERILOG_FILE sys/pll_hdmi_cfg/altera_pll_reconfig_core.v
set_global_assignment -name VERILOG_FILE sys/pll_hdmi_cfg/altera_pll_reconfig_top.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_cleaner.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
set_global_assignment -name VERILOG_FILE sys/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
set_global_assignment -name VERILOG_FILE sys/sync_vg.v
set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
set_global_assignment -name VERILOG_FILE sys/i2c.v
set_global_assignment -name VERILOG_FILE sys/i2s.v
set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name VERILOG_FILE sys/sd_card.v
set_global_assignment -name VERILOG_FILE sys/hps_io.v
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1

351
sys/sys_top.v
View File

@@ -189,16 +189,14 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
reg [15:0] cfg;
reg cfg_got = 0;
reg cfg_set = 0;
reg cfg_got = 0;
reg cfg_set = 0;
//wire [2:0] hdmi_res = cfg[10:8];
wire dvi_mode = cfg[7];
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
`ifndef LITE
wire dvi_mode = cfg[7];
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
wire vga_scaler= cfg[2];
`endif
reg cfg_custom_t = 0;
reg [5:0] cfg_custom_p1;
@@ -206,7 +204,19 @@ reg [31:0] cfg_custom_p2;
reg [4:0] vol_att = 0;
reg vip_newcfg = 0;
reg [6:0] coef_addr;
reg [8:0] coef_data;
reg coef_wr = 0;
`ifndef LITE
reg vip_newcfg = 0;
reg coef_set = 0;
`endif
wire [7:0] ARX, ARY;
reg [11:0] VSET = 0;
reg [2:0] scaler_flt;
always@(posedge clk_sys) begin
reg [7:0] cmd;
reg has_cmd;
@@ -214,8 +224,14 @@ always@(posedge clk_sys) begin
reg [7:0] cnt = 0;
old_strobe <= io_strobe;
coef_wr <= 0;
if(~io_uio) has_cmd <= 0;
if(~io_uio) begin
has_cmd <= 0;
`ifndef LITE
if(has_cmd && cmd == 'h2A) coef_set <= ~coef_set;
`endif
end
else
if(~old_strobe & io_strobe) begin
if(!has_cmd) begin
@@ -232,16 +248,18 @@ always@(posedge clk_sys) begin
cfg_set <= 0;
cnt <= cnt + 1'd1;
if(cnt<8) begin
`ifndef LITE
if(!cnt) vip_newcfg <= ~cfg_ready;
`endif
case(cnt)
0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; vip_newcfg <= 1; end
1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; vip_newcfg <= 1; end
2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; vip_newcfg <= 1; end
3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; vip_newcfg <= 1; end
4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end
5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; vip_newcfg <= 1; end
6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; vip_newcfg <= 1; end
7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; vip_newcfg <= 1; end
0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; `ifndef LITE vip_newcfg <= 1; `endif end
endcase
if(cnt == 1) begin
cfg_custom_p1 <= 0;
@@ -262,6 +280,8 @@ always@(posedge clk_sys) begin
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
if(cmd == 'h26) vol_att <= io_din[4:0];
if(cmd == 'h27) VSET <= io_din[11:0];
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
end
end
end
@@ -350,6 +370,16 @@ vip vip
.ram2_byteenable(0),
.ram2_write(0),
.uart_ri(0),
.uart_dsr(uart_dsr),
.uart_dcd(uart_dsr),
.uart_dtr(uart_dtr),
.uart_cts(uart_cts),
.uart_rts(uart_rts),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
//Video input
.in_clk(clk_vid),
.in_data({r_out, g_out, b_out}),
@@ -357,7 +387,7 @@ vip vip
.in_v_sync(vs),
.in_h_sync(hs),
.in_ce(ce_pix),
.in_f(0),
.in_f(f1),
//HDMI output
.hdmi_clk(iHdmiClk),
@@ -372,7 +402,6 @@ wire ctl_write;
wire [31:0] ctl_writedata;
wire ctl_waitrequest;
wire ctl_reset;
wire [7:0] ARX, ARY;
vip_config vip_config
(
@@ -393,6 +422,13 @@ vip_config vip_config
.VS(VS),
.VSET(VSET),
.coef_set(coef_set),
.coef_clk(clk_sys),
.coef_addr(coef_addr),
.coef_data(coef_data),
.coef_wr(coef_wr),
.scaler_flt(scaler_flt),
.address(ctl_address),
.write(ctl_write),
.writedata(ctl_writedata),
@@ -405,71 +441,6 @@ vip_config vip_config
`ifdef LITE
wire [11:0] x;
wire [11:0] y;
sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
(
.clk(iHdmiClk),
.reset(reset),
.v_total(HEIGHT+VFP+VBP+VS),
.v_fp(VFP),
.v_bp(VBP),
.v_sync(VS),
.h_total(WIDTH+HFP+HBP+HS),
.h_fp(HFP),
.h_bp(HBP),
.h_sync(HS),
.hv_offset(0),
.vde_out(vde),
.hde_out(hde),
.vs_out(vs_hdmi),
.v_count_out(),
.h_count_out(),
.x_out(x),
.y_out(y),
.hs_out(hs_hdmi)
);
wire vde, hde;
wire vs_hdmi;
wire hs_hdmi;
`ifndef HDMI_LITE
pattern_vg
#(
.B(8), // Bits per channel
.X_BITS(12),
.Y_BITS(12),
.FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern
)
pattern_vg
(
.reset(reset),
.clk_in(iHdmiClk),
.x(x),
.y(y),
.vn_in(vs_hdmi),
.hn_in(hs_hdmi),
.dn_in(vde & hde),
.r_in(0),
.g_in(0),
.b_in(0),
.vn_out(HDMI_TX_VS),
.hn_out(HDMI_TX_HS),
.den_out(hdmi_de),
.r_out(hdmi_data[23:16]),
.g_out(hdmi_data[15:8]),
.b_out(hdmi_data[7:0]),
.total_active_pix(WIDTH),
.total_active_lines(HEIGHT),
.pattern(4),
.ramp_step(20'h0333)
);
`endif
wire reset;
sysmem_lite sysmem
(
@@ -506,10 +477,18 @@ sysmem_lite sysmem
.ram2_read(0),
.ram2_writedata(0),
.ram2_byteenable(0),
.ram2_write(0)
.ram2_write(0),
.uart_ri(0),
.uart_dsr(uart_dsr),
.uart_dcd(uart_dsr),
.uart_dtr(uart_dtr),
.uart_cts(uart_cts),
.uart_rts(uart_rts),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
`ifdef HDMI_LITE
,
// HDMI frame buffer
.vbuf_clk(clk_ctl),
.vbuf_address(vbuf_address),
@@ -534,47 +513,103 @@ wire [127:0] vbuf_writedata;
wire [15:0] vbuf_byteenable;
wire vbuf_write;
assign HDMI_TX_VS = vs_hdmi;
assign HDMI_TX_HS = hs_hdmi;
hdmi_lite hdmi_lite
ascal
#(
.RAMBASE(32'h20000000),
.N_DW(128),
.N_AW(28)
)
ascal
(
.reset(reset),
.reset_na (~reset_req),
.run (1),
.freeze (0),
.clk_video(clk_vid),
.ce_pixel(ce_pix),
.video_vs(vs),
.video_de(de),
.video_d({r_out,g_out,b_out}),
.i_clk (clk_vid),
.i_ce (ce_pix),
.i_r (r_out),
.i_g (g_out),
.i_b (b_out),
.i_hs (hs),
.i_vs (vs),
.i_fl (f1),
.i_de (de),
.iauto (1),
.himin (0),
.himax (0),
.vimin (0),
.vimax (0),
.clk_hdmi(HDMI_TX_CLK),
.hdmi_hde(hde),
.hdmi_vde(vde),
.hdmi_d(hdmi_data),
.hdmi_de(hdmi_de),
.o_clk (iHdmiClk),
.o_ce (1),
.o_r (hdmi_data[23:16]),
.o_g (hdmi_data[15:8]),
.o_b (hdmi_data[7:0]),
.o_hs (HDMI_TX_HS),
.o_vs (HDMI_TX_VS),
.o_de (hdmi_de),
.htotal (WIDTH+HFP+HBP+HS),
.hsstart(WIDTH + HFP),
.hsend (WIDTH + HFP + HS),
.hdisp (WIDTH),
.hmin (hmin),
.hmax (hmax),
.vtotal (HEIGHT+VFP+VBP+VS),
.vsstart(HEIGHT + VFP),
.vsend (HEIGHT + VFP + VS),
.vdisp (HEIGHT),
.vmin (vmin),
.vmax (vmax),
.screen_w(WIDTH),
.screen_h(HEIGHT),
.quadbuf(1),
.scale_x(0),
.scale_y(0),
.scale_auto(1),
.clk_vbuf(clk_ctl),
.vbuf_address(vbuf_address),
.vbuf_burstcount(vbuf_burstcount),
.vbuf_waitrequest(vbuf_waitrequest),
.vbuf_writedata(vbuf_writedata),
.vbuf_byteenable(vbuf_byteenable),
.vbuf_write(vbuf_write),
.vbuf_readdata(vbuf_readdata),
.vbuf_readdatavalid(vbuf_readdatavalid),
.vbuf_read(vbuf_read)
`endif
.mode ({1'b1,scaler_flt,2'b00}),
.poly_clk (clk_sys),
.poly_a (coef_addr),
.poly_dw (coef_data),
.poly_wr (coef_wr),
.avl_clk (clk_ctl),
.avl_waitrequest (vbuf_waitrequest),
.avl_readdata (vbuf_readdata),
.avl_readdatavalid(vbuf_readdatavalid),
.avl_burstcount (vbuf_burstcount),
.avl_writedata (vbuf_writedata),
.avl_address (vbuf_address),
.avl_write (vbuf_write),
.avl_read (vbuf_read),
.avl_byteenable (vbuf_byteenable)
);
reg [11:0] hmin;
reg [11:0] hmax;
reg [11:0] vmin;
reg [11:0] vmax;
always @(posedge clk_vid) begin
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [2:0] state;
reg [11:0] videow;
reg [11:0] videoh;
state <= state + 1'd1;
case(state)
0: begin
wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
hcalc <= (WIDTH*ARY)/ARX;
end
6: begin
videow <= (!VSET && (wcalc > WIDTH)) ? WIDTH : wcalc[11:0];
videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
end
7: begin
hmin <= ((WIDTH - videow)>>1);
hmax <= ((WIDTH - videow)>>1) + videow - 1'd1;
vmin <= ((HEIGHT - videoh)>>1);
vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
end
endcase
end
`endif
@@ -598,7 +633,6 @@ reg [11:0] HEIGHT = 1080;
reg [11:0] VFP = 4;
reg [11:0] VS = 5;
reg [11:0] VBP = 36;
reg [11:0] VSET = 0;
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
@@ -664,8 +698,20 @@ hdmi_config hdmi_config
);
wire [23:0] hdmi_data;
wire [23:0] hdmi_data_sl;
wire hdmi_de;
scanlines #(1) HDMI_scanlines
(
.clk(iHdmiClk),
.scanlines(scanlines),
.din(hdmi_data),
.dout(hdmi_data_sl),
.hs(HDMI_TX_HS),
.vs(HDMI_TX_VS)
);
osd hdmi_osd
(
.clk_sys(clk_sys),
@@ -675,7 +721,7 @@ osd hdmi_osd
.io_din(io_din),
.clk_video(iHdmiClk),
.din(hdmi_data),
.din(hdmi_data_sl),
.dout(HDMI_TX_D),
.de_in(hdmi_de),
.de_out(HDMI_TX_DE)
@@ -700,7 +746,19 @@ i2s i2s
///////////////////////// VGA output //////////////////////////////////
wire [23:0] vga_q;
wire [23:0] vga_data_sl;
scanlines #(0) VGA_scanlines
(
.clk(clk_vid),
.scanlines(scanlines),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.dout(vga_data_sl),
.hs(hs1),
.vs(vs1)
);
osd vga_osd
(
.clk_sys(clk_sys),
@@ -710,11 +768,12 @@ osd vga_osd
.io_din(io_din),
.clk_video(clk_vid),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.din(vga_data_sl),
.dout(vga_q),
.de_in(de)
);
wire [23:0] vga_q;
wire [23:0] vga_o;
vga_out vga_out
@@ -722,20 +781,11 @@ vga_out vga_out
.ypbpr_full(1),
.ypbpr_en(ypbpr_en),
.dout(vga_o),
`ifdef LITE
.din(vga_q)
`else
.din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q)
`endif
);
`ifdef LITE
wire vs1 = vs;
wire hs1 = hs;
`else
wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
`endif
wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1;
assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1;
@@ -832,7 +882,8 @@ wire signed [15:0] audio_ls, audio_rs;
wire audio_s;
wire [1:0] audio_mix;
wire [7:0] r_out, g_out, b_out;
wire vs, hs, de;
wire vs, hs, de, f1;
wire [1:0] scanlines;
wire clk_sys, clk_vid, ce_pix;
wire ram_clk;
@@ -851,8 +902,15 @@ wire [1:0] led_power;
wire [1:0] led_disk;
wire vs_emu, hs_emu;
sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs);
sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs);
sync_fix sync_v(clk_vid, vs_emu, vs);
sync_fix sync_h(clk_vid, hs_emu, hs);
wire uart_dtr;
wire uart_dsr;
wire uart_cts;
wire uart_rts;
wire uart_rxd;
wire uart_txd;
emu emu
(
@@ -869,15 +927,15 @@ emu emu
.VGA_HS(hs_emu),
.VGA_VS(vs_emu),
.VGA_DE(de),
.VGA_F1(f1),
.VGA_SL(scanlines),
.LED_USER(led_user),
.LED_POWER(led_power),
.LED_DISK(led_disk),
`ifndef LITE
.VIDEO_ARX(ARX),
.VIDEO_ARY(ARY),
`endif
.AUDIO_L(audio_ls),
.AUDIO_R(audio_rs),
@@ -918,7 +976,14 @@ emu emu
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CLK(SDRAM_CLK),
.SDRAM_CKE(SDRAM_CKE)
.SDRAM_CKE(SDRAM_CKE),
.UART_CTS(uart_rts),
.UART_RTS(uart_cts),
.UART_RXD(uart_txd),
.UART_TXD(uart_rxd),
.UART_DTR(uart_dsr),
.UART_DSR(uart_dtr)
);
endmodule

149
sys/sysmem.sv
View File

@@ -38,7 +38,18 @@ module sysmem_lite
input vbuf_read, // .read
input [127:0] vbuf_writedata, // .writedata
input [15:0] vbuf_byteenable, // .byteenable
input vbuf_write // .write
input vbuf_write, // .write
input uart_cts, // uart.cts
input uart_dsr, // .dsr
input uart_dcd, // .dcd
input uart_ri, // .ri
output uart_dtr, // .dtr
output uart_rts, // .rts
output uart_out1_n, // .out1_n
output uart_out2_n, // .out2_n
input uart_rxd, // .rxd
output uart_txd // .txd
);
assign ctl_clock = clk_vip_clk;
@@ -82,7 +93,17 @@ sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
.f2h_sdram2_WRITE (ram2_write), // .write
.uart_cts (uart_cts),
.uart_dsr (uart_dsr),
.uart_dcd (uart_dcd),
.uart_ri (uart_ri),
.uart_dtr (uart_dtr),
.uart_rts (uart_rts),
.uart_out1_n (uart_out1_n),
.uart_out2_n (uart_out2_n),
.uart_rxd (uart_rxd),
.uart_txd (uart_txd)
);
reset_source reset_source (
@@ -100,105 +121,6 @@ reset_source reset_source (
endmodule
`timescale 1 ps / 1 ps
module sysmem
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input [27:0] ram_vip_address, // ram_vip.address
input [7:0] ram_vip_burstcount, // .burstcount
output ram_vip_waitrequest, // .waitrequest
output [127:0] ram_vip_readdata, // .readdata
output ram_vip_readdatavalid, // .readdatavalid
input ram_vip_read, // .read
input [127:0] ram_vip_writedata, // .writedata
input [15:0] ram_vip_byteenable, // .byteenable
input ram_vip_write, // .write
output clk_vip_clk, // clk_vip.clk
output reset_vip_reset // reset_vip.reset
);
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (ram_vip_readdata), // .readdata
.f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (ram_vip_read), // .read
.f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable
.f2h_sdram0_WRITE (ram_vip_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (reset_vip_reset), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
@@ -254,6 +176,17 @@ module sysmem_HPS_fpga_interfaces
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
,input uart_cts // uart.cts
,input uart_dsr // .dsr
,input uart_dcd // .dcd
,input uart_ri // .ri
,output uart_dtr // .dtr
,output uart_rts // .rts
,output uart_out1_n // .out1_n
,output uart_out2_n // .out2_n
,input uart_rxd // .rxd
,output uart_txd // .txd
);
@@ -527,5 +460,19 @@ cyclonev_hps_interface_fpga2sdram f2sdram(
,intermediate[4:4] // 0:0
})
);
cyclonev_hps_interface_peripheral_uart peripheral_uart1
(
.txd(uart_txd)
,.cts(uart_cts)
,.out1_n(uart_out1_n)
,.dtr(uart_dtr)
,.rts(uart_rts)
,.out2_n(uart_out2_n)
,.rxd(uart_rxd)
,.ri(uart_ri)
,.dsr(uart_dsr)
,.dcd(uart_dcd)
);
endmodule

231
sys/vip.qsys
View File

@@ -13,7 +13,15 @@
{
datum _sortIndex
{
value = "9";
value = "10";
type = "int";
}
}
element Deinterlacer
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
@@ -21,7 +29,7 @@
{
datum _sortIndex
{
value = "4";
value = "5";
type = "int";
}
}
@@ -45,7 +53,7 @@
{
datum _sortIndex
{
value = "6";
value = "7";
type = "int";
}
}
@@ -53,7 +61,7 @@
{
datum _sortIndex
{
value = "8";
value = "9";
type = "int";
}
}
@@ -69,7 +77,7 @@
{
datum _sortIndex
{
value = "5";
value = "6";
type = "int";
}
}
@@ -85,7 +93,7 @@
{
datum _sortIndex
{
value = "7";
value = "8";
type = "int";
}
}
@@ -505,62 +513,6 @@
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element vip
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@@ -586,8 +538,6 @@
<interface name="finish" internal="Reset_Source.reset_cold_req" />
<interface name="hdmi" internal="Output.Output" type="conduit" dir="end" />
<interface name="in" internal="Input.input" type="conduit" dir="end" />
<interface name="out_mix_0_Output" internal="Output.Output1" />
<interface name="out_mix_0_input" internal="Output.input1" />
<interface name="ram1" internal="HPS.f2h_sdram1_data" type="avalon" dir="end" />
<interface name="ram2" internal="HPS.f2h_sdram2_data" type="avalon" dir="end" />
<interface name="ramclk1" internal="HPS.f2h_sdram1_clock" type="clock" dir="end" />
@@ -597,13 +547,54 @@
internal="Reset_Source.reset_ctl"
type="conduit"
dir="end" />
<interface name="uart" internal="HPS.uart1" type="conduit" dir="end" />
<module name="Controller" kind="avalon_combiner" version="17.0" enabled="1" />
<module name="Deinterlacer" kind="alt_vip_cl_dil" version="17.0" enabled="1">
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BITS_PER_SYMBOL" value="8" />
<parameter name="BOB_BEHAVIOUR" value="FRAME_FOR_FIELD" />
<parameter name="CADENCE_ALGORITHM_NAME" value="CADENCE_32_22" />
<parameter name="CADENCE_DETECTION" value="0" />
<parameter name="CLOCKS_ARE_SEPARATE" value="1" />
<parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
<parameter name="DEINTERLACE_ALGORITHM" value="MOTION_ADAPTIVE" />
<parameter name="DISABLE_EMBEDDED_STREAM_CLEANER" value="0" />
<parameter name="EDI_READ_MASTER_BURST_TARGET" value="32" />
<parameter name="EDI_READ_MASTER_FIFO_DEPTH" value="128" />
<parameter name="FAMILY" value="Cyclone V" />
<parameter name="FIELD_LATENCY" value="0" />
<parameter name="INCOMING_VIDEO_IS_422" value="0" />
<parameter name="INCOMING_VIDEO_IS_YCBCR" value="0" />
<parameter name="MAX_HEIGHT" value="1080" />
<parameter name="MAX_SYMBOLS_PER_PACKET" value="10" />
<parameter name="MAX_WIDTH" value="1920" />
<parameter name="MA_READ_MASTER_BURST_TARGET" value="32" />
<parameter name="MA_READ_MASTER_FIFO_DEPTH" value="128" />
<parameter name="MEM_BASE_ADDR" value="570425344" />
<parameter name="MEM_PORT_WIDTH" value="128" />
<parameter name="MOTION_BLEED" value="1" />
<parameter name="MOTION_BPS" value="7" />
<parameter name="MOTION_READ_MASTER_BURST_TARGET" value="32" />
<parameter name="MOTION_READ_MASTER_FIFO_DEPTH" value="128" />
<parameter name="MOTION_WRITE_MASTER_BURST_TARGET" value="32" />
<parameter name="MOTION_WRITE_MASTER_FIFO_DEPTH" value="128" />
<parameter name="NUMBER_OF_COLOR_PLANES" value="3" />
<parameter name="PIXELS_IN_PARALLEL" value="2" />
<parameter name="RUNTIME_CONTROL" value="0" />
<parameter name="SWAP_F0_F1" value="0" />
<parameter name="USER_PACKETS_MAX_STORAGE" value="0" />
<parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
<parameter name="USER_PACKET_SUPPORT" value="PASSTHROUGH" />
<parameter name="WRITE_MASTER_BURST_TARGET" value="32" />
<parameter name="WRITE_MASTER_FIFO_DEPTH" value="128" />
</module>
<module name="Frame_Buffer" kind="alt_vip_cl_vfb" version="17.0" enabled="1">
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BITS_PER_SYMBOL" value="8" />
<parameter name="BURST_ALIGNMENT" value="1" />
<parameter name="CLOCKS_ARE_SEPARATE" value="0" />
<parameter name="CLOCKS_ARE_SEPARATE" value="1" />
<parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
<parameter name="CONTROLLED_DROP_REPEAT" value="0" />
<parameter name="DROP_FRAMES" value="1" />
@@ -772,8 +763,8 @@
<parameter name="TRACE_PinMuxing" value="Unused" />
<parameter name="UART0_Mode" value="N/A" />
<parameter name="UART0_PinMuxing" value="Unused" />
<parameter name="UART1_Mode" value="N/A" />
<parameter name="UART1_PinMuxing" value="Unused" />
<parameter name="UART1_Mode" value="Full" />
<parameter name="UART1_PinMuxing" value="FPGA" />
<parameter name="USB0_Mode" value="N/A" />
<parameter name="USB0_PinMuxing" value="Unused" />
<parameter name="USB1_Mode" value="N/A" />
@@ -880,7 +871,7 @@
<module name="Scaler" kind="alt_vip_cl_scl" version="17.0" enabled="1">
<parameter name="ALGORITHM_NAME" value="POLYPHASE" />
<parameter name="ALWAYS_DOWNSCALE" value="0" />
<parameter name="ARE_IDENTICAL" value="1" />
<parameter name="ARE_IDENTICAL" value="0" />
<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="BITS_PER_SYMBOL" value="8" />
@@ -890,7 +881,7 @@
<parameter name="ENABLE_FIR" value="0" />
<parameter name="EXTRA_PIPELINING" value="1" />
<parameter name="FAMILY" value="Cyclone V" />
<parameter name="H_BANKS" value="1" />
<parameter name="H_BANKS" value="2" />
<parameter name="H_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
<parameter name="H_FRACTION_BITS" value="7" />
<parameter name="H_FUNCTION" value="LANCZOS_3" />
@@ -901,8 +892,8 @@
<parameter name="H_TAPS" value="4" />
<parameter name="IS_420" value="0" />
<parameter name="IS_422" value="0" />
<parameter name="LIMITED_READBACK" value="0" />
<parameter name="LOAD_AT_RUNTIME" value="0" />
<parameter name="LIMITED_READBACK" value="1" />
<parameter name="LOAD_AT_RUNTIME" value="1" />
<parameter name="MAX_IN_HEIGHT" value="1080" />
<parameter name="MAX_IN_WIDTH" value="1920" />
<parameter name="MAX_OUT_HEIGHT" value="1080" />
@@ -914,13 +905,13 @@
<parameter name="SYMBOLS_IN_PAR" value="3" />
<parameter name="SYMBOLS_IN_SEQ" value="1" />
<parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
<parameter name="USER_PACKET_SUPPORT" value="PASSTHROUGH" />
<parameter name="V_BANKS" value="1" />
<parameter name="USER_PACKET_SUPPORT" value="DISCARD" />
<parameter name="V_BANKS" value="2" />
<parameter name="V_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
<parameter name="V_FRACTION_BITS" value="7" />
<parameter name="V_FUNCTION" value="LANCZOS_2" />
<parameter name="V_INTEGER_BITS" value="1" />
<parameter name="V_PHASES" value="32" />
<parameter name="V_PHASES" value="16" />
<parameter name="V_SIGNED" value="1" />
<parameter name="V_SYMMETRIC" value="0" />
<parameter name="V_TAPS" value="4" />
@@ -1027,6 +1018,24 @@
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
start="Deinterlacer.edi_read_master"
end="HPS.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
start="Deinterlacer.ma_read_master"
end="HPS.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
@@ -1045,11 +1054,43 @@
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
start="Deinterlacer.motion_read_master"
end="HPS.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
start="Deinterlacer.motion_write_master"
end="HPS.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="17.0"
start="Deinterlacer.write_master"
end="HPS.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon_streaming"
version="17.0"
start="Mixer.dout"
end="Video_Output.din" />
<connection
kind="avalon_streaming"
version="17.0"
start="Deinterlacer.dout"
end="Frame_Buffer.din" />
<connection
kind="avalon_streaming"
version="17.0"
@@ -1064,7 +1105,17 @@
kind="avalon_streaming"
version="17.0"
start="Video_Input.dout_0"
end="Frame_Buffer.din" />
end="Deinterlacer.din" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Deinterlacer.av_mm_clock" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Deinterlacer.av_st_clock" />
<connection
kind="clock"
version="17.0"
@@ -1085,11 +1136,6 @@
version="17.0"
start="HPS.h2f_user0_clock"
end="Video_Input.main_clock" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Frame_Buffer.main_clock" />
<connection
kind="clock"
version="17.0"
@@ -1105,6 +1151,16 @@
version="17.0"
start="HPS.h2f_user0_clock"
end="Video_Output.main_clock" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Frame_Buffer.main_clock" />
<connection
kind="clock"
version="17.0"
start="HPS.h2f_user0_clock"
end="Frame_Buffer.mem_clock" />
<connection
kind="conduit"
version="17.0"
@@ -1137,6 +1193,16 @@
version="17.0"
start="Reset_Source.reset_cold"
end="HPS.f2h_cold_reset_req" />
<connection
kind="reset"
version="17.0"
start="Reset_Source.reset_sys"
end="Deinterlacer.av_mm_reset" />
<connection
kind="reset"
version="17.0"
start="Reset_Source.reset_sys"
end="Deinterlacer.av_st_reset" />
<connection
kind="reset"
version="17.0"
@@ -1162,6 +1228,11 @@
version="17.0"
start="Reset_Source.reset_sys"
end="Video_Output.main_reset" />
<connection
kind="reset"
version="17.0"
start="Reset_Source.reset_sys"
end="Frame_Buffer.mem_reset" />
<connection
kind="reset"
version="17.0"

169
sys/vip_config.sv
View File

@@ -18,6 +18,13 @@ module vip_config
input [11:0] VS,
input [11:0] VSET,
input coef_set,
input coef_clk,
input [6:0] coef_addr,
input [8:0] coef_data,
input coef_wr,
input [2:0] scaler_flt,
output reg [8:0] address,
output reg write,
@@ -61,6 +68,22 @@ wire [21:0] init[23] =
22'h3FFFFF
};
reg [6:0] coef_a;
wire [8:0] coef_q;
coeffbuf coeffbuf
(
.wrclock(coef_clk),
.wraddress({1'b1,coef_addr}),
.data(coef_data),
.wren(coef_wr),
.rdclock(clk),
.rdaddress({|scaler_flt,coef_a}),
.q(coef_q)
);
reg [11:0] w;
reg [11:0] hfp;
reg [11:0] hbp;
@@ -87,16 +110,21 @@ always @(posedge clk) begin
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [12:0] timeout = 0;
reg [4:0] coef_state = 0;
reg [6:0] coef_n;
reg coef_setd;
reg bank = 0;
arxd <= ARX;
aryd <= ARY;
vsetd <= VSET;
coef_setd <= coef_set;
cfg <= CFG_SET;
cfgd <= cfg;
write <= 0;
if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg) || (coef_setd ^ coef_set)) begin
arx <= arxd;
ary <= aryd;
vset <= vsetd;
@@ -139,21 +167,138 @@ always @(posedge clk) begin
endcase
end
else
if(~waitrequest && state)
if(~waitrequest)
begin
state <= state + 1'd1;
write <= 0;
if((state&3)==3) begin
if(init[state>>2] == 22'h3FFFFF) begin
state <= 0;
newres <= 0;
end
else begin
writedata <= 0;
{write, address, writedata[11:0]} <= init[state>>2];
if(state) begin
state <= state + 1'd1;
if((state&3)==3) begin
if(init[state>>2] == 22'h3FFFFF) begin
state <= 0;
newres <= 0;
coef_state <= 1;
coef_a <= 0;
end
else begin
writedata <= 0;
{write, address, writedata[11:0]} <= init[state>>2];
end
end
end
else begin
case(coef_state)
1,3: coef_state <= coef_state + 1'd1;
2: begin
address <= 8;
writedata <= 0;
writedata[0] <= bank;
write <= 1;
coef_state <= coef_state + 1'd1;
end
4: begin
address <= 10;
writedata <= 0;
writedata[0] <= bank;
write <= 1;
coef_state <= coef_state + 1'd1;
end
5,7,9,11: coef_state <= coef_state + 1'd1;
6,8,10,12:
begin
coef_state <= coef_state + 1'd1;
coef_a <= coef_a + 1'd1;
coef_n <= coef_a;
address <= 9'd14 + coef_a[1:0];
writedata <= coef_q;
write <= 1;
end
13: begin
coef_state <= (&coef_n) ? 5'd14 : 5'd5;
address <= 9'd12 + coef_n[6];
writedata <= coef_n[5:2];
write <= 1;
end
14,16: coef_state <= coef_state + 1'd1;
15: begin
address <= 9;
writedata <= 0;
writedata[0] <= bank;
write <= 1;
coef_state <= coef_state + 1'd1;
end
17: begin
address <= 11;
writedata <= 0;
writedata[0] <= bank;
write <= 1;
bank <= ~bank;
coef_state <= coef_state + 1'd1;
end
18: coef_state <= 0;
endcase;
end
end
end
endmodule
module coeffbuf
(
input wrclock,
input [7:0] wraddress,
input [8:0] data,
input wren,
input rdclock,
input [7:0] rdaddress,
output[8:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({9{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.init_file = "coeff.mif",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 9,
altsyncram_component.width_b = 9,
altsyncram_component.width_byteena_a = 1;
endmodule