mister-devel/ZX-Spectrum_MISTer
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Update scaler and clocks.

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This commit is contained in:
sorgelig
2018-12-29 17:19:45 +08:00
parent 5035546a77
commit 047ee6ff32
5 changed files with 58 additions and 105 deletions
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54
ZX-Spectrum.sv
View File

@@ -163,8 +163,10 @@ localparam CONF_STR2 = {
//////////////////// CLOCKS ///////////////////
assign CLK_VIDEO = clk_sys;
wire locked;
wire clk_sys, clk_vid;
wire clk_sys;
pll pll
(
@@ -172,7 +174,6 @@ pll pll
.rst(0),
.outclk_0(clk_sys),
.outclk_1(SDRAM_CLK),
.outclk_2(clk_vid),
.locked(locked)
);
@@ -761,54 +762,7 @@ always_comb begin
endcase
end
wire [1:0] scale = status[16:15];
assign VGA_SL = {scale == 3, scale == 2};
video video
(
.*,
.ce_pix(ce_vid1),
.VGA_R(r2),
.VGA_G(g2),
.VGA_B(b2),
.VGA_HS(hs2),
.VGA_VS(vs2),
.VGA_DE(de2),
.din(cpu_dout),
.page_ram(page_ram[2:0]),
.scale(scale == 1),
.forced_scandoubler(forced_scandoubler || scale),
.wide(status[5])
);
wire ce_vid1;
reg ce_vid2;
always @(posedge clk_sys) ce_vid2 <= ce_vid1;
wire ce_vid = ce_vid2 | ce_vid1;
reg ce_pix, ce_pix1;
reg [7:0] r,r1,r2,g,g1,g2,b,b1,b2;
reg hs,hs1,hs2,vs,vs1,vs2,de,de1,de2;
always @(posedge clk_vid) begin
ce_pix1 <= ce_vid;
ce_pix <= ce_pix1;
{r1,g1,b1} <= {r2,g2,b2};
{r,g,b} <= {r1,g1,b1};
{hs1,vs1,de1} <= {hs2,vs2,de2};
{hs,vs,de} <= {hs1,vs1,de1};
end
assign {VGA_R,VGA_G,VGA_B} = {r,g,b};
assign {VGA_HS,VGA_VS,VGA_DE} = {hs,vs,de};
assign CE_PIXEL = ce_pix;
assign CLK_VIDEO = clk_vid;
video video(.*, .ce_pix(CE_PIXEL), .din(cpu_dout), .page_ram(page_ram[2:0]), .scale(status[16:15]), .wide(status[5]));
reg new_vmode = 0;
always @(posedge clk_sys) begin

86
sys/ascal.vhd
View File

@@ -255,6 +255,8 @@ ARCHITECTURE rtl OF ascal IS
----------------------------------------------------------
-- Input image
SIGNAL i_phs,i_pvs,i_pfl,i_pde,i_pce : std_logic;
SIGNAL i_pr,i_pg,i_pb : unsigned(7 DOWNTO 0);
SIGNAL i_freeze : std_logic;
SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12;
SIGNAL i_hrsize,i_vrsize : uint12;
@@ -948,7 +950,6 @@ BEGIN
ELSIF rising_edge(i_clk) THEN
i_push<='0';
i_pushhead<='0';
i_eol<='0'; -- End Of Line
i_freeze <=freeze; -- <ASYNC>
i_iauto<=iauto; -- <ASYNC> ?
@@ -959,7 +960,7 @@ BEGIN
i_head(111 DOWNTO 96)<=to_unsigned(N_BURST,16); -- Header size
i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD
i_head(80)<=i_inter;
i_head(81)<=i_fl;
i_head(81)<=i_pfl;
i_head(82)<=i_hdown;
i_head(83)<=i_vdown;
i_head(79 DOWNTO 64)<=to_unsigned(i_hrsize,16); -- Image width
@@ -967,32 +968,42 @@ BEGIN
i_head(47 DOWNTO 32)<=
to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes
i_head(31 DOWNTO 0)<=x"0000_0000"; -- TBD
------------------------------------------------------
i_pr <=i_r;
i_pg <=i_g;
i_pb <=i_b;
i_phs<=i_hs;
i_pvs<=i_vs;
i_pfl<=i_fl;
i_pde<=i_de;
i_pce<=i_ce;
------------------------------------------------------
IF i_ce='1' THEN
IF i_pce='1' THEN
----------------------------------------------------
i_hs_pre<=i_hs;
i_vs_pre<=i_vs;
i_de_pre<=i_de;
i_fl_pre<=i_fl;
i_hs_pre<=i_phs;
i_vs_pre<=i_pvs;
i_de_pre<=i_pde;
i_fl_pre<=i_pfl;
----------------------------------------------------
-- Detect interlaced video
IF NOT INTER THEN
i_intercnt<=0;
ELSIF i_fl/=i_fl_pre THEN
ELSIF i_pfl/=i_fl_pre THEN
i_intercnt<=3;
ELSIF i_vs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN
ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN
i_intercnt<=i_intercnt-1;
END IF;
i_inter<=to_std_logic(i_intercnt>0);
----------------------------------------------------
IF i_vs='1' AND i_vs_pre='0' THEN
IF i_pvs='1' AND i_vs_pre='0' THEN
i_sof<='1';
END IF;
IF i_de='1' AND i_sof='1' THEN
IF i_pde='1' AND i_sof='1' THEN
i_sof<='0';
i_vcpt<=0;
IF i_inter='1' AND i_flm='1' AND i_half='0' AND INTER THEN
@@ -1005,33 +1016,33 @@ BEGIN
END IF;
END IF;
IF i_de='1' THEN
i_flm<=NOT i_fl;
IF i_pde='1' THEN
i_flm<=NOT i_pfl;
END IF;
i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax+1 AND
i_vcpt>=i_vmin AND i_vcpt<=i_vmax AND i_de='1');
i_vcpt>=i_vmin AND i_vcpt<=i_vmax AND i_pde='1');
-- Detects end of frame for triple buffering.
-- Waits for second frame of interlaced video
i_endframe<=to_std_logic(i_vcpt=i_vmax + 1 AND
(i_inter='0' OR i_fl='1'));
(i_inter='0' OR i_pfl='1'));
-- Detects third line for low lag mode
i_syncline<=to_std_logic(i_vcpt=i_vmin + 3);
----------------------------------------------------
IF i_de='1' AND i_de_pre='0' THEN
IF i_pde='1' AND i_de_pre='0' THEN
i_vimaxc<=i_vcpt;
i_hcpt<=0;
ELSE
i_hcpt<=(i_hcpt+1) MOD 4096;
END IF;
IF i_de='0' AND i_de_pre='1' THEN
IF i_pde='0' AND i_de_pre='1' THEN
i_himax<=i_hcpt;
END IF;
IF i_vs='1' THEN
IF i_pvs='1' THEN
i_vimax<=i_vimaxc;
END IF;
@@ -1040,7 +1051,7 @@ BEGIN
i_hmin<=0;
i_hmax<=i_himax;
i_vmin<=0;
IF i_inter='0' OR i_fl='0' THEN
IF i_inter='0' OR i_pfl='0' THEN
i_vmax<=i_vimax;
END IF;
ELSE
@@ -1051,17 +1062,15 @@ BEGIN
i_vmax<=vimax; -- <ASYNC>
END IF;
--pragma synthesis_off
----------------------------------------------------
-- TEST : Scan image properties
IF i_hs='1' AND i_hs_pre='0' AND i_vcpt=1 THEN i_hsstart<=i_hcpt+1; END IF;
IF i_hs='0' AND i_hs_pre='1' AND i_vcpt=1 THEN i_hsend<=i_hcpt+1; END IF;
IF i_de='1' AND i_de_pre='0' AND i_vcpt=1 THEN i_htotal<=i_hcpt+1; END IF;
IF i_phs='1' AND i_hs_pre='0' AND i_vcpt=1 THEN i_hsstart<=i_hcpt+1; END IF;
IF i_phs='0' AND i_hs_pre='1' AND i_vcpt=1 THEN i_hsend<=i_hcpt+1; END IF;
IF i_pde='1' AND i_de_pre='0' AND i_vcpt=1 THEN i_htotal<=i_hcpt+1; END IF;
IF i_vs='1' AND i_vs_pre='0' THEN i_vsstart<=i_vcpt; END IF;
IF i_vs='0' AND i_vs_pre='1' THEN i_vsend<=i_vcpt; END IF;
IF i_de='1' AND i_sof='1' THEN i_vtotal<=i_vcpt; END IF;
--pragma synthesis_on
IF i_pvs='1' AND i_vs_pre='0' THEN i_vsstart<=i_vcpt; END IF;
IF i_pvs='0' AND i_vs_pre='1' THEN i_vsend<=i_vcpt; END IF;
IF i_pde='1' AND i_sof='1' THEN i_vtotal<=i_vcpt; END IF;
----------------------------------------------------
i_mode<=mode; -- <ASYNC>
@@ -1132,7 +1141,7 @@ BEGIN
----------------------------------------------------
-- Downscaling interpolation
i_hpixp<=(i_r,i_g,i_b);
i_hpixp<=(i_pr,i_pg,i_pb);
i_hpix0<=i_hpixp;
i_hpix1<=i_hpix0;
i_hpix2<=i_hpix1;
@@ -1237,7 +1246,7 @@ BEGIN
END IF;
-- Delay I_HS raising for a few cycles, finish ongoing mem. access
IF i_hs='1' AND i_hs_pre='0' THEN
IF i_phs='1' AND i_hs_pre='0' THEN
i_hs_delay<=0;
ELSIF i_hs_delay<15 THEN
i_hs_delay<=i_hs_delay+1;
@@ -1257,24 +1266,24 @@ BEGIN
END IF;
END IF;
IF i_vs='0' AND i_vs_pre='1' THEN
IF i_pvs='0' AND i_vs_pre='1' THEN
i_vacc<=i_ovsize/2 + i_vsize/2;
-- Push header
i_pushhead<=to_std_logic(HEADER);
i_hbfix<='0';
END IF;
END IF; -- IF i_ce='1'
END IF; -- IF i_pce='1'
------------------------------------------------------
-- Push pixels to downscaling line buffer
i_lwr<=i_hnp4 AND i_ven5 AND i_ce;
i_lwr<=i_hnp4 AND i_ven5 AND i_pce;
IF i_lwr='1' THEN
i_lwad<=(i_lwad+1) MOD OHRES;
END IF;
i_ldw<=i_hpix;
IF i_hnp3='1' AND i_ven4='1' AND i_ce='1' THEN
IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN
i_lrad<=(i_lrad+1) MOD OHRES;
END IF;
@@ -2206,7 +2215,7 @@ BEGIN
o_llicpt<=0;
o_llipos<=o_llocpt;
o_llisize<=o_llicpt;
o_llfl<=i_fl; -- <ASYNC>
o_llfl<=i_pfl; -- <ASYNC>
ELSE
o_llicpt<=o_llicpt+1;
END IF;
@@ -2224,7 +2233,7 @@ BEGIN
-- Period difference between input and output images
o_lldiff<=(integer(o_llosize) - integer(o_llisize));
o_lltune_i(14)<='0'; -- Unused
o_lltune_i(14)<='0'; -- Interleaved video field
o_lltune_i(7 DOWNTO 6)<=i_inter & o_llfl; -- <ASYNC>
IF o_llup='1' THEN
o_llcpt<=0;
@@ -2389,13 +2398,11 @@ BEGIN
o_b<=x"00";
END IF;
--pragma synthesis_off
IF o_mode(2 DOWNTO 0)="111" AND o_vcpt<2*8 THEN
o_r<=(OTHERS => o_debug_set);
o_g<=(OTHERS => o_debug_set);
o_b<=(OTHERS => o_debug_set);
END IF;
--pragma synthesis_on
----------------------------------------------------
END IF;
@@ -2403,7 +2410,6 @@ BEGIN
END PROCESS VSCAL;
--pragma synthesis_off
-----------------------------------------------------------------------------
-- DEBUG
Debug:PROCESS(o_clk) IS
@@ -2507,8 +2513,6 @@ BEGIN
'0' & o_lltune_i(7 DOWNTO 4) & -- 1
'0' & o_lltune_i(3 DOWNTO 0) & -- 1
CS(" ");
----------------------------------------------------------------------------
--pragma synthesis_on
----------------------------------------------------------------------------
END ARCHITECTURE rtl;

10
sys/pll.qip
View File

@@ -35,8 +35,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
@@ -262,7 +262,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTIgcHM=::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMCwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

4
sys/pll.v
View File

@@ -10,7 +10,6 @@ module pll (
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire outclk_2, // outclk2.clk
output wire locked // locked.export
);
@@ -19,7 +18,6 @@ module pll (
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.outclk_2 (outclk_2), // outclk2.clk
.locked (locked) // locked.export
);
@@ -65,7 +63,7 @@ endmodule
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="3" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />

9
sys/pll/pll_0002.v
View File

@@ -13,9 +13,6 @@ module pll_0002(
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
@@ -24,14 +21,14 @@ module pll_0002(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(3),
.number_of_clocks(2),
.output_clock_frequency0("112.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("112.000000 MHz"),
.phase_shift1("-4352 ps"),
.duty_cycle1(50),
.output_clock_frequency2("56.000000 MHz"),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
@@ -83,7 +80,7 @@ module pll_0002(
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_2, outclk_1, outclk_0}),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),