mister-devel/Vectrex_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/Vectrex_MiSTer.git synced 2026-04-19 03:05:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix the slacks.

Browse Source
This commit is contained in:
sorgelig
2020-05-12 23:49:15 +08:00
parent 4c3d50cc9a
commit a125ca01f8
2 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Vectrex.sdc Normal file
View File

@@ -0,0 +1,7 @@
derive_pll_clocks
derive_clock_uncertainty
set_multicycle_path -from {emu|vectrex|limited_*} -setup 2
set_multicycle_path -from {emu|vectrex|limited_*} -hold 1
set_false_path -from {emu|hps_io|status*}

1
files.qip
View File

@@ -11,4 +11,5 @@ set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
set_global_assignment -name VERILOG_FILE rtl/mc6809is.v
set_global_assignment -name VERILOG_FILE rtl/mc6809.v
set_global_assignment -name VHDL_FILE rtl/vectrex.vhd
set_global_assignment -name SDC_FILE Vectrex.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Vectrex.sv