Gyorgy Szombathelyi
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0f1eb09080
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Fix signal name
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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e42f5a0c25
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GB: Redo ADD SP,dd
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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c5092d1300
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GB: fixed F flag so that 4 lowest bits always return 0
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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a68906221e
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GB: redo LD HL,SP
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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cae28f6b81
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GB: set ACC and F reset value
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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b18f91acb3
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GB: halt bug implemented
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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f52ed600f9
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GB: fixed rotate, cpl, scf and ccf opcodes, finally passed blargg's cpu_instr tests
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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9a4698a6b8
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GB: IStatus update
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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8937b8c015
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GB: cpu can use IRQ without IME set to resume from Halt
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2020-08-10 20:18:04 +02:00 |
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Gyorgy Szombathelyi
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dd3244e455
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Hold address bus for Z80 only
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2020-08-10 20:16:26 +02:00 |
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Gyorgy Szombathelyi
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1866ce483d
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Refresh address also can remain on the bus (+move bus hold to T80.vhd)
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2020-08-04 00:18:34 +02:00 |
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Gyorgy Szombathelyi
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1a6bf49b82
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Add the NMI cycle fix patch
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2020-07-12 18:31:15 +02:00 |
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Gyorgy Szombathelyi
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f653172436
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Don't restart busack cycle if busreq was held during reset
(from Genesis)
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2020-06-28 00:45:18 +02:00 |
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Gyorgy Szombathelyi
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250a292fef
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Apply the external register set patch
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2020-06-28 00:41:06 +02:00 |
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sorgelig
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4872af96c7
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T80: some fixes and updates.
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2018-12-04 20:54:31 +01:00 |
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sorgelig
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3a38412d13
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T80: fix MEMPTR for all known cases.
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2018-08-02 16:45:39 +08:00 |
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sorgelig
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c6bf68741e
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T80: Fix IN/INI/INIR/IND/INDR/OUTI/OTIR/OUTD/OTDR flags.
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2018-08-02 16:45:31 +08:00 |
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sorgelig
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2827372ffa
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T80: Fix X/Y flags of BIT N,(HL)/(XY) instrictions.
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2018-08-02 16:45:22 +08:00 |
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sorgelig
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aa3fc8f802
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T80: remove false comment.
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2018-07-23 20:54:50 +08:00 |
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sorgelig
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d85ced11eb
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T80: Fix undocumented flags of CPI/CPIR/CPD/CPDR instructions.
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2018-07-22 02:57:34 +08:00 |
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sorgelig
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cbe6aae02f
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T80: fix interrupt ack after IN/OUT instructions.
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2018-07-21 09:08:47 +08:00 |
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sorgelig
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501424c49d
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T80: fix regression.
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2018-07-20 03:47:03 +08:00 |
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sorgelig
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670437ea23
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T80: cleanup, fix interrupt ack cycle, fix WAIT_n.
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2018-07-14 04:25:45 +08:00 |
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sorgelig
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a16f1a5871
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T80: Fix RLD/RRD timings. Fix address for non-bus MCycle.
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2018-07-11 08:40:41 +08:00 |
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sorgelig
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86fdb49d20
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Replace CPU model to one with presize timings.
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2018-07-06 16:51:08 +08:00 |
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sorgelig
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5751277302
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Initial commit.
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2018-07-01 12:46:41 +08:00 |
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