Commit Graph

26 Commits

Author SHA1 Message Date
Gyorgy Szombathelyi
0f1eb09080 Fix signal name 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
e42f5a0c25 GB: Redo ADD SP,dd 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
c5092d1300 GB: fixed F flag so that 4 lowest bits always return 0 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
a68906221e GB: redo LD HL,SP 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
cae28f6b81 GB: set ACC and F reset value 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
b18f91acb3 GB: halt bug implemented 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
f52ed600f9 GB: fixed rotate, cpl, scf and ccf opcodes, finally passed blargg's cpu_instr tests 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
9a4698a6b8 GB: IStatus update 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
8937b8c015 GB: cpu can use IRQ without IME set to resume from Halt 2020-08-10 20:18:04 +02:00
Gyorgy Szombathelyi
dd3244e455 Hold address bus for Z80 only 2020-08-10 20:16:26 +02:00
Gyorgy Szombathelyi
1866ce483d Refresh address also can remain on the bus (+move bus hold to T80.vhd) 2020-08-04 00:18:34 +02:00
Gyorgy Szombathelyi
1a6bf49b82 Add the NMI cycle fix patch 2020-07-12 18:31:15 +02:00
Gyorgy Szombathelyi
f653172436 Don't restart busack cycle if busreq was held during reset
(from Genesis)
2020-06-28 00:45:18 +02:00
Gyorgy Szombathelyi
250a292fef Apply the external register set patch 2020-06-28 00:41:06 +02:00
sorgelig
4872af96c7 T80: some fixes and updates. 2018-12-04 20:54:31 +01:00
sorgelig
3a38412d13 T80: fix MEMPTR for all known cases. 2018-08-02 16:45:39 +08:00
sorgelig
c6bf68741e T80: Fix IN/INI/INIR/IND/INDR/OUTI/OTIR/OUTD/OTDR flags. 2018-08-02 16:45:31 +08:00
sorgelig
2827372ffa T80: Fix X/Y flags of BIT N,(HL)/(XY) instrictions. 2018-08-02 16:45:22 +08:00
sorgelig
aa3fc8f802 T80: remove false comment. 2018-07-23 20:54:50 +08:00
sorgelig
d85ced11eb T80: Fix undocumented flags of CPI/CPIR/CPD/CPDR instructions. 2018-07-22 02:57:34 +08:00
sorgelig
cbe6aae02f T80: fix interrupt ack after IN/OUT instructions. 2018-07-21 09:08:47 +08:00
sorgelig
501424c49d T80: fix regression. 2018-07-20 03:47:03 +08:00
sorgelig
670437ea23 T80: cleanup, fix interrupt ack cycle, fix WAIT_n. 2018-07-14 04:25:45 +08:00
sorgelig
a16f1a5871 T80: Fix RLD/RRD timings. Fix address for non-bus MCycle. 2018-07-11 08:40:41 +08:00
sorgelig
86fdb49d20 Replace CPU model to one with presize timings. 2018-07-06 16:51:08 +08:00
sorgelig
5751277302 Initial commit. 2018-07-01 12:46:41 +08:00