mister-devel/T80
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/T80.git synced 2026-04-19 03:05:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

Commit Graph

  • 830fd0315f T80a: port from Z80n master Gyorgy Szombathelyi 2021-03-31 00:41:13 +02:00
  • 0917cdf114 There should be no auto wait states in NMI Gyorgy Szombathelyi 2021-03-30 23:45:43 +02:00
  • 8cebad773e Latch IM2 vector at the end of TState=2 Gyorgy Szombathelyi 2021-03-30 23:33:17 +02:00
  • 3436a60705 Prevent address bus overwrite Gyorgy Szombathelyi 2021-03-28 11:55:27 +02:00
  • c34e6cfbaf GB: fix interrupt acknowledge cycle (by paulb-nl) Gyorgy Szombathelyi 2021-01-08 17:46:13 +01:00
  • 35ea9d4286 Merge R800 multiplier by TobiFlex Gyorgy Szombathelyi 2020-08-21 15:33:57 +02:00
  • 6d9358c94d GB: add toplevel Gyorgy Szombathelyi 2020-08-10 20:05:55 +02:00
  • 44fd7014d4 Update README with Gameboy fixes Gyorgy Szombathelyi 2020-08-10 19:49:20 +02:00
  • 0f1eb09080 Fix signal name Gyorgy Szombathelyi 2020-08-10 19:46:17 +02:00
  • b2edeebe13 ALU: silence warning Gyorgy Szombathelyi 2020-08-10 19:16:07 +02:00
  • 72af3ccc9a GB: Jump doesn't set WZ Gyorgy Szombathelyi 2020-08-10 18:51:35 +02:00
  • dbb60677e6 GB: fix test constants Gyorgy Szombathelyi 2020-08-10 18:18:45 +02:00
  • 72fe92ccb2 GB: fix JP cycles Gyorgy Szombathelyi 2020-08-10 16:14:02 +02:00
  • 701d6e508a GB: fix RETI cycles Gyorgy Szombathelyi 2020-08-10 16:04:30 +02:00
  • e42f5a0c25 GB: Redo ADD SP,dd Gyorgy Szombathelyi 2020-08-10 03:19:33 +02:00
  • c5092d1300 GB: fixed F flag so that 4 lowest bits always return 0 Gyorgy Szombathelyi 2020-08-10 02:55:36 +02:00
  • a68906221e GB: redo LD HL,SP Gyorgy Szombathelyi 2020-08-10 02:49:39 +02:00
  • 0568d4bf70 Fix LD SP,HL timings Gyorgy Szombathelyi 2020-08-10 02:23:28 +02:00
  • 82241cb8aa Fix ADD HL,ss timings Gyorgy Szombathelyi 2020-08-10 02:18:59 +02:00
  • cae28f6b81 GB: set ACC and F reset value Gyorgy Szombathelyi 2020-08-10 02:09:03 +02:00
  • 3c776d9ba1 GB: fix IM2 INT cycles Gyorgy Szombathelyi 2020-08-10 02:00:52 +02:00
  • bc23c68405 GB: apply "LD ($FF00+C)" fix by TH Gyorgy Szombathelyi 2020-08-10 01:51:51 +02:00
  • 71a109cc95 GB: fix PUSH qq cycles Gyorgy Szombathelyi 2020-08-10 01:46:13 +02:00
  • 2c31a097cd GB: fix INC ss cycles Gyorgy Szombathelyi 2020-08-10 01:42:01 +02:00
  • 15c006a7d3 GB: fix CALL cycles Gyorgy Szombathelyi 2020-08-10 01:34:54 +02:00
  • 4a5ea54df5 GB: fix RET cycles Gyorgy Szombathelyi 2020-08-10 01:31:42 +02:00
  • b18f91acb3 GB: halt bug implemented Gyorgy Szombathelyi 2020-08-10 01:00:53 +02:00
  • 91f1d2ca12 GB: skip byte after a stop opcode, fixes the Konami Collection Startup bugs Gyorgy Szombathelyi 2020-08-10 00:58:27 +02:00
  • b475441fa1 GB: fixed rst xx timing (16 cycles) Gyorgy Szombathelyi 2020-08-10 00:54:16 +02:00
  • ac8aa0cf7b GB: fixed 16 bit DEC opcode timing Gyorgy Szombathelyi 2020-08-10 00:46:43 +02:00
  • f52ed600f9 GB: fixed rotate, cpl, scf and ccf opcodes, finally passed blargg's cpu_instr tests Gyorgy Szombathelyi 2020-08-10 00:45:41 +02:00
  • 9a4698a6b8 GB: IStatus update Gyorgy Szombathelyi 2020-08-10 00:34:06 +02:00
  • cf7649292a GB: fixed DAA instruction (different from Z80) Gyorgy Szombathelyi 2020-08-10 00:17:01 +02:00
  • 8937b8c015 GB: cpu can use IRQ without IME set to resume from Halt Gyorgy Szombathelyi 2020-08-10 00:09:44 +02:00
  • 5153e10cd9 GB: ret cc mcycles 20/8 Gyorgy Szombathelyi 2020-08-09 23:59:49 +02:00
  • dd3244e455 Hold address bus for Z80 only Gyorgy Szombathelyi 2020-08-10 20:16:26 +02:00
  • 0e89c1826c Exchange ED 5E <-> ED 77 (undocumented NOP/IM2) Gyorgy Szombathelyi 2020-08-04 14:40:05 +02:00
  • 1866ce483d Refresh address also can remain on the bus (+move bus hold to T80.vhd) Gyorgy Szombathelyi 2020-08-04 00:18:34 +02:00
  • e221144f2c Use the component defs from T80_Pack Gyorgy Szombathelyi 2020-07-12 18:51:11 +02:00
  • 52bc9a9faf Auto-wait is enough for the NMI cycle Gyorgy Szombathelyi 2020-07-12 18:44:19 +02:00
  • 1a6bf49b82 Add the NMI cycle fix patch Gyorgy Szombathelyi 2020-07-12 18:31:15 +02:00
  • f653172436 Don't restart busack cycle if busreq was held during reset Gyorgy Szombathelyi 2020-06-28 00:45:18 +02:00
  • 250a292fef Apply the external register set patch Gyorgy Szombathelyi 2020-06-28 00:41:06 +02:00
  • 4872af96c7 T80: some fixes and updates. sorgelig 2018-08-24 23:10:00 +08:00
  • 3a38412d13 T80: fix MEMPTR for all known cases. sorgelig 2018-08-02 16:07:52 +08:00
  • c6bf68741e T80: Fix IN/INI/INIR/IND/INDR/OUTI/OTIR/OUTD/OTDR flags. sorgelig 2018-08-01 18:20:06 +08:00
  • 2827372ffa T80: Fix X/Y flags of BIT N,(HL)/(XY) instrictions. sorgelig 2018-07-31 23:44:26 +08:00
  • aa3fc8f802 T80: remove false comment. sorgelig 2018-07-23 20:54:50 +08:00
  • d85ced11eb T80: Fix undocumented flags of CPI/CPIR/CPD/CPDR instructions. sorgelig 2018-07-22 02:57:34 +08:00
  • cbe6aae02f T80: fix interrupt ack after IN/OUT instructions. sorgelig 2018-07-21 09:08:47 +08:00
  • 501424c49d T80: fix regression. sorgelig 2018-07-20 03:47:03 +08:00
  • 10b8756149 T80: update non-bus MCycle. sorgelig 2018-07-20 03:46:24 +08:00
  • 326ea961ef T80: fix RETI instruction. It's the same as RET, not RETN. sorgelig 2018-07-16 20:39:00 +08:00
  • 670437ea23 T80: cleanup, fix interrupt ack cycle, fix WAIT_n. sorgelig 2018-07-14 04:25:45 +08:00
  • 32d3457711 T80: fix IORQ_n in interrupt cycle. sorgelig 2018-07-12 08:10:54 +08:00
  • 63ca00ad0a T80: fix INIR/INDR timings. sorgelig 2018-07-12 04:30:57 +08:00
  • a16f1a5871 T80: Fix RLD/RRD timings. Fix address for non-bus MCycle. sorgelig 2018-07-11 07:37:18 +08:00
  • 712b35b3b3 Inject proper clock enablers. Some cleanup and refactoring. sorgelig 2018-07-06 21:16:43 +08:00
  • 86fdb49d20 Replace CPU model to one with presize timings. sorgelig 2018-07-06 16:51:08 +08:00
  • 5751277302 Initial commit. sorgelig 2018-07-01 12:46:41 +08:00