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33 lines
777 B
Verilog
33 lines
777 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/28/2018 01:31:30 PM
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// Design Name:
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// Module Name: SlugPositionSet
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SlugPositionSet(
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input [9:0] Hcount,
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input GreenHoriz,
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output load
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);
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assign load = (~Hcount[9] & ~Hcount[8] & ~Hcount[7] & ~Hcount[6] & ~Hcount[5] & ~Hcount[4] & ~Hcount[3] & ~Hcount[2] & ~Hcount[1]) &
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(GreenHoriz);
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endmodule
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