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https://github.com/MiSTer-devel/SlugCross_MiSTer.git
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309 lines
7.3 KiB
Systemverilog
309 lines
7.3 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign AUDIO_S = 0;
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assign AUDIO_L = 0;
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assign AUDIO_R = 0;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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//////////////////////////////////////////////////////////////////
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wire [1:0] ar = status[9:8];
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assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
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`include "build_id.v"
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localparam CONF_STR = {
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"SlugCross;;",
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"-;",
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"O23,Difficulty,0,1,2,3;",
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"-;",
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"O89,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"J1,C;",
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"jn,A;",
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"jp,A;",
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"V,v",`BUILD_DATE
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};
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wire [21:0] gamma_bus;
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wire [2:0] buttons;
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wire [15:0] joyA;
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wire [63:0] status;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.EXT_BUS(),
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.gamma_bus(gamma_bus),
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.buttons(buttons),
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.status(status),
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.joystick_0(joyA)
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);
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/////////////////////// CLOCKS ///////////////////////////////
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wire clk_sys;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys)
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);
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wire reset = RESET | status[0] | buttons[1];
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//////////////////////////////////////////////////////////////////
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wire vsync, hsync, VBlank, HBlank;
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wire [3:0] red;
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wire [3:0] blue;
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wire [3:0] green;
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TopLevel TopLevel
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(
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.clkin(0),
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.clk (clk_sys),
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.btnU(joyA[3]),
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.btnD(joyA[2]),
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.btnL(joyA[1]),
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.btnR(joyA[0]),
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.btnC(joyA[4]),
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.sw({~status[3:2], 3'd0, reset}),
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.Hsync(VGA_HS),
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.Vsync(VGA_VS),
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.VBlank(VBlank),
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.HBlank(HBlank),
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.vgaRed(red),
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.vgaBlue(blue),
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.vgaGreen(green),
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.seg(),
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.dp(),
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.an()
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);
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assign VGA_R = {red, red};
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assign VGA_B = {blue, blue};
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assign VGA_G = {green, green};
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assign VGA_DE = ~(HBlank | VBlank);
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assign CLK_VIDEO = clk_sys;
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assign CE_PIXEL = 1;
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reg [26:0] act_cnt;
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always @(posedge clk_sys) act_cnt <= act_cnt + 1'd1;
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assign LED_USER = act_cnt[26] ? act_cnt[25:18] > act_cnt[7:0] : act_cnt[25:18] <= act_cnt[7:0];
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endmodule
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module lab7_clks(
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input clkin,
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input greset,
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output clk,
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output digsel,
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output fastclk
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);
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assign clk = clkin;
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assign fastclk = clkin;
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assign digsel = clk;
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endmodule |