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https://github.com/MiSTer-devel/SNES_MiSTer.git
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96 lines
2.4 KiB
VHDL
96 lines
2.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library STD;
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use IEEE.NUMERIC_STD.ALL;
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entity SWRAM is
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port(
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CLK : in std_logic;
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SYSCLK_CE : in std_logic;
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RST_N : in std_logic;
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ENABLE : in std_logic;
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CA : in std_logic_vector(23 downto 0);
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CPURD_N : in std_logic;
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CPUWR_N : in std_logic;
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RAMSEL_N : in std_logic;
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PA : in std_logic_vector(7 downto 0);
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PARD_N : in std_logic;
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PAWR_N : in std_logic;
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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RAM_A : out std_logic_vector(16 downto 0);
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RAM_D : out std_logic_vector(7 downto 0);
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RAM_Q : in std_logic_vector(7 downto 0);
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RAM_WE_N : out std_logic;
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RAM_CE_N : out std_logic;
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RAM_OE_N : out std_logic
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);
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end SWRAM;
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architecture rtl of SWRAM is
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signal WMADD : std_logic_vector(16 downto 0);
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begin
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process( RST_N, CLK )
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begin
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if RST_N = '0' then
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WMADD <= (others => '0');
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elsif rising_edge(CLK) then
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if ENABLE = '1' and SYSCLK_CE = '1' then
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if PAWR_N = '0' then
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case PA is
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when x"80" =>
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if RAMSEL_N = '1' then --check if DMA use WRAM in ABUS
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WMADD <= std_logic_vector(unsigned(WMADD) + 1);
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end if;
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when x"81" =>
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WMADD(7 downto 0) <= DI;
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when x"82" =>
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WMADD(15 downto 8) <= DI;
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when x"83" =>
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WMADD(16 downto 16) <= DI(0 downto 0);
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when others => null;
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end case;
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elsif PARD_N = '0' then
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case PA is
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when x"80" =>
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if RAMSEL_N = '1' then --check if DMA use WRAM in ABUS
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WMADD <= std_logic_vector(unsigned(WMADD) + 1);
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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DO <= RAM_Q;
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RAM_D <= x"FF" when PA = x"80" and RAMSEL_N = '0' else DI;
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RAM_A <= CA(16 downto 0) when RAMSEL_N = '0' else
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WMADD;
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RAM_CE_N <= '0' when ENABLE = '0' else
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'0' when RAMSEL_N = '0' else
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'0' when PA = x"80" else
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'1';
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RAM_OE_N <= '0' when ENABLE = '0' else
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'0' when RAMSEL_N = '0' and CPURD_N = '0' else
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'0' when PA = x"80" and PARD_N = '0' and RAMSEL_N = '1' else
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'1';
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RAM_WE_N <= '1' when ENABLE = '0' else
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'0' when RAMSEL_N = '0' and CPUWR_N = '0' else
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'0' when PA = x"80" and PAWR_N = '0' and RAMSEL_N = '1' else
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'1';
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end rtl;
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