mister-devel/SNES_MiSTer
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SNES_MiSTer/rtl
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Jonathan Keller 0907b84276 Allow CPU access to core memory over UART for SNI (#462) 
* Allow UART access to ROM and WRAM for SNI

* [SNI] SRAM and controller register support

* keep file definitions in files.qip

* fix SDRAM timing

* further SDRAM optimization

* add a protocol version number to SNI command handler

* sdram: move raw_req_test off the critical path

* sni: fix issue with WRAM writes to SA-1 games

* Address review feedback
2026-03-31 14:40:29 +08:00
..
65C816
65C816: NMI delay after DMA by 1 cycle (Battletoads in Battlemaniacs intro)
2026-01-04 17:44:31 +02:00
chip
CX4: Adjust bus access timings to reduce excess slowdown on wireframes (#467)
2026-02-16 13:40:43 +08:00
pll
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
SPC700
Add Save states
2025-07-08 00:53:09 +08:00
bram.vhd
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
CEGen.vhd
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
cheatcodes.sv
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
CPU.vhd
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
ddram.sv
Add Save states
2025-07-08 00:53:09 +08:00
DSP_PKG.vhd
Add Sound frequency option.
2025-12-18 21:07:37 +02:00
DSP.vhd
Add Sound frequency option.
2025-12-18 21:07:37 +02:00
hps_ext.v
MSU: fixes and refactoring.
2022-05-19 23:22:58 +08:00
ioport.sv
Rumble Support (#419)
2025-07-23 14:40:45 +08:00
lightgun.sv
Lightgun: delay P6 signal to better match a real Scope (#307)
2021-12-14 23:09:14 +08:00
main.v
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
miracle.sv
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
mlab.vhd
PPU: rework access to OAM.
2025-12-25 16:31:50 +02:00
pll.qip
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
pll.v
Update sys. Re-organize the sources.
2020-05-11 22:24:53 +08:00
PPU_PKG.vhd
PPU: rework access to OAM.
2025-12-25 16:31:50 +02:00
PPU.vhd
Revert rom address mirroring, fix async clk in PPU (#472)
2026-03-24 14:50:16 +08:00
savestate_ui.sv
Add Save states
2025-07-08 00:53:09 +08:00
savestates_map.sv
Add Save states
2025-07-08 00:53:09 +08:00
savestates_regs.sv
Add Save states
2025-07-08 00:53:09 +08:00
savestates_sa1.sv
Add Save states
2025-07-08 00:53:09 +08:00
savestates.sv
Add Save states
2025-07-08 00:53:09 +08:00
sdr.xlsx
New sdram controller.
2024-09-18 20:09:56 +03:00
sdram.sv
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
SMP.vhd
Add Save states
2025-07-08 00:53:09 +08:00
SNES.vhd
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
sni.sv
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00
SWRAM.vhd
Move WRAM to sdram. Increase bsram size to 256Kbyte.
2024-09-18 21:01:47 +03:00
uart.sv
Allow CPU access to core memory over UART for SNI (#462)
2026-03-31 14:40:29 +08:00