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45 lines
1.2 KiB
VHDL
45 lines
1.2 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.SPC700_pkg.all;
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entity SPC700_AddSub is
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port(
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A : in std_logic_vector(7 downto 0);
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B : in std_logic_vector(7 downto 0);
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CI : in std_logic;
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ADD : in std_logic;
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S : out std_logic_vector(7 downto 0);
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CO : out std_logic;
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VO : out std_logic;
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HO : out std_logic
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);
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end SPC700_AddSub;
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architecture rtl of SPC700_AddSub is
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signal tempB : std_logic_vector(7 downto 0);
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signal res : unsigned(7 downto 0);
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signal C7 : std_logic;
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begin
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tempB <= B when ADD = '1' else B xor x"FF";
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process(A, tempB, CI, ADD)
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variable temp0, temp1 : unsigned(4 downto 0);
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begin
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temp0 := ('0' & unsigned(A(3 downto 0))) + ('0' & unsigned(tempB(3 downto 0))) + ("0000" & CI);
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temp1 := ('0' & unsigned(A(7 downto 4))) + ('0' & unsigned(tempB(7 downto 4))) + ("0000" & temp0(4));
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res <= temp1(3 downto 0) & temp0(3 downto 0);
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C7 <= temp1(4);
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end process;
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S <= std_logic_vector(res);
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VO <= (not (A(7) xor tempB(7))) and (A(7) xor res(7));
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HO <= (A(4) xor B(4) xor res(4)) xor not ADD;
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CO <= C7;
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end rtl; |