14 Commits

Author	SHA1	Message	Date
Marcel Kilgus	8f22dec295	Switched IPC code to Hermes binary ... This fixes the problem with missing key-presses (key rollover). With kind permission of the original Hermes developers Laurence Reeves and Tony Firshman	2021-03-16 01:05:11 +01:00
Marcel Kilgus	cab8d29071	Restore SDRAM CS toggling ... This somehow fixes a glitch on at least one 128MB SDRAM board	2021-03-16 01:05:11 +01:00
sorgelig	77553d9ef4	Eliminate async clocks.	2021-03-06 05:18:35 +08:00
sorgelig	fd7a5cbcf0	sdram: use register in I/O buffer.	2021-03-05 23:56:32 +08:00
sorgelig	2bd6650e4b	Update sys. Some fixes and tweaks.	2021-03-05 23:55:44 +08:00
Marcel Kilgus	965a0ae9cc	Merge upstream again	2021-03-04 21:51:06 +01:00
Daniele Terdina	cbe86dd05e	Unbreak full speed	2021-02-03 00:34:05 -08:00
Daniele Terdina	fde2624b81	Accurate QL speed emulation. ... Main changes: 1) Improve accuracy of ZX8301 bus contention logic, including adding a wait cycle for writes and reducing the amount of ZX8301 bus access during VBLANK. 2) Add wait states to simulate extra bus access by 68008 for 16 bit ROM access. 3) Reworked IPC communication logic in ZX8302 and added a COMDATA latch.	2021-01-23 20:57:48 -08:00
Marcel Kilgus	134ce2fa73	Implemented fractional divisions for slower clocks ... Moved IPC to clk_sys clock domain	2020-09-26 10:14:07 +02:00
Marcel Kilgus	386e2ee53f	Fixed MDV timings	2020-09-25 23:55:01 +02:00
Marcel Kilgus	f00aa1d873	Fixed path to MGC ROM code	2020-09-18 09:11:30 +02:00
Marcel Kilgus	70e5f0bd9c	Tracking upstream changes (new source structure, updated sys)	2020-09-17 00:15:53 +02:00
sorgelig	b1f6d7f1ea	Update TG68K, fix the slacks.	2020-05-13 06:15:17 +08:00
sorgelig	17acf4a0d3	Update sys. Re-organize the sources.	2020-05-13 05:29:11 +08:00