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- add experimental data cache (debug options)

Browse Source 
- fix savestates for videoout
- CD overlay as option
This commit is contained in:
Robert Peip
2022-03-11 19:19:24 +01:00
parent d741d816e2
commit e61bd8d16d
14 changed files with 383 additions and 85 deletions
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8
PSX.sv
View File

@@ -351,7 +351,7 @@ wire reset = RESET | buttons[1] | status[0] | bios_download | cart_download | cd
// 0 1 2 3 4 5 6
// 01234567890123456789012345678901 23456789012345678901234567890123
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
// XXXXX XXX XXXXXXXXXXXXXX XXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXX XX
// XXXXX XXX XXXXXXXXXXXXXX XXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXX XX
`include "build_id.v"
parameter CONF_STR = {
@@ -385,6 +385,7 @@ parameter CONF_STR = {
"-;",
"OS,FPS Overlay,Off,On;",
"OT,Error Overlay,On,Off;",
"oR,CD Slow Overlay,Off,On;",
"-;",
"P1,Video & Audio;",
@@ -415,6 +416,7 @@ parameter CONF_STR = {
"P3OU,Sound,On,Off;",
"P3oA,SPU Reverb,On,Off;",
"P3OV,Fast Memory,Off,On;",
"P3oQ,Data Cache(Cheats Off),Off,On;",
"P3OJ,RepTimingGPU,Off,On;",
"P3OK,RepTimingDMA,Off,On;",
"P3oB,RepTimingSPUDMA,Off,On;",
@@ -783,6 +785,7 @@ psx
.loadExe(loadExe),
.fastboot(status[16]),
.FASTMEM(status[31]),
.DATACACHEON(status[58]),
.REPRODUCIBLEGPUTIMING(status[19]),
.REPRODUCIBLEDMATIMING(status[20]),
.DMABLOCKATONCE(status[26]),
@@ -790,6 +793,7 @@ psx
.INSTANTSEEK(status[21]),
.ditherOff(status[22]),
.fpscountOn(status[28]),
.cdslowOn(status[59]),
.errorOn(~status[29]),
.PATCHSERIAL(status[54]),
.noTexture(status[27]),
@@ -945,7 +949,7 @@ psx
.rewind_active (0), //(status[27] & joy[15]),
//cheats
.cheat_clear(gg_reset),
.cheats_enabled(~status[6]),
.cheats_enabled(~status[6] && ~status[58]),
.cheat_on(gg_valid),
.cheat_in(gg_code),
.cheats_active(gg_active),

189
rtl/datacache.vhd Normal file
View File

@@ -0,0 +1,189 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
library mem;
entity datacache is
generic
(
SIZE : integer;
SIZEBASEBITS : integer;
BITWIDTH : integer
);
port
(
clk1x : in std_logic;
clk2x : in std_logic;
reset : in std_logic;
read_enable : in std_logic;
read_addr : in std_logic_vector(SIZEBASEBITS-1 downto 0);
read_hit : out std_logic := '0';
read_data : out std_logic_vector(BITWIDTH -1 downto 0) := (others => '0');
write_enable : in std_logic;
write_clear : in std_logic;
write_addr : in std_logic_vector(SIZEBASEBITS-1 downto 0);
write_data : in std_logic_vector(BITWIDTH -1 downto 0) := (others => '0')
);
end entity;
architecture arch of datacache is
constant SIZEBITS : integer := integer(ceil(log2(real(SIZE))));
constant ADDRSAVEBITS : integer := SIZEBASEBITS - SIZEBITS;
type tState is
(
IDLE,
CLEARCACHE
);
signal state : tstate := IDLE;
-- memory
signal memory_addr_a : std_logic_vector(SIZEBITS - 1 downto 0) := (others => '0');
signal memory_addr_b : std_logic_vector(SIZEBITS - 1 downto 0) := (others => '0');
signal memory_datain : std_logic_vector(BITWIDTH - 1 downto 0) := (others => '0');
signal memory_dataout : std_logic_vector(BITWIDTH - 1 downto 0) := (others => '0');
signal memory_we : std_logic := '0';
-- addr save -- uppermost bit is invalid bit
signal addrsave_addr_a : std_logic_vector(SIZEBITS - 1 downto 0) := (others => '0');
signal addrsave_addr_b : std_logic_vector(SIZEBITS - 1 downto 0) := (others => '0');
signal addrsave_datain : std_logic_vector(ADDRSAVEBITS downto 0) := (others => '0');
signal addrsave_dataout : std_logic_vector(ADDRSAVEBITS downto 0) := (others => '0');
signal addrsave_we : std_logic := '0';
signal upperbits : std_logic_vector(SIZEBASEBITS - SIZEBITS - 1 downto 0) := (others => '0');
-- clear cache
signal clear_counter : unsigned(SIZEBITS - 1 downto 0);
-- debug
signal cache_requests : integer := 0;
signal cache_hits : integer := 0;
begin
iRamMemory: entity work.dpram
generic map ( addr_width => SIZEBITS, data_width => BITWIDTH)
port map
(
clock_a => clk1x,
address_a => memory_addr_a,
data_a => (memory_dataout'range => '0'),
wren_a => '0',
q_a => memory_dataout,
clock_b => clk1x,
address_b => memory_addr_b,
data_b => memory_datain,
wren_b => memory_we,
q_b => open
);
iRamaddrsave: entity work.dpram
generic map ( addr_width => SIZEBITS, data_width => ADDRSAVEBITS + 1)
port map
(
clock_a => clk2x,
address_a => addrsave_addr_a,
data_a => (addrsave_dataout'range => '0'),
wren_a => '0',
q_a => addrsave_dataout,
clock_b => clk1x,
address_b => addrsave_addr_b,
data_b => addrsave_datain,
wren_b => addrsave_we,
q_b => open
);
-- reading
memory_addr_a <= read_addr(SIZEBITS - 1 downto 0);
addrsave_addr_a <= read_addr(SIZEBITS - 1 downto 0);
upperbits <= read_addr(SIZEBASEBITS-1 downto SIZEBITS);
read_hit <= '1' when (addrsave_dataout = '0' & upperbits) else '0';
read_data <= memory_dataout;
-- writing
addrsave_addr_b <= std_logic_vector(clear_counter) when (state = CLEARCACHE) else write_addr(SIZEBITS - 1 downto 0);
addrsave_datain <= (others => '1') when (state = CLEARCACHE) else write_clear & write_addr(SIZEBASEBITS-1 downto SIZEBITS);
addrsave_we <= '1' when (state = CLEARCACHE) else write_enable;
memory_addr_b <= write_addr(SIZEBITS - 1 downto 0);
memory_datain <= write_data;
memory_we <= write_enable;
process (clk1x)
begin
if rising_edge(clk1x) then
if (reset = '1') then
state <= CLEARCACHE;
clear_counter <= (others => '0');
cache_requests <= 0;
cache_hits <= 0;
else
case(state) is
when IDLE =>
if (read_enable = '1') then
cache_requests <= cache_requests + 1;
if (read_hit = '1') then
cache_hits <= cache_hits + 1;
end if;
end if;
when CLEARCACHE =>
if (clear_counter < SIZE - 1) then
clear_counter <= clear_counter + 1;
else
state <= IDLE;
end if;
end case;
end if;
if (cache_requests = 0 and cache_hits = 1) then
cache_hits <= 0;
end if;
end if;
end process;
end architecture;

4
rtl/gpu.vhd
View File

@@ -451,6 +451,7 @@ begin
ss_timing_out(3)(24 downto 16) <= videoout_ss_out.vpos;
ss_timing_out(4)(17) <= videoout_ss_out.inVsync;
ss_timing_out(4)(20) <= videoout_ss_out.activeLineLSB;
ss_timing_out(4)(29 downto 21) <= videoout_ss_out.vdisp;
process (clk1x)
variable cmdNew : unsigned(7 downto 0);
@@ -477,7 +478,7 @@ begin
GPUSTAT_HorRes2 <= ss_gpu_in(1)(16);
GPUSTAT_HorRes1 <= ss_gpu_in(1)(18 downto 17);
GPUSTAT_VerRes <= ss_gpu_in(1)(19);
GPUSTAT_PalVideoMode <= isPal; --ss_gpu_in(1)(20); --;
GPUSTAT_PalVideoMode <= ss_gpu_in(1)(20); --isPal;
GPUSTAT_ColorDepth24 <= ss_gpu_in(1)(21);
GPUSTAT_VertInterlace <= ss_gpu_in(1)(22);
GPUSTAT_DisplayDisable <= ss_gpu_in(1)(23);
@@ -1483,6 +1484,7 @@ begin
videoout_ss_in.interlacedDisplayField <= ss_timing_in(4)(19);
videoout_ss_in.nextHCount <= ss_timing_in(4)(11 downto 0);
videoout_ss_in.vpos <= ss_timing_in(3)(24 downto 16);
videoout_ss_in.vdisp <= ss_timing_in(4)(29 downto 21);
videoout_ss_in.inVsync <= ss_timing_in(4)(17);
videoout_ss_in.activeLineLSB <= ss_timing_in(4)(20);
videoout_ss_in.GPUSTAT_InterlaceField <= ss_gpu_in(1)(13);

3
rtl/gpu_videoout_async.vhd
View File

@@ -183,6 +183,7 @@ begin
videoout_ss_out.interlacedDisplayField <= videoout_reports.interlacedDisplayField;
videoout_ss_out.nextHCount <= std_logic_vector(to_unsigned(nextHCount, 12));
videoout_ss_out.vpos <= std_logic_vector(to_unsigned(vpos, 9));
videoout_ss_out.vdisp <= std_logic_vector(to_unsigned(vdisp, 9));
videoout_ss_out.inVsync <= videoout_reports.inVsync;
videoout_ss_out.activeLineLSB <= videoout_reports.activeLineLSB;
videoout_ss_out.GPUSTAT_InterlaceField <= videoout_reports.GPUSTAT_InterlaceField;
@@ -217,7 +218,7 @@ begin
videoout_reports.GPUSTAT_InterlaceField <= videoout_ss_in.GPUSTAT_InterlaceField;
videoout_reports.GPUSTAT_DrawingOddline <= videoout_ss_in.GPUSTAT_DrawingOddline;
vdisp <= 0;
vdisp <= to_integer(unsigned(videoout_ss_in.vdisp));
allowunpause <= '1';
unpauseCnt <= 3;

1
rtl/gpu_videoout_sync.vhd
View File

@@ -77,6 +77,7 @@ begin
videoout_ss_out.interlacedDisplayField <= videoout_reports.interlacedDisplayField;
videoout_ss_out.nextHCount <= std_logic_vector(to_unsigned(nextHCount, 12));
videoout_ss_out.vpos <= std_logic_vector(to_unsigned(vpos, 9));
videoout_ss_out.vdisp <= std_logic_vector(to_unsigned(vpos, 9));
videoout_ss_out.inVsync <= videoout_reports.inVsync;
videoout_ss_out.activeLineLSB <= videoout_reports.activeLineLSB;
videoout_ss_out.GPUSTAT_InterlaceField <= videoout_reports.GPUSTAT_InterlaceField;

225
rtl/memorymux.vhd
View File

@@ -6,6 +6,7 @@ entity memorymux is
port
(
clk1x : in std_logic;
clk2x : in std_logic;
ce : in std_logic;
reset : in std_logic;
@@ -15,6 +16,7 @@ entity memorymux is
fastboot : in std_logic;
NOMEMWAIT : in std_logic;
PATCHSERIAL : in std_logic;
DATACACHEON : in std_logic;
isIdle : out std_logic;
@@ -42,6 +44,11 @@ entity memorymux is
mem_dataCache : out std_logic_vector(127 downto 0);
mem_done : out std_logic;
dma_Adr : in std_logic_vector(20 downto 0);
dma_data : in std_logic_vector(31 downto 0);
dma_rnw : in std_logic;
dma_ena : in std_logic;
--bus_exp1_addr : out unsigned(22 downto 0);
--bus_exp1_dataWrite : out std_logic_vector(31 downto 0);
bus_exp1_read : out std_logic;
@@ -163,55 +170,74 @@ architecture arch of memorymux is
EXECOPYREAD,
EXECOPYWRITE
);
signal state : tState := IDLE;
signal state : tState := IDLE;
signal byteStep : unsigned(1 downto 0);
signal waitcnt : integer range 0 to 127;
signal mem_dataRead_buf : std_logic_vector(31 downto 0);
signal mem_done_buf : std_logic := '0';
signal readram : std_logic := '0';
signal writeram : std_logic := '0';
signal maskram : std_logic := '0';
signal instantwrite : std_logic := '0';
signal data_ram : std_logic_vector(31 downto 0);
signal data_ram_rotate : std_logic_vector(31 downto 0);
signal ram_rotate_bits : std_logic_vector(1 downto 0);
signal addressData_buf : unsigned(31 downto 0);
signal dataWrite_buf : std_logic_vector(31 downto 0);
signal reqsize_buf : unsigned(1 downto 0);
signal writeMask_buf : std_logic_vector(3 downto 0);
signal addressBIOS_buf : unsigned(18 downto 0);
signal dataFromBusses : std_logic_vector(31 downto 0);
signal rotate32 : std_logic;
signal rotate16 : std_logic;
signal data_cd : std_logic_vector(31 downto 0);
signal data_spu : std_logic_vector(31 downto 0);
-- EXE handling
signal loadExe_latched : std_logic := '0';
signal exestep : integer range 0 to 8;
signal execopycnt : unsigned(31 downto 0);
signal exe_initial_pc : unsigned(31 downto 0);
signal exe_initial_gp : unsigned(31 downto 0);
signal exe_load_address : unsigned(31 downto 0);
signal exe_file_size : unsigned(31 downto 0);
signal exe_stackpointer : unsigned(31 downto 0);
signal byteStep : unsigned(1 downto 0);
signal waitcnt : integer range 0 to 127;
signal mem_dataRead_buf : std_logic_vector(31 downto 0);
signal mem_done_buf : std_logic := '0';
signal readram : std_logic := '0';
signal writeram : std_logic := '0';
signal maskram : std_logic := '0';
signal instantwrite : std_logic := '0';
signal addressData_buf : unsigned(31 downto 0);
signal dataWrite_buf : std_logic_vector(31 downto 0);
signal reqsize_buf : unsigned(1 downto 0);
signal writeMask_buf : std_logic_vector(3 downto 0);
signal addressBIOS_buf : unsigned(18 downto 0);
signal dataFromBusses : std_logic_vector(31 downto 0);
signal rotate32 : std_logic;
signal rotate16 : std_logic;
signal data_cd : std_logic_vector(31 downto 0);
signal data_spu : std_logic_vector(31 downto 0);
-- EXE handling
signal loadExe_latched : std_logic := '0';
signal exestep : integer range 0 to 8;
signal execopycnt : unsigned(31 downto 0);
signal exe_initial_pc : unsigned(31 downto 0);
signal exe_initial_gp : unsigned(31 downto 0);
signal exe_load_address : unsigned(31 downto 0);
signal exe_file_size : unsigned(31 downto 0);
signal exe_stackpointer : unsigned(31 downto 0);
-- debug
signal stallcountRead : integer;
signal stallcountReadC : integer;
signal stallcountWrite : integer;
signal stallcountWriteF : integer;
signal stallcountIntBus : integer;
signal addressDataF : std_logic := '0';
-- data cache
signal dcache_read_enable : std_logic := '0';
signal dcache_read_addr : std_logic_vector(18 downto 0) := (others => '0');
signal dcache_read_hit : std_logic;
signal dcache_read_hit_A1 : std_logic;
signal dcache_read_data : std_logic_vector(31 downto 0);
signal dcache_hit_next : std_logic := '0';
signal dcache_write_enable : std_logic := '0';
signal dcache_write_clear : std_logic := '0';
signal dcache_write_addr : std_logic_vector(18 downto 0) := (others => '0');
signal dcache_write_data : std_logic_vector(31 downto 0) := (others => '0');
-- debug
signal stallcountRead : integer;
signal stallcountReadC : integer;
signal stallcountWrite : integer;
signal stallcountWriteF : integer;
signal stallcountIntBus : integer;
signal addressDataF : std_logic := '0';
begin
isIdle <= '1' when (state = IDLE and readram = '0' and writeram = '0') else '0';
isIdle <= '1' when (state = IDLE and readram = '0' and writeram = '0' and maskram = '0' and dcache_hit_next = '0') else '0';
process (state, mem_request, mem_rnw, mem_isData, mem_addressData, mem_reqsize, mem_writeMask, mem_dataWrite, ce)
variable address : unsigned(28 downto 0);
@@ -368,33 +394,44 @@ begin
end process;
dataFromBusses <= bus_exp1_dataRead or bus_memc_dataRead or bus_pad_dataRead or bus_sio_dataRead or bus_memc2_dataRead or bus_irq_dataRead or
bus_dma_dataRead or bus_tmr_dataRead or bus_gpu_dataRead or bus_mdec_dataRead or bus_exp2_dataRead or bus_exp3_dataRead or
data_cd or data_spu;
dataFromBusses <= bus_exp1_dataRead or bus_memc_dataRead or bus_pad_dataRead or bus_sio_dataRead or bus_memc2_dataRead or bus_irq_dataRead or
bus_dma_dataRead or bus_tmr_dataRead or bus_gpu_dataRead or bus_mdec_dataRead or bus_exp2_dataRead or bus_exp3_dataRead or
data_cd or data_spu;
data_ram <= dcache_read_data when (dcache_hit_next = '1') else ram_dataRead32;
mem_dataRead <= ram_dataRead32 when (readram = '1' and ram_done = '1') else mem_dataRead_buf;
mem_done <= '1' when (instantwrite = '1') else
'1' when (readram = '1' and ram_done = '1' and maskram = '0') else
'1' when (writeram = '1' and ram_done = '1' and maskram = '0') else
mem_done_buf;
mem_dataCache <= ram_dataRead;
data_ram_rotate <= data_ram when ram_rotate_bits(1 downto 0) = "00" else
x"00" & data_ram(31 downto 8) when ram_rotate_bits(1 downto 0) = "01" else
x"0000" & data_ram(31 downto 16) when ram_rotate_bits(1 downto 0) = "10" else
x"000000" & data_ram(31 downto 24);
mem_dataRead <= data_ram_rotate when ((dcache_hit_next = '1') or (readram = '1' and ram_done = '1')) else
mem_dataRead_buf;
mem_done <= '1' when (dcache_hit_next = '1') else
'1' when (instantwrite = '1') else
'1' when (readram = '1' and ram_done = '1' and maskram = '0') else
'1' when (writeram = '1' and ram_done = '1' and maskram = '0') else
mem_done_buf;
mem_dataCache <= ram_dataRead;
process (clk1x)
variable biosPatch : std_logic_vector(31 downto 0);
begin
if rising_edge(clk1x) then
ram_ena <= '0';
mem_done_buf <= '0';
reset_exe <= '0';
ram_ena <= '0';
mem_done_buf <= '0';
reset_exe <= '0';
bus_cd_read <= '0';
bus_cd_write <= '0';
bus_SPU_read <= '0';
bus_SPU_write <= '0';
bus_cd_read <= '0';
bus_cd_write <= '0';
bus_SPU_read <= '0';
bus_SPU_write <= '0';
dcache_hit_next <= '0';
if (loadExe = '1') then
loadExe_latched <= '1';
@@ -407,7 +444,7 @@ begin
writeram <= '0';
end if;
end if;
instantwrite <= '0';
if (reset = '1') then
@@ -482,10 +519,16 @@ begin
ram_ena <= '1';
ram_128 <= '0';
ram_rnw <= mem_rnw;
ram_Adr <= "00" & std_logic_vector(mem_addressData(20 downto 0));
ram_Adr <= "00" & std_logic_vector(mem_addressData(20 downto 2)) & "00";
ram_rotate_bits <= std_logic_vector(mem_addressData(1 downto 0));
if (mem_rnw = '1') then
state <= IDLE;
readram <= '1';
if (dcache_read_hit = '1') then
dcache_hit_next <= '1';
ram_ena <= '0';
else
readram <= '1';
end if;
else
state <= IDLE;
if (ram_idle = '1') then
@@ -818,6 +861,54 @@ begin
end if;
end process;
--##############################################################
--############################### datacache
--##############################################################
dcache_write_enable <= DATACACHEON when (ram_done = '1' and maskram = '0' and readram = '1') else
DATACACHEON when (ce = '1' and mem_request = '1' and mem_isData = '1' and mem_rnw = '0' and mem_addressData(28 downto 0) < 16#800000#) else
DATACACHEON when (dma_ena = '1' and dma_rnw = '0') else
'0';
dcache_write_clear <= '1' when (ce = '1' and mem_request = '1' and mem_isData = '1' and mem_rnw = '0' and mem_writeMask /= "1111") else '0';
dcache_write_addr <= ram_Adr(20 downto 2) when (readram = '1') else
dma_Adr(20 downto 2) when (dma_ena = '1') else
std_logic_vector(mem_addressData(20 downto 2));
dcache_write_data <= ram_dataRead32 when (readram = '1') else
dma_data when (dma_ena = '1') else
mem_dataWrite;
dcache_read_enable <= ce when (state = IDLE and mem_request = '1' and mem_isData = '1' and mem_rnw = '1' and mem_addressData(28 downto 0) < 16#800000#) else '0';
dcache_read_addr <= std_logic_vector(mem_addressData(20 downto 2));
idatacache : entity work.datacache
generic map
(
SIZE => 16384,
SIZEBASEBITS => 19,
BITWIDTH => 32
)
port map
(
clk1x => clk1x,
clk2x => clk2x,
reset => reset,
read_enable => dcache_read_enable,
read_addr => dcache_read_addr,
read_hit => dcache_read_hit,
read_data => dcache_read_data,
write_enable => dcache_write_enable,
write_clear => dcache_write_clear,
write_addr => dcache_write_addr,
write_data => dcache_write_data
);
--##############################################################
--############################### debug
--##############################################################

1
rtl/pGPU.vhd
View File

@@ -42,6 +42,7 @@ package pGPU is
interlacedDisplayField : std_logic;
nextHCount : std_logic_vector(11 downto 0);
vpos : std_logic_vector(8 downto 0);
vdisp : std_logic_vector(8 downto 0);
inVsync : std_logic;
activeLineLSB : std_logic;
GPUSTAT_InterlaceField : std_logic;

1
rtl/psx.qip
View File

@@ -41,6 +41,7 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sio.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) spu_ram.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) spu.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) datacache.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) memorymux.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) memcard.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) statemanager.vhd ]

4
rtl/psx_mister.vhd
View File

@@ -19,6 +19,7 @@ entity psx_mister is
loadExe : in std_logic;
fastboot : in std_logic;
FASTMEM : in std_logic;
DATACACHEON : in std_logic;
REPRODUCIBLEGPUTIMING : in std_logic;
REPRODUCIBLEDMATIMING : in std_logic;
DMABLOCKATONCE : in std_logic;
@@ -26,6 +27,7 @@ entity psx_mister is
INSTANTSEEK : in std_logic;
ditherOff : in std_logic;
fpscountOn : in std_logic;
cdslowOn : in std_logic;
errorOn : in std_logic;
PATCHSERIAL : in std_logic;
noTexture : in std_logic;
@@ -225,6 +227,7 @@ begin
loadExe => loadExe,
fastboot => fastboot,
FASTMEM => FASTMEM,
DATACACHEON => DATACACHEON,
REPRODUCIBLEGPUTIMING => REPRODUCIBLEGPUTIMING,
REPRODUCIBLEDMATIMING => REPRODUCIBLEDMATIMING,
DMABLOCKATONCE => DMABLOCKATONCE,
@@ -232,6 +235,7 @@ begin
INSTANTSEEK => INSTANTSEEK,
ditherOff => ditherOff,
fpscountOn => fpscountOn,
cdslowOn => cdslowOn,
errorOn => errorOn,
PATCHSERIAL => PATCHSERIAL,
noTexture => noTexture,

14
rtl/psx_top.vhd
View File

@@ -24,6 +24,7 @@ entity psx_top is
loadExe : in std_logic;
fastboot : in std_logic;
FASTMEM : in std_logic;
DATACACHEON : in std_logic;
REPRODUCIBLEGPUTIMING : in std_logic;
REPRODUCIBLEDMATIMING : in std_logic;
DMABLOCKATONCE : in std_logic;
@@ -31,6 +32,7 @@ entity psx_top is
INSTANTSEEK : in std_logic;
ditherOff : in std_logic;
fpscountOn : in std_logic;
cdslowOn : in std_logic;
errorOn : in std_logic;
PATCHSERIAL : in std_logic;
noTexture : in std_logic;
@@ -440,6 +442,7 @@ architecture arch of psx_top is
-- overlay + error codes
signal cdSlow : std_logic;
signal cdslowEna : std_logic;
signal errorEna : std_logic;
signal errorCode : unsigned(3 downto 0);
@@ -1245,6 +1248,8 @@ begin
SS_Idle => SS_Idle_cd
);
cdslowEna <= cdSlow and cdslowOn;
igpu : entity work.gpu
port map
(
@@ -1275,7 +1280,7 @@ begin
Gun2X => Gun2X,
Gun2Y_scanlines => Gun2Y_scanlines,
cdSlow => cdSlow,
cdSlow => cdslowEna,
errorOn => errorOn,
errorEna => errorEna,
@@ -1481,6 +1486,7 @@ begin
port map
(
clk1x => clk1x,
clk2x => clk2x,
ce => ce_cpu,
reset => reset_intern,
@@ -1491,6 +1497,7 @@ begin
fastboot => fastboot,
NOMEMWAIT => FASTMEM,
DATACACHEON => DATACACHEON,
PATCHSERIAL => PATCHSERIAL,
ram_dataWrite => ram_cpu_dataWrite,
@@ -1516,6 +1523,11 @@ begin
mem_dataRead => mem_dataRead,
mem_dataCache => mem_dataCache,
mem_done => mem_done,
dma_Adr => ram_dma_Adr(20 downto 0),
dma_data => ram_dma_dataWrite,
dma_rnw => ram_dma_rnw,
dma_ena => ram_dma_ena,
--bus_exp1_addr => bus_exp1_addr,
--bus_exp1_dataWrite => bus_exp1_dataWrite,

9
rtl/sdram.sv
View File

@@ -145,11 +145,7 @@ always @(posedge clk_base) begin
end
if (ch1_ready_ramclock) begin
if (ch1_addr_0) begin
ch1_dout32 <= { 8'b0, ch1_dout[31:8] };
end else begin
ch1_dout32 <= ch1_dout[31:0];
end
ch1_dout32 <= ch1_dout[31:0];
end
end
@@ -162,8 +158,6 @@ reg ch1_reqprocessed_ramclock = 0;
reg req128 = 0;
reg ch1_addr_0 = 0;
reg [3:0] state = STATE_STARTUP;
reg ch1_rq, ch2_rq, ch3_rq, refreshForce_req;
@@ -313,7 +307,6 @@ always @(posedge clk) begin
state <= STATE_WAIT;
req128 <= ch1_128;
ch1_reqprocessed_ramclock <= ch1_rnw;
ch1_addr_0 <= ch1_addr[0];
end else if(ch2_req | ch2_rq) begin
{cas_addr[12:9],SDRAM_BA,SDRAM_A,cas_addr[8:0]} <= {~ch2_be[1:0], ch2_rnw, ch2_addr[25:1]};
chip <= ch2_addr[26];

6
sim/system/src/tb/sdram_model3x.vhd
View File

@@ -105,11 +105,7 @@ begin
end if;
if (done_3x = '1') then
if (addr_buffer(0) = '1') then
do32 <= x"00" & do(31 downto 8);
else
do32 <= do(31 downto 0);
end if;
do32 <= do(31 downto 0);
end if;
end process;

2
sim/system/src/tb/tb.vhd
View File

@@ -240,6 +240,7 @@ begin
loadExe => psx_LoadExe(0),
fastboot => '1',
FASTMEM => '0',
DATACACHEON => '1',
REPRODUCIBLEGPUTIMING => '0',
REPRODUCIBLEDMATIMING => '0',
DMABLOCKATONCE => '0',
@@ -247,6 +248,7 @@ begin
INSTANTSEEK => '0',
ditherOff => '0',
fpscountOn => '0',
cdslowOn => '0',
errorOn => '0',
PATCHSERIAL => '0',
noTexture => '0',

1
sim/system/vcom_all.bat
View File

@@ -64,6 +64,7 @@ vcom -2008 -quiet -work sim/psx ^
../../rtl/spu_ram.vhd ^
../../rtl/spu.vhd ^
../../rtl/cpu.vhd ^
../../rtl/datacache.vhd ^
../../rtl/memorymux.vhd ^
../../rtl/memcard.vhd ^
../../rtl/statemanager.vhd ^