Aitor Gómez García 27ce98f6fe Fix PCjr UART POST test by implementing writable LSR/MSR registers ...

The PCjr BIOS POST test writes directly to LSR and MSR registers to verify
interrupt generation - a non-standard 8250 behavior that real hardware
apparently supported.

This change adds:
- Writable LSR register with forced bits (DR, OE, PE, FE, BI, THRE)
- Writable MSR register with forced delta bits (DCTS, DDSR, TERI, DDCD)
- Standard 8250 clearing behavior:
  - DR cleared on RBR read
  - Error bits (OE, PE, FE, BI) cleared on LSR read
  - THRE cleared on THR write
  - MSR delta bits cleared on MSR read

The forced bits are OR'd with real UART status, allowing the BIOS to
inject interrupt conditions for testing. This resolves the POST "D"
error (COM1 failure) on the PCjr core.

2026-01-30 17:07:02 +01:00

..

slib_clock_div.vhd

Initial commit

2026-01-06 11:36:45 +01:00

slib_counter.vhd

Initial commit

2026-01-06 11:36:45 +01:00

slib_edge_detect.vhd

Initial commit

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slib_fifo_cyclone2.vhd

Initial commit

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slib_fifo.vhd

Initial commit

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slib_input_filter.vhd

Initial commit

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slib_input_sync.vhd

Initial commit

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slib_mv_filter.vhd

Initial commit

2026-01-06 11:36:45 +01:00

uart_16750.vhd

Fix PCjr UART POST test by implementing writable LSR/MSR registers

2026-01-30 17:07:02 +01:00

uart_baudgen.vhd

Initial commit

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uart_interrupt.vhd

Initial commit

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uart_receiver.vhd

Initial commit

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uart_transmitter.vhd

Initial commit

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uart.qip

Initial commit

2026-01-06 11:36:45 +01:00

uart.v

Initial commit

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