Aitor Gómez García 84146170a4 PCjr video: retime scandoubled CGA output path ...

Drive the scandoubled CGA mixer and top-level output from the 57.272 MHz video path and a phase-shifted sibling clock, instead of sampling the doubled signal back through the old 28.636 MHz chain.

This keeps the existing 640x200 timing and mode 06h fixes intact while preserving the full 640-pixel width when the scandoubler is enabled. Update pll_system to expose the required 28.636/57.272/114.544 MHz outputs plus the phase-shifted 57.272 MHz clock, and keep the new retiming stage on a synchronous reset to avoid extra recovery and removal pressure in the video output domain.

2026-03-13 16:27:46 +01:00

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8088

Initial commit

2026-01-06 11:36:45 +01:00

common

PCjr FDC: clamp sector range using CHS-derived limits

2026-02-27 15:52:11 +01:00

KFPC-XT

XT timing: drive the chipset with exact clock enables

2026-03-13 16:27:46 +01:00

pll

Improve clock accuracy by separating system clocks into dedicated PLL

2026-02-08 07:35:59 +01:00

pll_system

PCjr video: retime scandoubled CGA output path

2026-03-13 16:27:46 +01:00

sound

Initial commit

2026-01-06 11:36:45 +01:00

uart

Fix PCjr UART POST test by implementing writable LSR/MSR registers

2026-01-30 17:07:02 +01:00

video

PCjr video: fix mode 06h pixel serialization cadence

2026-03-13 16:27:46 +01:00

hps_ext.v

Initial commit

2026-01-06 11:36:45 +01:00

pll_system.qip

Improve clock accuracy by separating system clocks into dedicated PLL

2026-02-08 07:35:59 +01:00

pll_system.v

PCjr video: retime scandoubled CGA output path

2026-03-13 16:27:46 +01:00

pll.qip

Improve clock accuracy by separating system clocks into dedicated PLL

2026-02-08 07:35:59 +01:00

pll.v

Improve clock accuracy by separating system clocks into dedicated PLL

2026-02-08 07:35:59 +01:00