Aitor Gómez 8e4fd5ddf6 beta 2.0
* Fix CGA memory mapper.
* Switch the CPU clock at the timing of biu_done=1'b1.
* Modified to switch data sampling timing between Turbo mode and Normal…
* Modified CPU core to operate in turbo mode.
* Improved access timing to peripherals.
* Improved access speed to SDRAM.
* Memory map selection according to video mode
* Fix READY signals.
* Setting timings for tandy_16_gfx mode.
* Overscan removal.
* changed chipset clock to 50 mhz and rework.
* OSD menu update to accept HDD and FDD images.
* Added HQ2X and Gamma support.
* Add MiSTer Filters support (updated to latest framework)
2022-08-17 12:17:39 +02:00
2022-07-08 08:51:19 +02:00
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PCXT_MiSTer

PCXT port for MiSTer by spark2k06.

The purpose of this core is to implement a PCXT as reliable as possible. For this purpose, the MCL86 core from @MicroCoreLabs and KTPC-XT from @kitune-san are used.

The Graphics Gremlin project from TubeTimeUS (@schlae) has also been integrated in this first stage.

JTOPL by Jose Tejada (@topapate)

SN76489AN Compatible Implementation in VHDL Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)

Place pcxt.rom and tandy.rom (in SW folder) inside games/PCXT folder at root of SD card. Original and copyrighted ROMs can be generated on the fly using the python scripts available in the SW folder of this repository. OpenSource ROMs are available in the same folder.

https://github.com/virtualxt/pcxtbios

https://github.com/skiselev/8088_bios

https://www.xtideuniversalbios.org/

Discussion and evolution of the core in the following misterfpga forum thread:

https://misterfpga.org/viewtopic.php?t=4680&start=1020

Mounting the disk image

Initially, and until an 8-bit IDE module compatible with XTIDE is available, floppy and hdd mounting will be done through the serial port available in the core. The available transfer speeds are as follows:

  • 115200 Kbps
  • 230400 Kbps
  • 460800 Kbps
  • 921600 Kbps

By default it is set to 115200, but this speed does not work, as XTIDE does not identify it... The most suitable speed is 460800, although 921600 is possible to use only with the CPU speed at 14.318MHz.

To-do list and challenges

  • Refactor Graphics Gremlin module, the new KFPC-XT system will make this refactor possible.
  • 8-bit IDE module implementation
  • Floppy implementation
  • Addition of other modules
Description
PCXT port for MiSTer by spark2k06.
Readme GPL-3.0 253 MiB
Languages
Verilog 30.3%
SystemVerilog 29.7%
Assembly 18.2%
VHDL 8.1%
C++ 5%
Other 8.6%