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55 lines
1.5 KiB
VHDL
55 lines
1.5 KiB
VHDL
--
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-- Input synchronization
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--
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-- Author: Sebastian Witt
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-- Data: 27.01.2008
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-- Version: 1.0
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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--
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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entity slib_input_sync is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal output
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);
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end slib_input_sync;
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architecture rtl of slib_input_sync is
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signal iD : std_logic_vector(1 downto 0);
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begin
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IS_D: process (RST, CLK)
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begin
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if (RST = '1') then
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iD <= (others => '0');
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elsif (CLK'event and CLK='1') then
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iD(0) <= D;
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iD(1) <= iD(0);
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end if;
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end process;
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-- Output ports
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Q <= iD(1);
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end rtl;
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