Aitor Gómez a258ec8654 Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

..

slib_clock_div.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_counter.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_edge_detect.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_fifo_cyclone2.vhd

Upgrade to UART 16750

2022-09-12 11:12:45 +02:00

slib_fifo.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_input_filter.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_input_sync.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

slib_mv_filter.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart_16750.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart_baudgen.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart_interrupt.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart_receiver.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart_transmitter.vhd

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart.qip

Upgrade UART 16750 to version 1.4

2022-09-14 14:46:24 +02:00

uart.v

Changed clock wiring to uart module.

2022-09-14 00:53:29 +09:00