Replace the derived XT pseudo-clocks with a synchronous clock-enable scheduler on clk_chipset so the XT side runs from a single base clock without changing the mature 8088/BIU clocking model.
- generate exact CPU and peripheral enables from clk_chipset
- update the XT chipset and peripheral path to consume enables instead of reconstructed pseudo-clock edges
- keep the 8088 CLK pin as a local compatibility signal
- refresh SYSTEM.sdc so pll_system video clocks and clk_14_318 resolve cleanly in TimeQuest
Move the final CGA and HGC/MDA export off the raw exact-frequency video domains and retime it onto a phase-shifted 57.272727 MHz sibling clock, while keeping the internal 28.636363/57.272727/114.545454 MHz clocks exact.
Derive the 9.54/7.16/4.77 MHz clocks locally from clk_57_272, feed the final CE_PIXEL and overlay path from the retimed output stage, and add explicit timing constraints for the handoff into the phase-shifted video clock domain.
Split the CGA scan-doubling path into a dedicated video_scandoubler block instead of relying on the previous shared path.
This keeps the output timing stable for the CGA pipeline and avoids CRTC-sensitive behaviour seen with UM6845R-compatible software and demos.
Add OSD menu controls for VSync and HSync pulse widths in CRTC
- Add P2oMO/P2oPR parameters to configure VSync/HSync widths (Auto or 1-7)
- Implement effective_vsync_width logic with OSD override capability
- Add fixed-width HSYNC pulse shaping for TV compatibility across 40/80-col modes
- Route vsync_width_osd and hsync_width_osd to UM6845R module
- Update VSYNC generation to use effective pulse width
These controls allow users to adjust sync pulse widths via the OSD to improve compatibility with different displays and TV standards.
- Add std_hsyncwidth and vblank_border outputs to HGC module for border detection
- Connect CRTC hsync_width register (R3) to enable dynamic sync width detection
- Update HGC H_SYNCWIDTH to standard value (4'd15) per Hercules specifications
- Extend Peripherals.sv to multiplex HGC timing signals with CGA
- Fix critical bug: HBlank_fixed was calculated only in CGA clock domain
In HGC mode, it was desynchronized, causing shifted display instead of proper border
- Add HBlank_fixed_hgc calculated on clk_57_272 (HGC clock) for correct timing
- Update LHBL logic to use appropriate HBlank_fixed for each video mode
- Border now properly reduces visible area in HGC mode with correct synchronization
- Extract system clocks (clk_28_636, clk_57_272, clk_114_544, clk_9_54, clk_7_16, clk_4_77)
from main PLL to new pll_system module for improved frequency precision
- Simplify main PLL: now outputs only clk_100 (100 MHz) and clk_chipset (50 MHz)
- Replace integer divider chains with dedicated PLL outputs for better timing accuracy
- Remove clk_div3 logic and generate clock dividers directly from PLL
- New pll_system uses lower VCO frequency (300 MHz vs 1600 MHz) for better stability
- Update SYSTEM.sdc timing constraints for new clock distribution
- Reduces jitter and improves timing closure for sensitive subsystems
- Remove the Tandy 1000 mention from splash/credits text variants and keep the byline centered.
- Simplify the F11 hotkey hint to CGA ↔ HGC only.
- Regenerate msg.bin and splash.hex to match the updated text.
- Add config.tcl as the PCXT build profile and source it from PCXT.qsf with defaults for system/ROM and feature toggles.
- Gate video/audio/EMS/Tandy logic by macros in PCXT.sv, Peripherals.sv, RAM.sv, and cga.v to avoid unused I/O and logic.
- Update OSD options and video swap behavior to match CGA/HGC combos and hide Tandy-only items when disabled.
- Move constraints to SYSTEM.sdc and update files.qip.
- Refresh README.md with the PCXT default config and resource profile.
Detect Ctrl+Alt+Del at the PS/2 interface and assert a short warm reset pulse for the JTOPL2 core. This clears any stuck notes after a warm reboot without touching BIOS behavior.
Generate HGC pixel enable in the 113.75 MHz domain, retime HGC RGB/sync/blank into that domain, and resync mixer output/CE_PIXEL back to 56.875 MHz for the overlay and final mux. This removes CDC sensitivity and stabilizes HGC/MDA output across synthesis changes.
- Delay splash start until the boot splash option is loaded, with a short boot window and reset hold to avoid missed first-boot splash.
- Add a status[0] clear pulse path through Chipset/Peripherals and defer VRAM clear until after the splash completes.
- Update testbench wiring for the new status0_clear signal.
- Use the status[0] reset path to rearm the boot screen flow while suppressing it on physical reset.
- Zero the full 128 KB CGA VRAM after the status[0] reset path to avoid POST garbage; hold reset until the clear finishes.
- Reset Tandy page/NMI mask defaults on reset and add splash_rom.v to video.qip.
- Track mounted floppy presence via mgmt writes and expose it through PERIPHERALS/CHIPSET.
- Derive DIP 7/8 from drive B presence while preserving existing HGC/CGA bits.
- Propagate new fdd_present signal to the top-level PCXT.sv.
Introduce an MDA VSync delay shift register and feed the delayed VSync into the video pipeline. Update the scaler VB input to use raw VBlank when swapping video outside Tandy mode.
- align monochrome conversion timing with color output and update only on ce_pix rising edges to prevent double-sampling
- make HBlank_VGA independent of Display mode to avoid the 1‑pixel shift when switching to monochrome
In addition, the selected CGA mode (hires_mode) is taken into account internally so that the offset values do not have to be readjusted according to the mode displayed on the screen.
* Adjust RAM data output timing, by @kitune-san
* Measures against 601 errors in turbo mode, by @kitune-san
* Added 8259A INT signal output delay, by @kitune-san
