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https://github.com/MiSTer-devel/PCXT_MiSTer.git
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Memory map selection according to video mode
Thanks to this change, some parts of the area5150 demo that didn't look right, like the dancing elephant, are now displayed correctly. Thanks @somhi for noticing this detail.
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@@ -97,6 +97,10 @@ module PERIPHERALS #(
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// Mode Switch
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input logic tandy_mode
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);
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wire grph_mode;
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wire hres_mode;
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//
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// chip select
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//
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@@ -131,8 +135,8 @@ module PERIPHERALS #(
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wire tandy_chip_select_n = ~(iorq && ~address_enable_n && address[15:3] == (16'h00c0 >> 3)); // 0xc0 - 0xc7
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wire opl_chip_select_n = ~(iorq && ~address_enable_n && address[15:1] == (16'h0388 >> 1)); // 0x388 .. 0x389
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wire cga_chip_select_n = ~(~iorq && ~address_enable_n && enable_cga & (address[19:15] == 6'b10111)); // B8000 - BFFFF (32 KB)
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wire mda_chip_select_n = ~(~iorq && ~address_enable_n && enable_mda & (address[19:15] == 6'b10110)); // B0000 - B7FFF (32 KB)
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wire cga_chip_select_n = ~(~iorq && ~address_enable_n && enable_cga & (address[19:15] == 5'b10111)); // B8000 - BFFFF (16 KB / 32 KB)
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wire mda_chip_select_n = ~(~iorq && ~address_enable_n && enable_mda & (address[19:14] == 6'b101100)); // B0000 - B7FFF (16 KB)
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wire bios_select_n = ~(~iorq && ~address_enable_n && address[19:16] == 4'b1111); // F0000 - FFFFF (64 KB)
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wire xtide_select_n = ~(~iorq && ~address_enable_n && address[19:14] == 6'b111011); // EC000 - EFFFF (16 KB)
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wire uart_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h03F8);
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@@ -729,7 +733,9 @@ module PERIPHERALS #(
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.splashscreen (splashscreen),
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.thin_font (thin_font),
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.tandy_video (tandy_video),
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.color (color)
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.color (color),
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.grph_mode (grph_mode),
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.hres_mode (hres_mode)
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);
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always_ff @(posedge clock) begin
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@@ -752,13 +758,13 @@ module PERIPHERALS #(
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.clka (clock),
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.ena (~cga_chip_select_n),
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.wea (~memory_write_n),
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.addra (address[14:0]),
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.addra ((tandy_mode & grph_mode & hres_mode) ? address[14:0] : address[13:0]),
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.dina (internal_data_bus),
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.douta (cga_vram_cpu_dout),
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.clkb (clk_vga_cga),
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.web (1'b0),
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.enb (CGA_VRAM_ENABLE),
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.addrb (CGA_VRAM_ADDR[14:0]),
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.addrb ((tandy_mode & grph_mode & hres_mode) ? CGA_VRAM_ADDR[14:0] : CGA_VRAM_ADDR[13:0]),
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.dinb (8'h0),
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.doutb (CGA_VRAM_DOUT)
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);
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@@ -769,13 +775,13 @@ module PERIPHERALS #(
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.clka (clock),
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.ena (~mda_chip_select_n),
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.wea (~memory_write_n),
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.addra (address[14:0]),
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.addra (address[13:0]),
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.dina (internal_data_bus),
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.douta (mda_vram_cpu_dout),
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.clkb (clk_vga_mda),
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.web (1'b0),
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.enb (MDA_VRAM_ENABLE),
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.addrb (MDA_VRAM_ADDR[14:0]),
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.addrb (MDA_VRAM_ADDR[13:0]),
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.dinb (8'h0),
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.doutb (MDA_VRAM_DOUT)
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);
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@@ -42,7 +42,9 @@ module cga(
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input splashscreen,
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input thin_font,
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input tandy_video,
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input color
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input color,
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output grph_mode,
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output hres_mode
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);
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parameter MDA_70HZ = 0;
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@@ -73,8 +75,6 @@ module cga(
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reg[3:0] tandy_newcolor = 4'b0000;
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reg tandy_palette_set;
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wire hres_mode;
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wire grph_mode;
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wire bw_mode;
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wire mode_640;
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wire tandy_16_mode;
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