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Improved bus speed.

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kitune-san
2022-10-29 21:35:02 +09:00
parent 22664eb44c
commit baaac362d4
2 changed files with 37 additions and 60 deletions
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18
rtl/KFPC-XT/HDL/KF8237/HDL/KF8237_Address_And_Count_Registers.sv
View File

@@ -183,13 +183,12 @@ module KF8237_Address_And_Count_Registers (
//
always_comb begin
temporary_address = current_address[dma_select];
if (next_word)
if (address_hold_config)
temporary_address = temporary_address;
else if (decrement_address_config)
temporary_address = temporary_address - 16'h01;
else
temporary_address = temporary_address + 16'h01;
if (address_hold_config)
temporary_address = temporary_address;
else if (decrement_address_config)
temporary_address = temporary_address - 16'h01;
else
temporary_address = temporary_address + 16'h01;
end
//
@@ -197,8 +196,7 @@ module KF8237_Address_And_Count_Registers (
//
always_comb begin
temporary_word_count = {1'b1, current_word_count[dma_select]};
if (next_word)
temporary_word_count = temporary_word_count - 17'h01;
temporary_word_count = temporary_word_count - 17'h01;
end
//
@@ -209,7 +207,7 @@ module KF8237_Address_And_Count_Registers (
//
// Detects To Update Address[15-8]
//
assign update_high_address = (next_word) ? (transfer_address[8] != temporary_address[8]) : 1'b0;
assign update_high_address = (transfer_address[8] != temporary_address[8]);
//
// Transfer Addres

79
rtl/KFPC-XT/HDL/KF8237/HDL/KF8237_Timing_And_Control.sv
View File

@@ -75,7 +75,7 @@ module KF8237_Timing_And_Control (
state_t state;
state_t next_state;
logic ready_ff;
logic next_s4;
logic [1:0] bit_select[4] = '{ 2'b00, 2'b01, 2'b10, 2'b11 };
logic memory_to_memory_enable;
logic chanel_0_address_hold_enable;
@@ -89,7 +89,6 @@ module KF8237_Timing_And_Control (
logic [1:0] dma_select;
logic [3:0] dma_acknowledge_ff;
logic terminal_count;
logic terminal_count_internal;
logic reoutput_high_address;
logic external_end_of_process;
logic prev_read_status_register;
@@ -172,6 +171,7 @@ module KF8237_Timing_And_Control (
//
always_comb begin
next_state = state;
next_s4 = 1'b0;
casez (state)
SI: begin
@@ -183,28 +183,37 @@ module KF8237_Timing_And_Control (
next_state = S1;
end
S1: begin
if (transfer_mode[dma_select] == `TRANSFER_MODE_CASCADE)
if (transfer_mode[dma_select] == `TRANSFER_MODE_CASCADE) begin
next_state = S4;
next_s4 = 1'b1;
end
else
next_state = S2;
end
S2: begin
if (~compressed_timing)
next_state = S3;
else if ((ready_ff) || (transfer_type[dma_select] == `TRANSFER_TYPE_VERIFY))
next_state = S4;
else if (transfer_type[dma_select] == `TRANSFER_TYPE_VERIFY) begin
if (ready)
next_state = S4;
next_s4 = 1'b1;
end
else
next_state = SW;
end
S3: begin
if ((ready_ff) || (transfer_type[dma_select] == `TRANSFER_TYPE_VERIFY))
next_state = S4;
if (transfer_type[dma_select] == `TRANSFER_TYPE_VERIFY) begin
if (ready)
next_state = S4;
next_s4 = 1'b1;
end
else
next_state = SW;
end
SW: begin
if (ready_ff)
if (ready)
next_state = S4;
next_s4 = 1'b1;
end
S4: begin
if (transfer_mode[dma_select] == `TRANSFER_MODE_CASCADE)
@@ -237,20 +246,6 @@ module KF8237_Timing_And_Control (
state <= state;
end
//
// Ready Signal
//
always_ff @(posedge clock, posedge reset) begin
if (reset)
ready_ff <= 1'b0;
else if (master_clear)
ready_ff <= 1'b0;
else if (cpu_clock_posedge)
ready_ff <= ready;
else
ready_ff <= ready_ff;
end
//
// Sample DREQn Line
//
@@ -559,13 +554,10 @@ module KF8237_Timing_And_Control (
reoutput_high_address <= 1'b0;
else if (master_clear)
reoutput_high_address <= 1'b0;
else if (cpu_clock_posedge)
if (state == S2)
reoutput_high_address <= 1'b0;
else if (next_word)
reoutput_high_address <= update_high_address;
else
reoutput_high_address <= reoutput_high_address;
else if (state == S2)
reoutput_high_address <= 1'b0;
else if ((cpu_clock_negedge) && (next_word))
reoutput_high_address <= update_high_address;
else
reoutput_high_address <= reoutput_high_address;
end
@@ -574,32 +566,19 @@ module KF8237_Timing_And_Control (
// Terminal Count Signal
//
always_ff @(posedge clock, posedge reset) begin
if (reset) begin
if (reset)
terminal_count <= 1'b0;
terminal_count_internal <= 1'b0;
end
else if (master_clear) begin
else if (master_clear)
terminal_count <= 1'b0;
terminal_count_internal <= 1'b0;
end
else if (cpu_clock_posedge) begin
if (state == S4) begin
else if (cpu_clock_posedge)
if (state == S4)
terminal_count <= 1'b0;
terminal_count_internal <= 1'b0;
end
else if (next_word) begin
else if (next_s4)
terminal_count <= underflow;
terminal_count_internal <= underflow;
end
else begin
else
terminal_count <= terminal_count;
terminal_count_internal <= terminal_count_internal;
end
end
else begin
else
terminal_count <= terminal_count;
terminal_count_internal <= terminal_count_internal;
end
end
assign end_of_process_n_out = ~terminal_count;
@@ -630,7 +609,7 @@ module KF8237_Timing_And_Control (
end_of_process_internal <= 1'b0;
else if (cpu_clock_negedge)
if (next_state == S4)
end_of_process_internal <= terminal_count_internal | external_end_of_process;
end_of_process_internal <= terminal_count | external_end_of_process;
else
end_of_process_internal <= 1'b0;
else