mirror of
https://github.com/MiSTer-devel/PCXT_MiSTer.git
synced 2026-05-24 03:04:19 +00:00
Added DSS/Covox support
This commit is contained in:
Aitor Gómez
34
PCXT.sv
34
PCXT.sv
@@ -186,7 +186,6 @@ assign VGA_SCALER = 0;
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assign HDMI_FREEZE = 0;
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assign AUDIO_S = 1;
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assign AUDIO_L = AUDIO_R;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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@@ -209,6 +208,7 @@ localparam CONF_STR = {
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"O3,Model,IBM PCXT,Tandy 1000;",
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"-;",
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"OA,Adlib,On,Invisible;",
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"OE,DSS/Covox,Unplugged,Plugged;",
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//"O4,CPU Speed,4.77Mhz,7.16Mhz;",
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"OB,Lo-tech 2MB EMS, Enabled, Disabled;",
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"OCD,EMS Frame,A000,C000,D000;",
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@@ -354,6 +354,18 @@ wire ce_pix;
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assign CLK_VIDEO = clk_28_636;
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assign CE_PIXEL = 1'b1;
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reg cen_44100;
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reg [31:0] cen_44100_cnt;
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wire [31:0] cen_44100_cnt_next = cen_44100_cnt + 16'd44100;
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always @(posedge CLK_50M) begin
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cen_44100 <= 0;
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cen_44100_cnt <= cen_44100_cnt_next;
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if (cen_44100_cnt_next >= (50000000)) begin
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cen_44100 <= 1;
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cen_44100_cnt <= cen_44100_cnt_next - (50000000);
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end
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end
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always @(posedge clk_28_636)
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clk_14_318 <= ~clk_14_318; // 14.318Mhz
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@@ -622,17 +634,18 @@ end
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.ps2_data (device_data),
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.ps2_clock_out (ps2_kbd_clk_out),
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.ps2_data_out (ps2_kbd_data_out),
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.clk_en_44100 (cen_44100),
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.dss_covox_en (status[14]),
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.lclamp (AUDIO_L),
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.rclamp (AUDIO_R),
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.clk_en_opl2 (cen_opl2), // clk_en_opl2
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.jtopl2_snd_e (jtopl2_snd_e),
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.adlibhide (adlibhide),
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.tandy_video (tandy_mode),
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.tandy_snd_e (tandy_snd_e),
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.ioctl_download (ioctl_download),
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.ioctl_index (ioctl_index),
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.ioctl_wr (ioctl_wr),
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.ioctl_addr (ioctl_addr),
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.ioctl_data (ioctl_data),
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.ioctl_data (ioctl_data),
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.clk_uart (clk_uart),
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.uart_rx (uart_rx),
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.uart_tx (uart_tx),
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@@ -659,23 +672,14 @@ end
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.ems_address (status[13:12]),
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.tandy_mode (tandy_mode)
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);
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wire speaker_out;
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wire [7:0] tandy_snd_e;
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wire tandy_snd_rdy;
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wire [15:0] jtopl2_snd_e;
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wire [16:0]sndmix = (({jtopl2_snd_e[15], jtopl2_snd_e}) << 2) + (speaker_out << 15) + {tandy_snd_e, 6'd0}; // signed mixer
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wire [15:0] SDRAM_DQ_IN;
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wire [15:0] SDRAM_DQ_OUT;
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wire SDRAM_DQ_IO;
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assign SDRAM_DQ_IN = SDRAM_DQ;
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assign SDRAM_DQ = ~SDRAM_DQ_IO ? SDRAM_DQ_OUT : 16'hZZZZ;
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assign AUDIO_R = sndmix >> 1;
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wire s6_3_mux;
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wire [2:0] SEGMENT;
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@@ -74,14 +74,16 @@ module CHIPSET (
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input logic ps2_data,
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output logic ps2_clock_out,
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output logic ps2_data_out,
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// SOUND
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input logic clk_en_44100, // COVOX/DSS clock enable
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input logic dss_covox_en,
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output logic [15:0] lclamp,
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output logic [15:0] rclamp,
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// JTOPL
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input logic clk_en_opl2,
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output logic [15:0] jtopl2_snd_e,
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input logic adlibhide,
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// TANDY
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input logic tandy_video,
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output logic [7:0] tandy_snd_e,
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// IOCTL
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input logic ioctl_download,
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input logic [7:0] ioctl_index,
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@@ -265,10 +267,12 @@ module CHIPSET (
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.ps2_data (ps2_data),
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.ps2_clock_out (ps2_clock_out),
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.ps2_data_out (ps2_data_out),
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.clk_en_44100 (clk_en_44100),
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.dss_covox_en (dss_covox_en),
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.lclamp (lclamp),
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.rclamp (rclamp),
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.clk_en_opl2 (clk_en_opl2),
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.jtopl2_snd_e (jtopl2_snd_e),
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.adlibhide (adlibhide),
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.tandy_snd_e (tandy_snd_e),
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.tandy_video (tandy_video),
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.tandy_snd_rdy (tandy_snd_rdy),
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.ioctl_download (ioctl_download),
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@@ -7,7 +7,7 @@ module PERIPHERALS #(
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) (
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input logic clock,
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input logic clk_sys,
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input logic peripheral_clock,
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input logic peripheral_clock,
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input logic reset,
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// CPU
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output logic interrupt_to_cpu,
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@@ -56,13 +56,16 @@ module PERIPHERALS #(
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input logic ps2_data,
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output logic ps2_clock_out,
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output logic ps2_data_out,
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// SOUND
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input logic clk_en_44100, // COVOX/DSS clock enable
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input logic dss_covox_en,
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output logic [15:0] lclamp,
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output logic [15:0] rclamp,
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// JTOPL
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input logic clk_en_opl2,
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output logic [15:0] jtopl2_snd_e,
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input logic clk_en_opl2,
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input logic adlibhide,
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// TANDY
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input logic tandy_video,
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output logic [7:0] tandy_snd_e,
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input logic tandy_video,
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output logic tandy_snd_rdy,
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// IOCTL
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input logic ioctl_download,
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@@ -131,6 +134,7 @@ module PERIPHERALS #(
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wire xtide_select_n = ~(~iorq && ~address_enable_n && address[19:14] == 6'b111011); // EC000 - EFFFF (16 KB)
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wire uart_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h03F8);
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wire lpt_cs = (iorq && ~address_enable_n && {address[15:3], 3'd0} == 16'h0378);
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wire lpt_ctl_cs = (iorq && ~address_enable_n && {address[15:3], 3'd0} == 16'h0379);
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wire [3:0] ems_page_address = (ems_address == 2'b00) ? 4'b1010 : (ems_address == 2'b01) ? 4'b1100 : 4'b1101;
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@@ -330,8 +334,9 @@ module PERIPHERALS #(
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end
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wire [15:0] jtopl2_snd_e;
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wire [7:0] jtopl2_dout;
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wire [7:0]opl32_data;
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wire [7:0] opl32_data;
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assign opl32_data = adlibhide ? 8'hFF : jtopl2_dout;
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jtopl2 jtopl2_inst
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@@ -351,6 +356,7 @@ module PERIPHERALS #(
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// Tandy sound
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wire [7:0] tandy_snd_e;
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sn76489_top sn76489
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(
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.clock_i(clock),
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@@ -361,7 +367,26 @@ module PERIPHERALS #(
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.ready_o(tandy_snd_rdy),
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.d_i(internal_data_bus),
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.aout_o(tandy_snd_e)
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);
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);
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wire dss_full;
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soundwave sound_gen
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(
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.CLK(clock),
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.clk_en(clk_en_44100),
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.data(internal_data_bus),
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.we(dss_covox_en && lpt_cs && ~io_write_n),
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// .word(WORD),
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.speaker(speaker_out),
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.tandy_snd(tandy_snd_e),
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.opl2left(jtopl2_snd_e),
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.opl2right(jtopl2_snd_e),
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// .full(sq_full), // when not full, write max 2x1152 16bit samples
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.dss_full(dss_full),
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.lclamp(lclamp),
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.rclamp(rclamp)
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);
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logic keybord_interrupt_ff;
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always_ff @(posedge clock, posedge reset) begin
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@@ -724,6 +749,10 @@ module PERIPHERALS #(
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data_bus_out_from_chipset = 1'b1;
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data_bus_out = lpt_data;
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end
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else if ((lpt_ctl_cs) && (~io_read_n)) begin
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data_bus_out_from_chipset = 1'b1;
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data_bus_out = {1'bx, dss_full, 6'bxxxxxx};
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end
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else begin
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data_bus_out_from_chipset = 1'b0;
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data_bus_out = 8'b00000000;
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@@ -1,3 +1,5 @@
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ram.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) clk_div3.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) bios.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) bios.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) soundwave.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sndfifo.v ]
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172
rtl/common/sndfifo.v
Normal file
172
rtl/common/sndfifo.v
Normal file
@@ -0,0 +1,172 @@
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: dcfifo
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// ============================================================
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// File Name: sndfifo.v
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// Megafunction Name(s):
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// dcfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus Prime License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module sndfifo (
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data,
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rdclk,
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rdreq,
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wrclk,
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wrreq,
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q,
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rdempty,
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rdusedw,
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wrusedw);
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input [31:0] data;
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input rdclk;
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input rdreq;
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input wrclk;
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input wrreq;
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output [31:0] q;
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output rdempty;
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output [11:0] rdusedw;
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output [11:0] wrusedw;
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wire [31:0] sub_wire0;
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wire sub_wire1;
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wire [11:0] sub_wire2;
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wire [11:0] sub_wire3;
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wire [31:0] q = sub_wire0[31:0];
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wire rdempty = sub_wire1;
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wire [11:0] rdusedw = sub_wire2[11:0];
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wire [11:0] wrusedw = sub_wire3[11:0];
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dcfifo dcfifo_component (
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.data (data),
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.rdclk (rdclk),
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.rdreq (rdreq),
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.wrclk (wrclk),
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.wrreq (wrreq),
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.q (sub_wire0),
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.rdempty (sub_wire1),
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.rdusedw (sub_wire2),
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.wrusedw (sub_wire3),
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.aclr (),
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.eccstatus (),
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.rdfull (),
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.wrempty (),
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.wrfull ());
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defparam
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dcfifo_component.intended_device_family = "Cyclone IV E",
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dcfifo_component.lpm_numwords = 4096,
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dcfifo_component.lpm_showahead = "OFF",
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dcfifo_component.lpm_type = "dcfifo",
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dcfifo_component.lpm_width = 32,
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dcfifo_component.lpm_widthu = 12,
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dcfifo_component.overflow_checking = "ON",
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dcfifo_component.rdsync_delaypipe = 4,
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dcfifo_component.underflow_checking = "ON",
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dcfifo_component.use_eab = "ON",
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dcfifo_component.wrsync_delaypipe = 4;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "4"
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// Retrieval info: PRIVATE: Depth NUMERIC "4096"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "0"
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||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "32"
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||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
|
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL "rdusedw[11..0]"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL "wrusedw[11..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL sndfifo_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
119
rtl/common/soundwave.v
Normal file
119
rtl/common/soundwave.v
Normal file
@@ -0,0 +1,119 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file is part of the Next186 Soc PC project
|
||||
// http://opencores.org/project,next186
|
||||
//
|
||||
// Filename: sound_gen.v
|
||||
// Description: Part of the Next186 SoC PC project,
|
||||
// stereo 2x16bit pulse density modulated sound generator
|
||||
// 44100 samples/sec
|
||||
// Disney Sound Source and Covox Speech compatible
|
||||
// Version 1.0
|
||||
// Creation date: Jan2015
|
||||
//
|
||||
// Author: Nicolae Dumitrache
|
||||
// e-mail: ndumitrache@opencores.org
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2015 Nicolae Dumitrache
|
||||
//
|
||||
// This source file may be used and distributed without
|
||||
// restriction provided that this copyright statement is not
|
||||
// removed from the file and that any derivative work contains
|
||||
// the original copyright notice and the associated disclaimer.
|
||||
//
|
||||
// This source file is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU Lesser General
|
||||
// Public License as published by the Free Software Foundation;
|
||||
// either version 2.1 of the License, or (at your option) any
|
||||
// later version.
|
||||
//
|
||||
// This source is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. See the GNU Lesser General Public License for more
|
||||
// details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General
|
||||
// Public License along with this source; if not, download it
|
||||
// from http://www.opencores.org/lgpl.shtml
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Additional Comments:
|
||||
//
|
||||
// byte write: both channels are the same (Covox emulation), the 8bit sample value is shifted by 8, the channel selector is reset to LEFT
|
||||
// word write: LEFT first, the queue is updated only after RIGHT value is written
|
||||
// sample rate: 44100Hz
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`define SPKVOL 11
|
||||
|
||||
module soundwave(
|
||||
input CLK,
|
||||
input clk_en,
|
||||
// input [15:0]data,
|
||||
input [7:0]data,
|
||||
input we,
|
||||
// input word,
|
||||
input speaker,
|
||||
input [15:0]opl2left,
|
||||
input [15:0]opl2right,
|
||||
input [7:0]tandy_snd,
|
||||
output full, // when not full, write max 2x1152 16bit samples
|
||||
output dss_full,
|
||||
output [15:0] lclamp,
|
||||
output [15:0] rclamp
|
||||
);
|
||||
|
||||
reg [31:0]wdata;
|
||||
reg lr = 1'b0;
|
||||
reg [2:0]write = 3'b000;
|
||||
wire qempty;
|
||||
wire [31:0]sample;
|
||||
wire [31:0]sample1 = qempty ? 32'hc000c000 : sample;
|
||||
reg [15:0]r_opl2left = 0;
|
||||
reg [15:0]r_opl2right = 0;
|
||||
wire [16:0]lmix = {sample1[15], sample1[15:0]} + {r_opl2left[15], r_opl2left} + {tandy_snd, 6'd0} + (speaker << `SPKVOL); // signed mixer left
|
||||
wire [16:0]rmix = {sample1[31], sample1[31:16]} + {r_opl2right[15], r_opl2right} + {tandy_snd, 6'd0} + (speaker << `SPKVOL); // signed mixer right
|
||||
assign lclamp = (~|lmix[16:15] | &lmix[16:15]) ? {!lmix[15], lmix[14:0]} : {16{!lmix[16]}}; // clamp to [-32768..32767] and add 32878
|
||||
assign rclamp = (~|rmix[16:15] | &rmix[16:15]) ? {!rmix[15], rmix[14:0]} : {16{!rmix[16]}};
|
||||
wire [11:0]wrusedw;
|
||||
wire [11:0]rdusedw;
|
||||
assign full = wrusedw >= 12'd2940;
|
||||
assign dss_full = rdusedw > 12'd90; // Disney sound source queue full
|
||||
|
||||
sndfifo sndfifo_inst
|
||||
(
|
||||
.wrclk(CLK), // input wr_clk
|
||||
.rdclk(CLK), // input rd_clk
|
||||
.data(wdata), // input [31 : 0] din
|
||||
.wrreq(|write), // input wr_en
|
||||
.rdreq(clk_en), // input rd_en
|
||||
.q(sample), // output [31 : 0] dout
|
||||
.wrusedw(wrusedw),
|
||||
.rdusedw(rdusedw),
|
||||
.rdempty(qempty) // output empty
|
||||
);
|
||||
|
||||
always @(posedge CLK) begin
|
||||
r_opl2left <= opl2left;
|
||||
r_opl2right <= opl2right;
|
||||
if(we) begin
|
||||
/*
|
||||
if(word) begin
|
||||
lr <= !lr;
|
||||
write <= {2'b00, lr};
|
||||
if(lr) wdata[31:16] <= data;
|
||||
else wdata[15:0] <= data;
|
||||
end else begin
|
||||
*/
|
||||
lr <= 1'b0; // left
|
||||
write <= 3'b110;
|
||||
wdata <= {1'b1, data[7:0], 8'b00000001, data[7:0], 7'b0000000};
|
||||
end
|
||||
else write <= write - |write;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user