mister-devel/PCFX_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/PCFX_MiSTer.git synced 2026-04-26 03:04:29 +00:00
Code Issues Packages Projects Releases Wiki Activity
77 Commits 3 Branches 0 Tags
bd908cda3cf7e5ab61faeeeb6de141f168d55a4b
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
David Hunter bd908cda3c Fix backup mem. load on real SDRAM 
SDRAM burst reads/writes wrap column adds at the burst length.  And
pcfx_top was illegally doing a 32-bit write at an odd 16-bit boundary.
Thus every other 16-bit word was being written to zero.  This fixes
both the SDRAM burst simulation and the odd address read/write.
2026-01-25 18:01:57 -08:00
releases
Release 20260102
2026-01-02 23:29:06 -08:00
rtl
Fix backup mem. load on real SDRAM
2026-01-25 18:01:57 -08:00
sys
Copy Template_MiSTer
2025-11-22 14:26:51 -08:00
test-rom
Pick up v810 update to add instruction cache
2026-01-10 17:08:08 -08:00
.gitignore
Add v810 code as submodule
2025-11-23 15:17:57 -08:00
.gitmodules
Add v810 code as submodule
2025-11-23 15:17:57 -08:00
clean.bat
Copy Template_MiSTer
2025-11-22 14:26:51 -08:00
COPYING
Might as well start calling this the real core
2026-01-02 22:44:45 -08:00
files.qip
Refine FX-BMP implementation
2026-01-24 18:44:06 -08:00
PCFX.qpf
Might as well start calling this the real core
2026-01-02 22:44:45 -08:00
PCFX.qsf
Might as well start calling this the real core
2026-01-02 22:44:45 -08:00
PCFX.sdc
Might as well start calling this the real core
2026-01-02 22:44:45 -08:00
PCFX.srf
Might as well start calling this the real core
2026-01-02 22:44:45 -08:00
PCFX.sv
Correct img_mounted and status_menumask usage
2026-01-22 22:41:41 -08:00
Description
No description provided
3.3 MiB
Languages
Verilog 38.6%
SystemVerilog 33.5%
VHDL 24.6%
Tcl 2.6%
Assembly 0.3%
Other 0.2%