David Hunter 47a4e1969b Appease iverilog 13.0

2026-03-27 21:48:19 -07:00

..

.gitignore

HuC6272 BG video (WIP)

2026-03-08 16:47:49 -07:00

altddio_out.v

Simulate full core with SDRAM memory

2025-11-26 20:18:16 -08:00

as4c32m16sb.sv

Fix backup mem. load on real SDRAM

2026-01-25 18:01:57 -08:00

dpram.sv

Fix dpram read-during-write behavior

2025-12-24 14:47:37 -08:00

huc6272_dut_kram_vce.svh

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

huc6272_render2png.py

HuC6272 BG video (WIP)

2026-03-08 16:47:49 -07:00

huc6272_video_kram_tb.gtkw

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

huc6272_video_kram_tb.sv

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

huc6272_video_render_tb.gtkw

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

huc6272_video_render_tb.sv

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

kpc_tb.gtkw

Might as well start calling this the real core

2026-01-02 22:44:45 -08:00

kpc_tb.sv

FXGA: Implement K-Port controller

2026-01-02 19:00:57 -08:00

pcfx_top_tb-cpu-dev.verilator.gtkw

Might as well start calling this the real core

2026-01-02 22:44:45 -08:00

pcfx_top_tb.cpp

huc6261: Implement 320 dots (7MHz dot clock) mode

2026-01-16 20:53:36 -08:00

pcfx_top_tb.gtkw

Might as well start calling this the real core

2026-01-02 22:44:45 -08:00

pcfx_top_tb.sv

Appease iverilog 13.0

2026-03-27 21:48:19 -07:00

pcfx_top_tb.verilator.gtkw

HuC6272 refactor

2026-03-21 21:20:43 -07:00

pcfx_top.files

Color space conversion

2026-02-14 15:47:33 -08:00

pd424260.sv

HuC6272 CPU KRAM read/write

2026-03-25 22:05:51 -07:00

render2png.py

huc6261: Implement 320 dots (7MHz dot clock) mode

2026-01-16 20:53:36 -08:00

sdram_xsds.sv

Fix SDRAM 8- and 16-bit writes

2025-12-20 22:46:38 -08:00