David Hunter
47a4e1969b
Appease iverilog 13.0
2026-03-27 21:48:19 -07:00
David Hunter
4e33b7bbac
HuC6272 CPU KRAM read/write
2026-03-25 22:05:51 -07:00
David Hunter
94465f6f12
HuC6272 refactor
...
Move CPU and SCSI into their own modules
2026-03-21 21:20:43 -07:00
David Hunter
9840ace59a
HuC6272 BG video
...
Use microprogram to drive fetch
2026-03-15 21:53:42 -07:00
David Hunter
0ea919738d
HuC6272 BG video
...
Add BG register file
2026-03-15 21:53:37 -07:00
David Hunter
64466cff52
HuC6272 BG video (WIP)
2026-03-08 16:47:49 -07:00
David Hunter
37e72c7adf
Color space conversion
2026-02-14 15:47:33 -08:00
David Hunter
c3c9430da9
New OSD feature: load FX-BMP ROM
...
This is a shortcut for mounting an .FXB as FX-BMP backup RAM and then
loading it. Additionally, the "Save backup RAM" option cannot save
over it.
2026-02-07 16:57:45 -08:00
David Hunter
b026355e16
Pick up V810 update: MOVBSU (WIP)
2026-02-04 23:11:27 -08:00
David Hunter
1de764e03e
memif_sdram: Clear pending request on reset
...
This was causing the first instruction fetch out of reset to be
skipped, causing the CPU to eventually leap into space and the ERROR
LED[7] to light up.
2026-01-25 23:11:28 -08:00
David Hunter
bd908cda3c
Fix backup mem. load on real SDRAM
...
SDRAM burst reads/writes wrap column adds at the burst length. And
pcfx_top was illegally doing a 32-bit write at an odd 16-bit boundary.
Thus every other 16-bit word was being written to zero. This fixes
both the SDRAM burst simulation and the odd address read/write.
2026-01-25 18:01:57 -08:00
David Hunter
fe0ccdcf5e
Verify SRAM/BMP load
2026-01-25 16:34:54 -08:00
David Hunter
6f6d075d8a
Refine FX-BMP implementation
...
- Add battery status readout
- Narrow address range to E800_0000 .. EBFF_FFFF
- Enable BMP only if it's mounted
- Configure BMP size according to mounted image size
2026-01-24 18:44:06 -08:00
David Hunter
554b19a237
Correct img_mounted and status_menumask usage
2026-01-22 22:41:41 -08:00
David Hunter
093579c1b6
Enable saving both backup SRAMs to SD
2026-01-19 15:42:14 -08:00
David Hunter
7bc6250385
Implement BMP (external SRAM), and hook it up to SD loader
2026-01-19 13:51:21 -08:00
David Hunter
8fc354d5d7
Hook internal backup SRAM up to the SD block device interface
2026-01-19 01:54:33 -08:00
David Hunter
01018f429a
Pick up V810 update: DIVU (unsigned) and DIV (signed)
2026-01-17 22:46:12 -08:00
David Hunter
cd529be82d
Use USER LED to indicate fatal error
...
Error is currently defined as:
- Invalid Instruction Exception (read 0xFFFF_FF90)
- Duplexed Exception (read 0xFFFF_FFD0)
2026-01-16 23:13:50 -08:00
David Hunter
e7d8876e76
huc6261: Implement 320 dots (7MHz dot clock) mode
2026-01-16 20:53:36 -08:00
David Hunter
48bf9f80cd
Get internal SRAM working
2026-01-15 23:32:21 -08:00
David Hunter
fa0e45c92a
Add 4 I/O wait states; fix HuC6270 BUSY_N and CPU_CE use
...
HuC6270 signals are now more closely aligned with how huc6280.vhd uses
them.
This fixes a freeze on entering the backup memory screen.
2026-01-14 00:45:40 -08:00
David Hunter
01cae25670
Merge branch 'dev2' into dev
2026-01-10 22:30:49 -08:00
David Hunter
b9c1ec33ad
Add internal SRAM (WIP)
2026-01-10 19:12:17 -08:00
David Hunter
7c688af179
v810_tag/dataram: Drop the manual Megafunction instantiations
2026-01-10 17:08:08 -08:00
David Hunter
c9d050b1b2
Pick up v810 update to add instruction cache
2026-01-10 17:08:08 -08:00
David Hunter
db75b26824
Might as well start calling this the real core
...
Test_V810 -> PCFX
mycore -> pcfx_top
2026-01-02 22:44:45 -08:00
David Hunter
de32e9bb4e
Add virtual K-Port joypads
2026-01-02 21:40:29 -08:00
David Hunter
ee24ce9cc1
FXGA: Implement K-Port controller
2026-01-02 19:00:57 -08:00
David Hunter
aace72f0db
huc6270: Fix some sprites not rendered
2025-12-31 00:19:00 -08:00
David Hunter
ba46cd758c
Fix multiple instabilities due to unplanned CDC
...
Switch CPU and sys clocks over to a PLL 50 MHz output
2025-12-30 22:54:44 -08:00
David Hunter
01281bfd15
HuC6261: Add color palette RAM, sync gen, and VDC out mixer
2025-12-29 20:14:30 -08:00
David Hunter
dd9c652112
Double VRAM to 128KB
2025-12-26 23:22:42 -08:00
David Hunter
e91ea9e5b5
Add the SCSI controller and a fake CD drive
2025-12-26 16:19:59 -08:00
David Hunter
770ee2f7bf
Fix dpram read-during-write behavior
2025-12-24 14:47:37 -08:00
David Hunter
c3fb721a5f
Appease Verilator
2025-12-24 11:08:00 -08:00
David Hunter
71a6401d72
Integrate the real HuC6270 from TurboGrafx16_MiSTer
...
- Translate huc6270 from VHDL to SystemVerilog
- Display each VDC's output as a bit-reversed color channel
2025-12-24 00:05:38 -08:00
David Hunter
72be3244f3
Pick up v810 update
2025-12-21 17:46:46 -08:00
David Hunter
dac69366d4
Fix SDRAM 8- and 16-bit writes
...
SDRAM pins DQMH/L and A[12:11] are shorted on the SDRAM board.
Top-level FPGA pins SDRAM_DQMH/L don't actually go to the SDRAM board.
2025-12-20 22:46:38 -08:00
David Hunter
068cdf37df
Add a fake Gate Array and HuC6270
...
Implements just enough registers in each IP to get VBlank interrupts working.
2025-12-15 22:34:41 -08:00
David Hunter
45157b2623
Pick up v810 update
2025-11-30 20:28:03 -08:00
David Hunter
78d49e7f73
Add a fake HuC6121 w/ raster counter
2025-11-29 20:27:20 -08:00
David Hunter
3817eb96c5
Use SDRAM to store 2MB RAM
2025-11-27 21:29:08 -08:00
David Hunter
91d46f49bd
Simulate full core with SDRAM memory
2025-11-26 20:18:16 -08:00
