166 Commits

Author SHA1 Message Date
Marc Roy
77f2bfe54d Merge pull request #66 from wwark/master
Update sys + New Release
2026-04-16 12:45:41 +02:00
Marc Roy
e9df9534b5 Update sys + New Release 2026-04-16 12:44:30 +02:00
Marc Roy
8b06c65817 Merge pull request #63 from yosinda/hotfix-14
Workarounds for disk subsystem
2026-03-21 07:55:27 +01:00
yosinda
3852e1bc82 Workaround for FDC_READY
Assert FDC READY only when USEL=00 or 01.
2026-03-20 19:01:52 +09:00
yosinda
a6efbbebe6 Remove the signal mask when the FDD is empty
Instead of masking the data signal when there is no disk, the transfer start flag is not asserted.
2026-03-20 19:01:52 +09:00
yosinda
2f780234a4 Workaround for when sector size is 0
If 0 is specified for the sector size, it will be treated as 128 bytes.
2026-03-20 19:01:52 +09:00
Marc Roy
0f8e89b30b Merge pull request #59 from yosinda/hotfix-13
Minor improvements to disk and sound
2026-03-14 14:01:28 +01:00
yosinda
e68664e15a Always assert the FDC's READY pin
In actual hardware, the READY pin is clipped, so it's always active.

This resolves the issue where the disk on drive 2 is not recognized if drive 2 is empty at startup.
Note that, compared to before the change, it takes longer for the "How many files" to be displayed when drive 1 is empty.
This is the same behavior as in actual hardware.
2026-03-14 12:09:04 +09:00
yosinda
e594710d0a Ignore invalid offset addresses in D88 images
The header of a D88 image file defines the offset address where each track data is stored.
If an offset address exceeding the size of the image file is set, it is stored in the table as offset=0 (unformatted).
2026-03-13 21:51:14 +09:00
yosinda
85f75ad3c3 Change the track length to 8000 in extension mode. 2026-03-13 17:11:17 +09:00
yosinda
6e71494f69 Supports booting from CDOS2 2HD disk images
The disk image reading process improves the handling of tracks containing a mix of FM and MFM sectors.
2026-03-13 14:19:03 +09:00
yosinda
e60a99a6d6 Change the definition to match the extended bit width of the SSG output 2026-03-07 02:22:04 +09:00
yosinda
ff01d2e9a6 [JT12] Change the definition to match the extended bit width of the SSG output 2026-03-07 02:21:23 +09:00
yosinda
fc509225ce [JT49] Expand SSG volume level LUT to 10bit
The resolution of the volume LUT is expanded to 10 bits, and the accumulator and mix output are also expanded to 12 bits.
2026-03-07 02:19:05 +09:00
yosinda
65553194e6 [JT08] Improvements ADPCM-B linear interpolation
The linear interpolation step value is now applied immediately on the next cen55 cycle after updating the PCM sample.
2026-03-06 01:56:41 +09:00
yosinda
84f8d5223f [JT12] Fix ADPCM-B step calculation
The ADPCM-B accumulator is calculated in 16-bit signed format.
Not only the final output PCM value, but also the step value must be capped at 16-bit signed.
2026-03-05 20:44:56 +09:00
Marc Roy
10fa0084ec Merge pull request #58 from jackyangantelope/update-sys
modify frame
2025-12-08 07:09:40 +01:00
jackyangantelope
2aaf3d9c12 modify frame 2025-12-04 16:21:01 +08:00
Marc Roy
0bfc9b9ae8 Merge pull request #56 from wwark/master
Update SYS + New Release
2025-09-18 22:57:37 +02:00
Marc Roy
370a58ebb9 Update SYS + New Release
Fix warning sramdefault.hex not found
2025-09-18 22:31:03 +02:00
Marc Roy
efa02723f0 Merge pull request #51 from yosinda/hotfix-12
Fix CRTC attibute and palette behavior
2025-04-07 17:44:29 +02:00
yosinda
68536ffa60 Fix the digital palette behavior
Palette mode has been added to the conditions for determining whether palette colors are valid.

Adding a DMA stop with digital palette and B&W graphics mode settings means that the bits on the graphics plane are no longer colored with the palette colors.
This behavior differs from that of analog palette mode.
2025-04-07 21:42:34 +09:00
yosinda
0c54bb59d2 Modify the attribute "Column address" (CRTC)
According to the specification, the "Column address" is 7 bits, and valid values ​​are from 0x00 to 0x4F.
Previously, values ​​0x50 and above were treated as 0, but now they are ignored as invalid values.
0x80 is still treated the same as 0x00 because "Column address" ignore the 8th bit.

Note:
0x60 means "special control code", but is still not supported.
So it is ignored as an invalid value.
2025-04-07 18:43:22 +09:00
Marc Roy
6cdf4c4346 Merge pull request #48 from yosinda/hotfix-11
Fix interrupt and timer behavior
2025-04-06 18:12:18 +02:00
yosinda
5bf5a2c17f Fixes the interval of the 1/600s timer 2025-04-06 23:55:53 +09:00
yosinda
c139127e73 Modify the behavior of multiple interrupts (INTC)
In the uPD8214, "interrupt disable flip-flop" is set at the same time as INT is asserted, and the next INT is not asserted until it is reset.
INTC has been modified to comply with this specification.

This fixes an issue where the CPU was interrupted even though the interrupt handler implementation did not expect multiple interrupts.
2025-04-06 23:34:31 +09:00
Marc Roy
a684523116 Merge pull request #47 from yosinda/fix-jt08-2
Fix volume balances and improve ADPCM sound
2025-04-06 09:31:19 +02:00
yosinda
0a54df3b0a Changes volume balance for ADPCM-A
In ADPCM-A,
- Change the gain formula to old MAME based
- Remove linear interpolation

Fork and replace jt10_adpcm_gain/acc with jt08_adpcm_gain/acc.
In jt08_acc, the ADPCM-A volume correction is removed.
2025-03-25 12:11:56 +09:00
yosinda
38b95b69b4 Corrects SSG volume balance on the core 2025-03-22 23:53:32 +09:00
yosinda
a4714fc592 Change JT49 COMP parameter
- Allow JT49 COMP parameter to be set from JT12 wrapper.
- For JT03 and JT08, set JT49_COMP parameter to 0.

According to the YM2608 application manual, the characteristics of the analog output pins are measured with a load resistance (Rload) of 470 ohms.
I think the default setting for JT49_COMP should be 0 (Rload < 1000ohm).
2025-03-22 21:41:46 +09:00
yosinda
337bd61e8a Fix SSG output level
According to the YM2608 application manual, the SSG output level has the following specifications:

- The lowest 4 bits of registers $08-$0a are mapped to the highest 4 bits of the DAC's 5-bit resolution. The DAC's LSB is '1'.
- DAC output levels of 0 and 1 have the same output value.

Actual measurement of the output value showed that when the DAC output level is 0, the output value is 0.
-> https://d4.princess.ne.jp/msx/psg/
2025-03-22 21:32:16 +09:00
yosinda
ca5303d140 Adds linear interpolation support to ADPCM
Adds a linear interpolation method with an interpolation factor (Delta-n).
Change this module to be included in the build.
2025-03-09 14:30:29 +09:00
Marc Roy
28bf1c88c6 Merge pull request #46 from yosinda/hotfix-10
Change the aspect ratio in normal mode
2025-03-01 09:49:04 +01:00
yosinda
bc9649c87f Change the aspect ratio in normal mode
Actual PC8801 series "high resolution" 24kHz CRT monitors display images with a maximum of 640x400 square dots, just like the PC9801 series.
The correct aspect ratio is 16:10, and the current 4:3 does not display images correctly in normal mode.
Change the definition of aspect ratio in PC8801.sv.

Note:
In 640x200 mode, the even lines in 400 line mode are simply hidden, so the aspect ratio remains the same.
2025-03-01 16:24:28 +09:00
Marc Roy
554a875b0c Merge pull request #45 from yosinda/fix-fdc-2
Fix FDC result status and some behavior
2025-02-25 15:56:26 +01:00
yosinda
1d4de0f7ad Fix EOT behavior (FDC)
- When R == EOT, reset R=1 and change C/H depending on MT.
- When R != EOT, add 1 to R.

The software emulator is implemented with these conditions.
I have verified that this condition does not violate the specification.
2025-02-25 20:52:16 +09:00
yosinda
50e699b4ec Fix an issue where a command may be aborted while reading data.
If an IAM is detected a second time while reading data, the command will terminate incorrectly.
This is an unexpected behavior on the host side, so fix the issue.

As with READ DIAG, the IAM counter is reset before reading the sector data.
2025-02-24 18:04:00 +09:00
yosinda
6a278b6391 Improve index mark detection in FM decoders
Change the detection condition to SYNC 1 byte + AM 1 byte.
Widening the check range will prevent false detection.
2025-02-24 13:49:12 +09:00
yosinda
752d321983 Fix behavior when detecting index marks
The condition for aborting the command is modified to detect the index mark twice.
In the case of the READ DIAG command, the detection of the index mark is waited for first, and the counter is reset after the sector is detected.
2025-02-24 13:31:14 +09:00
yosinda
4507f70846 Fix FDC result
- Treat ID AM detection as sector detection (DETSECT=1).
- If sector not found, only sMA=1 is returned.
- In the case of "READ DELETED DATA", sCM returns DAM detection.
- If there is an ID CRC error with the "READ ID" command, search for the next sector.
2025-02-24 11:48:45 +09:00
Marc Roy
9b851f31dd Merge pull request #44 from yosinda/fix-fdc
Fix FDC behavior in irregular cases
2025-02-22 20:24:09 +01:00
yosinda
2d59620b44 Fix WRITE_DATA behavior (FDC)
- Change to skip the GAP2 field instead of overwriting it
- Change the start of writing from GAP2 to SYNC
- After writing, change the GAP3 field to write only one byte.

At the same time, the behavior of the disk emulator will be changed.
- The start of write operations will be unified to SYNC.
  The GAP generation function will be removed from mkgapsync.
2025-02-23 02:50:57 +09:00
yosinda
edb2fe0220 fix WRITE ID behavior (FDC)
WRITE ID command should use the value of the 'N' parameter for the data length instead of the 'N' value of the ID field.
2025-02-23 02:50:57 +09:00
yosinda
e760f23632 Fix how to load unformatted tracks
When a track is unformatted in loading D88 image, the disk emulator fills the buffer for the track with 0xFF.
2025-02-23 02:50:57 +09:00
yosinda
dd0cab503e Fix TC=1 and OR=1 behavior
When TC=1 or OR=1 in READ DATA/WRITE DATA/WRITE ID,
- The current operation of one sector or one track continues until completion.
- No access request INT or DMA is issued.
2025-02-23 02:50:57 +09:00
yosinda
3d47ad80e8 fix e8255 behavior
The PPI (8255) switches output with a delay from the rising edge of WR_n.
2025-02-23 02:50:57 +09:00
Marc Roy
bb152c9237 Merge pull request #43 from yosinda/hotfix-9
Fix CRTC attribute change limits
2025-02-16 10:04:07 +01:00
yosinda
c67891a370 Fix CRTC attribute change limits
The CRTC supports up to 20 attribute changes, but only 19 were allowed.
Fixes upper limit check.
2025-02-16 17:38:50 +09:00
Marc Roy
502f31bf63 Merge pull request #40 from yosinda/hotfix-8
Import the FDC fix from Zet98 core
2025-01-26 11:41:00 +01:00
yosinda
0d6d6f64e9 Fix the FDC issue when WRITEDATA with MT=1
This is the same problem that Puu-san encountered while developing Zet98,
so we'll import the fix from that version.

http://fpga8801.seesaa.net/article/479349706.html
2025-01-26 16:06:28 +09:00