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CD: Add VBlank IRQ mask

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paulb-nl
2023-06-28 13:20:54 +02:00
parent a86546fa87
commit ff3e8e0a71
4 changed files with 14 additions and 4 deletions
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3
neogeo.sv
View File

@@ -791,6 +791,7 @@ wire CD_USE_SPR, CD_USE_FIX, CD_USE_Z80;
wire CD_UPLOAD_EN;
wire CD_BANK_PCM;
wire CD_IRQ;
wire CD_VBLANK_IRQ_EN;
wire DMA_RUNNING, DMA_WR_OUT, DMA_RD_OUT;
wire [15:0] DMA_DATA_OUT;
wire [23:0] DMA_ADDR_IN;
@@ -901,6 +902,7 @@ cd_sys cdsystem(
.CD_TR_WR_DATA(CD_TR_WR_DATA), .CD_TR_WR_ADDR(CD_TR_WR_ADDR),
.CD_UPLOAD_EN(CD_UPLOAD_EN),
.CD_IRQ(CD_IRQ), .IACK(IACK),
.CD_VBLANK_IRQ_EN(CD_VBLANK_IRQ_EN),
.CDD_STATUS_IN(CDD_STATUS), .CDD_STATUS_LATCH(CDD_STATUS_LATCH),
.CDD_COMMAND_DATA(CDD_COMMAND_DATA), .CDD_COMMAND_SEND(CDD_COMMAND_SEND),
.CD_DATA_DOWNLOAD(CD_DATA_DOWNLOAD), .CD_DATA_WR(CD_DATA_WR),
@@ -1960,6 +1962,7 @@ lspc2_a2 LSPC(
.FVRAM_DATA_IN(FAST_VRAM_DATA_IN), .FVRAM_DATA_OUT(FAST_VRAM_DATA_OUT),
.CWE(CWE),
.VMODE(video_mode),
.CD_VBLANK_IRQ_EN(CD_VBLANK_IRQ_EN | ~SYSTEM_CDx),
.FIXMAP_ADDR(FIXMAP_ADDR) // Extracted for NEO-CMC
);

4
rtl/cd/cd.sv
View File

@@ -55,6 +55,8 @@ module cd_sys(
output reg [19:1] CD_TR_WR_ADDR,
output reg CD_UPLOAD_EN, // The bios writes to Z80 RAM without CD_UPLOAD_EN enabled. Maybe this is only watchdog disable?
output CD_VBLANK_IRQ_EN,
input IACK,
output reg CD_IRQ,
@@ -790,6 +792,8 @@ module cd_sys(
end
endfunction
assign CD_VBLANK_IRQ_EN = &{REG_FF0004[5:4]};
assign M68K_DATA = (SYSTEM_CDx & ~nAS & M68K_RW & IACK) ? {8'h00, CD_IRQ_VECTOR} : // Vectored interrupt handler
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h004) ? {4'h0, REG_FF0004} :
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h11C) ? {3'b110, CD_LID, CD_JUMPERS, 8'h00} : // Top mech

5
rtl/video/irq.v
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@@ -19,7 +19,8 @@ module irq(
input [2:0] ACK_BITS,
input RESET_IRQ,
input TIMER_IRQ,
input VBL_IRQ,
input VBL_IRQ,
input CD_VBL_EN,
input CLK,
output IPL0, IPL1
);
@@ -36,7 +37,7 @@ module irq(
wire B56_Q, B56_nQ, B52_Q, B52_nQ, C52_Q;
FD3 B56(RESET_IRQ, 1'b0, ACK[0], B56_Q, B56_nQ);
FD3 B52(TIMER_IRQ, 1'b0, ACK[1], B52_Q, B52_nQ);
FD3 C52(VBL_IRQ, 1'b0, ACK[2], C52_Q);
FD3 C52(VBL_IRQ, ~CD_VBL_EN, ACK[2], C52_Q);
// B49
wire B49_OUT = B52_Q | B56_nQ;

6
rtl/video/lspc2_a2.v
View File

@@ -65,7 +65,9 @@ module lspc2_a2(
output nPBUS_OUT_EN,
input VMODE,
input CD_VBLANK_IRQ_EN,
output [14:0] FIXMAP_ADDR // Extracted for NEO-CMC
);
@@ -589,7 +591,7 @@ module lspc2_a2(
resetp RSTP(CLK_24MB, RESET, nRESETP);
wire BNK;
irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, LSPC_6M, IPL0, IPL1);
irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, CD_VBLANK_IRQ_EN, LSPC_6M, IPL0, IPL1);
wire Q53_CO, FLIP, P50_CO;
videosync VS(CLK_24MB, LSPC_3M, LSPC_1_5M, Q53_CO, nRESETP, VMODE, PIXELC, RASTERC, HSYNC, VSYNC, BNK,