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CD: SPR & FIX readable by CPU

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This commit is contained in:
paulb-nl
2023-02-21 14:20:01 +01:00
parent 3bd322ac60
commit 4e26636c72
3 changed files with 106 additions and 67 deletions
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27
neogeo.sv
View File

@@ -784,6 +784,8 @@ wire [19:1] CD_TR_WR_ADDR;
wire [1:0] CD_BANK_SPR;
wire CD_TR_WR_SPR, CD_TR_WR_PCM, CD_TR_WR_Z80, CD_TR_WR_FIX;
wire CD_TR_RD_SPR, CD_TR_RD_FIX;
wire CD_USE_SPR, CD_USE_FIX;
wire CD_UPLOAD_EN;
wire CD_BANK_PCM;
wire CD_IRQ;
@@ -867,6 +869,8 @@ cd_sys cdsystem(
.CD_nRESET_Z80(CD_nRESET_Z80),
.CD_TR_WR_SPR(CD_TR_WR_SPR), .CD_TR_WR_PCM(CD_TR_WR_PCM),
.CD_TR_WR_Z80(CD_TR_WR_Z80), .CD_TR_WR_FIX(CD_TR_WR_FIX),
.CD_TR_RD_FIX(CD_TR_RD_FIX), .CD_TR_RD_SPR(CD_TR_RD_SPR),
.CD_USE_FIX(CD_USE_FIX), .CD_USE_SPR(CD_USE_SPR),
.CD_TR_AREA(CD_TR_AREA),
.CD_BANK_SPR(CD_BANK_SPR), .CD_BANK_PCM(CD_BANK_PCM),
.CD_TR_WR_DATA(CD_TR_WR_DATA), .CD_TR_WR_ADDR(CD_TR_WR_ADDR),
@@ -888,7 +892,7 @@ cd_sys cdsystem(
// The P1 zone is writable on the Neo CD
// Is there a write enable register for it ?
wire CD_EXT_WR = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_OUT[23:21] == 3'd0) & DMA_WR_OUT) : // DMA writes to $000000~$1FFFFF
(SYSTEM_CDx & ~|{A23Z, A22Z, M68K_ADDR[21]} & ~M68K_RW & ~nAS); // CPU writes to $000000~$1FFFFF
(SYSTEM_CDx & ~|{A23Z, A22Z, M68K_ADDR[21]} & ~M68K_RW & ~(nLDS & nUDS)); // CPU writes to $000000~$1FFFFF
wire CD_WR_SDRAM_SIG = SYSTEM_CDx & |{CD_TR_WR_SPR, CD_TR_WR_FIX, CD_EXT_WR};
@@ -896,7 +900,7 @@ wire nROMOE = nROMOEL & nROMOEU;
wire nPORTOE = nPORTOEL & nPORTOEU;
// CD system work ram is in SDRAM
wire CD_EXT_RD = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_IN[23:21] == 3'd0) & DMA_RD_OUT) : // DMA reads from $000000~$1FFFFF
wire CD_WRAM_RD = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_IN[23:20] == 4'd1) & DMA_RD_OUT) : // DMA reads from $100000~$1FFFFF
(SYSTEM_CDx & (~nWRL | ~nWRU)); // CPU reads from $100000~$1FFFFF
wire sdram_ready;
@@ -1028,10 +1032,15 @@ sdram_mux SDRAM_MUX(
.PROM_DATA_READY(PROM_DATA_READY),
.CD_TR_AREA(CD_TR_AREA),
.CD_EXT_RD(CD_EXT_RD),
.CD_EXT_WR(CD_EXT_WR),
.CD_WRAM_RD(CD_WRAM_RD),
.CD_WR_SDRAM_SIG(CD_WR_SDRAM_SIG),
.CD_USE_FIX(CD_USE_FIX),
.CD_TR_RD_FIX(CD_TR_RD_FIX),
.CD_TR_WR_FIX(CD_TR_WR_FIX),
.CD_BANK_SPR(CD_BANK_SPR),
.CD_USE_SPR(CD_USE_SPR),
.CD_TR_RD_SPR(CD_TR_RD_SPR),
.DMA_ADDR_OUT(DMA_ADDR_OUT), .DMA_ADDR_IN(DMA_ADDR_IN),
.DMA_DATA_OUT(DMA_DATA_OUT),
@@ -1048,6 +1057,7 @@ sdram_mux SDRAM_MUX(
.S_LATCH(S_LATCH),
.FIX_BANK(FIX_BANK),
.FIX_EN(FIX_EN),
.SROM_DATA(SROM_DATA),
.DL_EN(ioctl_download & ioctl_en),
@@ -1190,7 +1200,7 @@ wire IPL2_OUT = ~(SYSTEM_CDx & CD_IRQ);
// Because of the SDRAM latency, nDTACK is handled differently for ROM zones
// If the address is in a ROM zone, PROM_DATA_READY is used to extend the normal nDTACK output by NEO-C1
wire nDTACK_ADJ = ~&{nSROMOE, nROMOE, nPORTOE, ~CD_EXT_RD} ? ~PROM_DATA_READY | nDTACK
wire nDTACK_ADJ = ~&{nSROMOE, nROMOE, nPORTOE, ~CD_WRAM_RD, ~CD_TR_RD_FIX, ~CD_TR_RD_SPR} ? ~PROM_DATA_READY | nDTACK
: (CD_TR_WR_Z80 | CD_TR_WR_PCM) ? ~ddram_dtack | nDTACK
: nDTACK;
@@ -1217,10 +1227,13 @@ assign M68K_DATA_BYTE_MASK = (~|{nLDS, nUDS}) ? M68K_DATA :
assign M68K_DATA = M68K_RW ? 16'bzzzzzzzz_zzzzzzzz : FX68K_DATAOUT;
assign FX68K_DATAIN = M68K_RW ? M68K_DATA_BYTE_MASK : 16'h0000;
assign FIXD = S2H1 ? SROM_DATA[15:8] : SROM_DATA[7:0];
assign FIXD = CD_USE_FIX ? 8'bzzzz_zzzz : S2H1 ? SROM_DATA[15:8] : SROM_DATA[7:0];
// Disable ROM read in PORT zone if the game uses a special chip
assign M68K_DATA = (nROMOE & nSROMOE & |{nPORTOE, cart_chip, cart_pchip}) ? 16'bzzzzzzzzzzzzzzzz : PROM_DATA;
assign M68K_DATA = ((nROMOE & nSROMOE & |{nPORTOE, cart_chip, cart_pchip}) | CD_TR_RD_FIX) ? 16'bzzzzzzzzzzzzzzzz : PROM_DATA;
// Output correct FIX byte
assign M68K_DATA[7:0] = ~CD_TR_RD_FIX ? 8'bzzzz_zzzz : (M68K_ADDR[4] ? PROM_DATA[15:8] : PROM_DATA[7:0]);
// 68k work RAM
dpram #(15) WRAML(
@@ -1547,7 +1560,7 @@ end
// CR_DOUBLE: [8px left] [8px right]
// BP A B C D A B C D
wire [31:0] CR = CA4_REG ? CR_DOUBLE[63:32] : CR_DOUBLE[31:0];
wire [31:0] CR = CD_USE_SPR ? {32{1'bz}} : CA4_REG ? CR_DOUBLE[63:32] : CR_DOUBLE[31:0];
neo_zmc2 ZMC2(
.CLK_12M(CLK_12M),

34
rtl/cd/cd.sv
View File

@@ -39,6 +39,12 @@ module cd_sys(
output CD_TR_WR_PCM,
output CD_TR_WR_Z80,
output CD_TR_WR_FIX,
output CD_TR_RD_FIX,
output CD_TR_RD_SPR,
output reg CD_USE_FIX,
output reg CD_USE_SPR,
output reg [2:0] CD_TR_AREA,
output reg [1:0] CD_BANK_SPR,
output reg CD_BANK_PCM,
@@ -78,7 +84,7 @@ module cd_sys(
input DMA_SDRAM_BUSY
);
reg CD_USE_SPR, CD_USE_PCM, CD_USE_Z80, CD_USE_FIX;
reg CD_USE_PCM, CD_USE_Z80;
reg CD_nRESET_DRIVE;
reg [15:0] REG_FF0002;
reg [11:0] REG_FF0004;
@@ -406,15 +412,25 @@ module cd_sys(
wire LC8951_WR = (WRITING & (M68K_ADDR[11:2] == 10'b0001_000000)); // FF0101, FF0103
// nAS used ?
wire TR_ZONE_WR = DMA_RUNNING ? CD_UPLOAD_EN & (DMA_ADDR_OUT[23:20] == 4'hE) & DMA_WR_OUT :
CD_UPLOAD_EN & (M68K_ADDR[23:20] == 4'hE) & ~M68K_RW;
wire TR_ZONE = DMA_RUNNING ? (DMA_ADDR_OUT[23:20] == 4'hE) : (M68K_ADDR[23:20] == 4'hE);
wire TR_ZONE_RD = TR_ZONE & (DMA_RUNNING ? DMA_RD_OUT : M68K_RW & ~(nLDS & nUDS));
wire TR_ZONE_WR = TR_ZONE & CD_UPLOAD_EN & (DMA_RUNNING ? DMA_WR_OUT : ~M68K_RW & ~(nLDS & nUDS));
wire CD_TR_SPR = (CD_TR_AREA == 3'd0) & CD_USE_SPR;
wire CD_TR_PCM = (CD_TR_AREA == 3'd1) & CD_USE_PCM;
wire CD_TR_Z80 = (CD_TR_AREA == 3'd4) & CD_USE_Z80;
wire CD_TR_FIX = (CD_TR_AREA == 3'd5) & CD_USE_FIX;
// Allow writes only if the "allow write" flag of the corresponding region is set
assign CD_TR_WR_SPR = TR_ZONE_WR & (CD_TR_AREA == 3'd0) & CD_USE_SPR;
assign CD_TR_WR_PCM = TR_ZONE_WR & (CD_TR_AREA == 3'd1) & CD_USE_PCM;
assign CD_TR_WR_Z80 = TR_ZONE_WR & (CD_TR_AREA == 3'd4) & CD_USE_Z80;
assign CD_TR_WR_FIX = TR_ZONE_WR & (CD_TR_AREA == 3'd5) & CD_USE_FIX;
assign CD_TR_WR_SPR = TR_ZONE_WR & CD_TR_SPR;
assign CD_TR_WR_PCM = TR_ZONE_WR & CD_TR_PCM;
assign CD_TR_WR_Z80 = TR_ZONE_WR & CD_TR_Z80;
assign CD_TR_WR_FIX = TR_ZONE_WR & CD_TR_FIX;
assign CD_TR_RD_FIX = TR_ZONE_RD & CD_TR_FIX;
assign CD_TR_RD_SPR = TR_ZONE_RD & CD_TR_SPR;
reg [1:0] CDD_nIRQ_SR;
always @(posedge clk_sys or negedge nRESET)

112
rtl/mem/sdram_mux.sv
View File

@@ -73,8 +73,13 @@ module sdram_mux(
output reg DMA_SDRAM_BUSY,
input [2:0] CD_TR_AREA,
input CD_EXT_WR,
input CD_EXT_RD,
input CD_WRAM_RD,
input [1:0] CD_BANK_SPR,
input CD_USE_SPR,
input CD_TR_RD_SPR,
input CD_USE_FIX,
input CD_TR_RD_FIX,
input CD_TR_WR_FIX,
input CD_WR_SDRAM_SIG
);
@@ -89,38 +94,33 @@ module sdram_mux(
assign SDRAM_BS = (DL_EN | ~SDRAM_WR_BYTE_MODE) ? 2'b11 : {~CD_REMAP_TR_ADDR[0],CD_REMAP_TR_ADDR[0]};
assign SDRAM_DIN = DL_EN ? dl_data : wr_data;
reg M68K_RD_RUN, SROM_RD_RUN, CROM_RD_RUN, CD_WR_RUN;
reg M68K_RD_RUN, SFIX_RD_RUN, CROM_RD_RUN, CD_TR_RUN;
// SDRAM address mux
always_comb begin
casez ({DL_EN, CD_WR_RUN, SROM_RD_RUN, M68K_RD_RUN, CD_EXT_RD, ~nROMOE, ~nPORTOE})
casez ({DL_EN, CD_TR_RUN, SFIX_RD_RUN, M68K_RD_RUN, ~nROMOE, ~nPORTOE})
// HPS loading pass-through
7'b1zzzzzz: SDRAM_ADDR = dl_addr;
6'b1zzzzz: SDRAM_ADDR = dl_addr;
// CD transfer
7'b01zzzzz: SDRAM_ADDR = CD_REMAP_TR_ADDR[24:1];
6'b01zzzz: SDRAM_ADDR = CD_REMAP_TR_ADDR[24:1];
// SFIX ROM (CD) $0080000~$009FFFF
// S1 ROM (cart) $0080000~$00FFFFF
// SFIX ROM (cart) $0020000~$003FFFF
7'b001zzzz: SDRAM_ADDR = SYSTEM_CDx ? {8'b0_0000_100, S_LATCH[15:4], S_LATCH[2:0], ~S_LATCH[3]}:
6'b001zzz: SDRAM_ADDR = SYSTEM_CDx ? {8'b0_0000_100, S_LATCH[15:4], S_LATCH[2:0], ~S_LATCH[3]}:
nSYSTEM_G ? {6'b0_0000_1, FIX_BANK, S_LATCH[15:4], S_LATCH[2:0], ~S_LATCH[3]}:
{8'b0_0000_001, S_LATCH[15:4], S_LATCH[2:0], ~S_LATCH[3]};
// Work RAM (cart) $0100000~$010FFFF, or Extended RAM (CD) $0100000~$01FFFFF
7'b00011zz: SDRAM_ADDR = ~SYSTEM_CDx ? {9'b0_0001_0000, M68K_ADDR[15:1]} :
DMA_RUNNING ? {5'b0_0001, DMA_ADDR_IN[19:1]} :
{5'b0_0001, M68K_ADDR[19:1]} ;
// P1 ROM $0200000~$02FFFFF
7'b000101z: SDRAM_ADDR = {5'b0_0010, M68K_ADDR[19:1]};
6'b00011z: SDRAM_ADDR = {5'b0_0010, M68K_ADDR[19:1]};
// P2 ROM (cart) $0300000~... bankswitched
7'b0001001: SDRAM_ADDR = P2ROM_OFFSET[26:1] + P2ROM_ADDR[26:1];
6'b000101: SDRAM_ADDR = P2ROM_OFFSET[26:1] + P2ROM_ADDR[26:1];
// System ROM (CD) $0000000~$007FFFF
// System ROM (cart) $0000000~$001FFFF
7'b0001000: SDRAM_ADDR = SYSTEM_CDx ? {6'b0_0000_0, M68K_ADDR[18:1]} :
6'b000100: SDRAM_ADDR = SYSTEM_CDx ? {6'b0_0000_0, M68K_ADDR[18:1]} :
{8'b0_0000_000, M68K_ADDR[16:1]} ;
// C ROMs Bytes $0800000~$7FFFFFF
@@ -132,19 +132,19 @@ module sdram_mux(
reg SDRAM_CROM_SIG_SR;
reg SDRAM_SROM_SIG_SR;
// Only allow DMA to read from $000000~$1FFFFF
wire SDRAM_M68K_SIG = CD_EXT_RD | (~DMA_RUNNING & ~&{nSROMOE, nROMOE, nPORTOE});
wire SDRAM_M68K_SIG = ~&{nSROMOE, nROMOE, nPORTOE};
wire REQ_M68K_RD = (~SDRAM_M68K_SIG_SR & SDRAM_M68K_SIG);
wire REQ_CROM_RD = (SDRAM_CROM_SIG_SR & ~PCK1) & SPR_EN;
wire REQ_SROM_RD = (SDRAM_SROM_SIG_SR & ~PCK2) & FIX_EN;
wire REQ_CROM_RD = (SDRAM_CROM_SIG_SR & ~PCK1) & SPR_EN & ~CD_USE_SPR;
wire REQ_SROM_RD = (SDRAM_SROM_SIG_SR & ~PCK2) & FIX_EN & ~CD_USE_FIX;
wire CD_FIX_WR = ((CD_TR_AREA == 3'd5) & ~CD_EXT_WR);
wire CD_LDS_ONLY_WR = CD_FIX_WR;
wire CD_RD_SDRAM_SIG = CD_WRAM_RD | CD_TR_RD_FIX | CD_TR_RD_SPR;
wire CD_LDS_ONLY_WR = CD_TR_WR_FIX;
always @(posedge CLK) begin
reg M68K_RD_REQ, SROM_RD_REQ, CROM_RD_REQ, CD_WR_REQ;
reg nDS_PREV, nAS_PREV, DMA_WR_OUT_PREV;
reg nAS_PREV;
reg CD_WR_SDRAM_SIG_PREV, CD_RD_SDRAM_SIG_PREV;
reg old_ready;
if(DL_WR & DL_EN) begin
@@ -160,8 +160,9 @@ module sdram_mux(
end
nAS_PREV <= nAS;
nDS_PREV <= nLDS & nUDS;
DMA_WR_OUT_PREV <= DMA_WR_OUT;
CD_RD_SDRAM_SIG_PREV <= CD_RD_SDRAM_SIG;
CD_WR_SDRAM_SIG_PREV <= CD_WR_SDRAM_SIG;
SDRAM_M68K_SIG_SR <= SDRAM_M68K_SIG;
SDRAM_CROM_SIG_SR <= PCK1;
@@ -174,9 +175,9 @@ module sdram_mux(
CD_WR_REQ <= 0;
CROM_RD_RUN <= 0;
SROM_RD_RUN <= 0;
SFIX_RD_RUN <= 0;
M68K_RD_RUN <= 0;
CD_WR_RUN <= 0;
CD_TR_RUN <= 0;
DMA_SDRAM_BUSY <= 0;
@@ -189,31 +190,39 @@ module sdram_mux(
if (~nAS_PREV & nAS) PROM_DATA_READY <= 0;
if (~DMA_RUNNING) DMA_SDRAM_BUSY <= 0;
// Detect 68k or DMA write requests
// Detect falling edge of nLDS or nUDS, or rising edge of DMA_WR_OUT while CD_WR_SDRAM_SIG is high
if (((nDS_PREV & ~(nLDS & nUDS)) | (~DMA_WR_OUT_PREV & DMA_WR_OUT)) & CD_WR_SDRAM_SIG) begin
// Detect 68k or DMA requests for CD specific reads/writes
if ((~CD_RD_SDRAM_SIG_PREV & CD_RD_SDRAM_SIG) | (~CD_WR_SDRAM_SIG_PREV & CD_WR_SDRAM_SIG)) begin
// Convert and latch address
casez({CD_EXT_WR, CD_TR_AREA})
4'b1_???: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {3'b0_00, ~DMA_ADDR_OUT[20], DMA_ADDR_OUT[20:1], 1'b0} : {3'b0_00, ~M68K_ADDR[20], M68K_ADDR[20:1], ~nLDS}; // EXT zone SDRAM
4'b0_000: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {3'b0_10, CD_BANK_SPR, DMA_ADDR_OUT[19:7], DMA_ADDR_OUT[5:2], ~DMA_ADDR_OUT[6], ~DMA_ADDR_OUT[1], 1'b0} : {3'b0_10, CD_BANK_SPR, M68K_ADDR[19:7], M68K_ADDR[5:2], ~M68K_ADDR[6], ~M68K_ADDR[1], 1'b0}; // Sprites SDRAM
//4'b0_001: CD_REMAP_TR_ADDR <= {4'b0_000, CD_BANK_PCM, CD_TR_WR_ADDR, 1'b0}; // ADPCM DDRAM
4'b0_101: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {8'b0_0000_100, DMA_ADDR_OUT[17:6], DMA_ADDR_OUT[3:1], ~DMA_ADDR_OUT[5], ~DMA_ADDR_OUT[4]} : {8'b0_0000_100, M68K_ADDR[17:6], M68K_ADDR[3:1], ~M68K_ADDR[5], ~M68K_ADDR[4]}; // Fix SDRAM
//4'b0_100: CD_REMAP_TR_ADDR <= {8'b0_0000_000, CD_TR_WR_ADDR[16:1], 1'b0}; // Z80 BRAM
default: CD_REMAP_TR_ADDR <= 25'h0AAAAAA; // DEBUG
casez({CD_WRAM_RD, CD_EXT_WR, CD_TR_AREA})
// Extended RAM (CD) read $0100000~$01FFFFF
5'b1_?_???: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {5'b0_0001, DMA_ADDR_IN[19:1], 1'b0} : {5'b0_0001, M68K_ADDR[19:1], ~nLDS} ; // EXT zone SDRAM
// P1 (write) or Extended RAM
5'b0_1_???: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {3'b0_00, ~DMA_ADDR_OUT[20], DMA_ADDR_OUT[20:1], 1'b0} : {3'b0_00, ~M68K_ADDR[20], M68K_ADDR[20:1], ~nLDS};
// Sprites SDRAM
5'b0_0_000: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {3'b0_10, CD_BANK_SPR, DMA_ADDR_OUT[19:7], DMA_ADDR_OUT[5:2], ~DMA_ADDR_OUT[6], ~DMA_ADDR_OUT[1], 1'b0} : {3'b0_10, CD_BANK_SPR, M68K_ADDR[19:7], M68K_ADDR[5:2], ~M68K_ADDR[6], ~M68K_ADDR[1], 1'b0};
// FIX SDRAM
5'b0_0_101: CD_REMAP_TR_ADDR <= DMA_RUNNING ? {8'b0_0000_100, DMA_ADDR_OUT[17:6], DMA_ADDR_OUT[3:1], ~DMA_ADDR_OUT[5], ~DMA_ADDR_OUT[4]} : {8'b0_0000_100, M68K_ADDR[17:6], M68K_ADDR[3:1], ~M68K_ADDR[5], ~M68K_ADDR[4]};
default: CD_REMAP_TR_ADDR <= 25'h0AAAAAA; // DEBUG
endcase
// DMA writes are always done in words
//SDRAM_WR_BYTE_MODE <= (((CD_TR_AREA == 3'd5) & ~CD_EXT_WR) | (CD_EXT_WR & (nLDS ^ nUDS))) & ~DMA_RUNNING; // Fix or extended RAM data
SDRAM_WR_BYTE_MODE <= (CD_LDS_ONLY_WR | (CD_EXT_WR & (nLDS ^ nUDS))); // Fix or extended RAM data
if (CD_RD_SDRAM_SIG) begin // read
M68K_RD_REQ <= 1;
end else begin
// DMA writes are always done in words. FIX layer is on a 8bit bus so should only write the low byte.
SDRAM_WR_BYTE_MODE <= (CD_LDS_ONLY_WR | ((CD_EXT_WR) & (nLDS ^ nUDS))); // Fix or extended RAM data
// TODO: make sure wr_data gets correct data according to selected byte
wr_data <= DMA_RUNNING ? (CD_LDS_ONLY_WR ? {DMA_DATA_OUT[7:0],DMA_DATA_OUT[7:0]} : DMA_DATA_OUT)
: (CD_LDS_ONLY_WR ? {M68K_DATA[7:0],M68K_DATA[7:0]} : M68K_DATA);
wr_data <= DMA_RUNNING ? (CD_LDS_ONLY_WR ? {DMA_DATA_OUT[7:0],DMA_DATA_OUT[7:0]} : DMA_DATA_OUT)
: (CD_LDS_ONLY_WR ? {M68K_DATA[7:0],M68K_DATA[7:0]} : M68K_DATA);
// In DMA, start if: nothing is running, no LSPC read (priority case C)
// Out of DMA, start if: nothing is running (priority case B)
// TO TEST
CD_WR_REQ <= 1;
// In DMA, start if: nothing is running, no LSPC read (priority case C)
// Out of DMA, start if: nothing is running (priority case B)
// TO TEST
CD_WR_REQ <= 1;
end
end
// Detect 68k read requests
@@ -236,13 +245,13 @@ module sdram_mux(
// Having two non-nested IF statements with the & in the condition
// prevents synthesis from chaining too many muxes and causing
// timing analysis to fail
if (CD_WR_RUN) begin
CD_WR_RUN <= 0;
if (CD_TR_RUN) begin
CD_TR_RUN <= 0;
DMA_SDRAM_BUSY <= 0;
end
if (SROM_RD_RUN) begin
if (SFIX_RD_RUN) begin
SROM_DATA <= SDRAM_DOUT[15:0];
SROM_RD_RUN <= 0;
SFIX_RD_RUN <= 0;
end
if (M68K_RD_RUN) begin
PROM_DATA <= SDRAM_DOUT[15:0];
@@ -259,6 +268,7 @@ module sdram_mux(
if (M68K_RD_REQ | REQ_M68K_RD) begin
M68K_RD_REQ <= 0;
M68K_RD_RUN <= 1;
CD_TR_RUN <= CD_RD_SDRAM_SIG;
SDRAM_RD <= 1;
SDRAM_BURST <= 0;
DMA_SDRAM_BUSY <= DMA_RUNNING;
@@ -271,13 +281,13 @@ module sdram_mux(
end
else if (SROM_RD_REQ | REQ_SROM_RD) begin
SROM_RD_REQ <= 0;
SROM_RD_RUN <= 1;
SFIX_RD_RUN <= 1;
SDRAM_RD <= 1;
SDRAM_BURST <= 0;
end
else if (CD_WR_REQ) begin
CD_WR_REQ <= 0;
CD_WR_RUN <= 1;
CD_TR_RUN <= 1;
SDRAM_WR <= 1;
DMA_SDRAM_BUSY <= DMA_RUNNING;
end