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Add mappers 94,97,180,155
--94: Tested with Senjou no Ookami --97: Tested with Kaiketsu Yanchamaru --180: Tested with Crazy Climber Mapper 2 currently doesn't enforce RAM protect, so mapper 155 is identical. --Tested with Tatakae!! Ramen Man
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GreyRogue
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@@ -27,13 +27,13 @@ The battery backed RAM (Save RAM) for the NES does not write to disk automatical
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49
mmu.v
49
mmu.v
@@ -1503,6 +1503,7 @@ module Mapper28(input clk, input ce, input reset,
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// Allow writes to 0x5000 only when launching through the proper mapper ID.
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wire [7:0] mapper = flags[7:0];
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wire allow_select = (mapper == 8'd28);
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wire extend_bit = (mapper == 97);
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always @(posedge clk) if (reset) begin
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mode[5:2] <= 0; // NROM mode, 32K mode
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@@ -1511,7 +1512,7 @@ module Mapper28(input clk, input ce, input reset,
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selreg <= 1;
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// Set value for mirroring
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if (mapper == 2 || mapper == 0 || mapper == 3 || mapper == 185)
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if (mapper == 2 || mapper == 0 || mapper == 3 || mapper == 94 || mapper == 180 || mapper == 185)
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mode[1:0] <= flags[14] ? 2'b10 : 2'b11;
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// UNROM #2 - Current bank in $8000-$BFFF and fixed top half of outer bank in $C000-$FFFF
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@@ -1527,6 +1528,26 @@ module Mapper28(input clk, input ce, input reset,
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if (mapper == 185)
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selreg <= 4;
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// UNROM #180 - Fixed first PRG bank, Fixed CHR Bank.
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if (mapper == 180) begin
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selreg <= 1;
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mode[5:2] <= 4'b1110;
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outer[5:0] <= 6'h00;
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end
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// IREM TAM-S1 IC #97 - Fixed first PRG bank, Fixed CHR Bank, Mirroring.
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if (mapper == 97) begin
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selreg <= 6;
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mode[5:2] <= 4'b1110;
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outer[5:0] <= 6'h3F;
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end
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// IREM TAM-S1 IC #94 - Fixed last PRG bank, Fixed CHR Bank
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if (mapper == 94) begin
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selreg <= 7;
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mode[5:2] <= 4'b1111;
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end
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// AxROM #7 - Switch 32kb rom bank + switchable nametables
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if (mapper == 7) begin
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mode[1:0] <= 2'b00; // Switchable VRAM page.
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@@ -1538,11 +1559,13 @@ module Mapper28(input clk, input ce, input reset,
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selreg <= {1'b0,prg_din[7], prg_din[0]}; // select register
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if (prg_ain[15] & prg_write) begin
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casez (selreg)
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3'h000: {mode[0], a53chr} <= {(mode[1] ? mode[0] : prg_din[4]), prg_din[1:0]}; // CHR RAM bank
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3'h001: {mode[0], inner} <= {(mode[1] ? mode[0] : prg_din[4]), prg_din[3:0]}; // "inner" bank
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3'h010: {mode} <= {prg_din[5:0]}; // mode register
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3'h011: {outer} <= {prg_din[5:0]}; // "outer" bank
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3'b1??: {security} <= {prg_din[5:4],prg_din[1:0]}; // security
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3'b000: {mode[0], a53chr} <= {(mode[1] ? mode[0] : prg_din[4]), prg_din[1:0]}; // CHR RAM bank
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3'b001: {mode[0], inner} <= {(mode[1] ? mode[0] : prg_din[4]), prg_din[3:0]}; // "inner" bank
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3'b010: {mode} <= {prg_din[5:0]}; // mode register
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3'b011: {outer} <= {prg_din[5:0]}; // "outer" bank
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3'b10?: {security} <= {prg_din[5:4],prg_din[1:0]}; // security
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3'b110: {mode[1:0],inner} <= {prg_din[7] ^ prg_din[6], prg_din[6], prg_din[3:0]}; // "inner" bank
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3'b111: {inner} <= {prg_din[5:2]}; // "inner" bank
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endcase
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end
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end
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@@ -1571,9 +1594,9 @@ module Mapper28(input clk, input ce, input reset,
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5'b11_10_1,
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5'b11_11_0 : a53prg = {outer[5:3], inner[3:0]}; // 256K banks, UNROM mode
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default : a53prg = {outer[5:0], prg_ain[14]}; // 16K fixed bank
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default : a53prg = {outer[5:0], extend_bit ? outer[0] : prg_ain[14]}; // 16K fixed bank
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endcase
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chr_dout = 8'hFF;//chr_ain[7:0]; // return LSB of address below when CHR disabled by security
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chr_dout = 8'hFF;//chr_ain[7:0]; // return open bus = LSB of address? below when CHR disabled by security
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end
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assign vram_ce = chr_ain[13];
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@@ -1581,7 +1604,7 @@ module Mapper28(input clk, input ce, input reset,
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assign prg_allow = prg_ain[15] && !prg_write;
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assign chr_allow = flags[15];
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assign chr_aout = {7'b10_0000_0, a53chr, chr_ain[12:0]};
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wire submapper = flags[24:21];
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wire [4:0] submapper = flags[24:21];
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assign has_chr_dout = (mapper == 185) && ( ((submapper == 0) && (security[1:0] == 2'b00))
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|| ((submapper == 4) && (security[1:0] != 2'b00))
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|| ((submapper == 5) && (security[1:0] != 2'b01))
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@@ -3170,7 +3193,9 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
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// 88 = Needs testing
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// 89 = Needs testing
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// 93 = Needs testing
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// 94 = Needs testing
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// 95 = Needs testing
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// 97 = Needs testing
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// 101 = Needs testing
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// 105 = Working
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// 113 = Working
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@@ -3179,8 +3204,10 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
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// 140 = Needs testing
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// 152 = Needs testing
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// 154 = Needs testing
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// 155 = Needs testing
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// 158 = Tons of GFX bugs
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// 165 = GFX corrupted
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// 180 = Needs testing
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// 184 = Needs testing
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// 185 = Needs testing
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// 191 = Not Tested
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@@ -3192,6 +3219,7 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
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// 228 = Working
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// 234 = Not Tested
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case(flags[7:0])
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155,
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1: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow} = {mmc1_prg_addr, mmc1_prg_allow, mmc1_chr_addr, mmc1_vram_a10, mmc1_vram_ce, mmc1_chr_allow};
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9: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow} = {mmc2_prg_addr, mmc2_prg_allow, mmc2_chr_addr, mmc2_vram_a10, mmc2_vram_ce, mmc2_chr_allow};
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118, // TxSROM connects A17 to CIRAM A10.
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@@ -3223,6 +3251,9 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
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2,
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3,
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7,
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94,
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97,
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180,
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185,
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28: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow, chr_dout, has_chr_dout} = {map28_prg_addr, map28_prg_allow, map28_chr_addr, map28_vram_a10, map28_vram_ce, map28_chr_allow, map28_chr_dout, map28_has_chr_dout};
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