mirror of
https://github.com/MiSTer-devel/MultiComp_MiSTer.git
synced 2026-04-19 03:04:38 +00:00
b4c9d45ed1
increase read buffer of UART from 16 to 64 bytes allow selection of UART baud rate allow selection of sd controller or image controller update readme.md with more explanation of above and more detail on MultiComp use specifically for CP/M
558 lines
14 KiB
Systemverilog
558 lines
14 KiB
Systemverilog
//============================================================================
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// Grant’s multi computer
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//
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// Port to MiSTer.
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//
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// Based on Grant’s multi computer
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// http://searle.hostei.com/grant/
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// http://searle.hostei.com/grant/Multicomp/index.html
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// and WiSo's collector blog (MiST port)
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// https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-1/
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// https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-2/
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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/*
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// Use framebuffer from DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of 16 bytes.
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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*/
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI SECONDARY SDCARD
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign UART_RTS = UART_CTS;
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assign UART_DTR = UART_DSR;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign VIDEO_ARX = 4;
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assign VIDEO_ARY = 3;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign AUDIO_S = 0;
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assign AUDIO_L = 0;
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assign AUDIO_R = 0;
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assign AUDIO_MIX = 0;
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// enable input on USER_IO[3] for ch376s MISO
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assign USER_OUT[3] = 1'b1;
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// enable input on USER_IO[0] for UART i.e. USER_IN[0] rx
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assign USER_OUT[0] = 1'b1;
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`include "build_id.v"
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localparam CONF_STR = {
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"MultiComp;;",
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"S,IMG;",
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"OF,Reset after Mount,No,Yes;", // 15
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"-;",
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"O78,CPU-ROM,Z80-CP/M,Z80-BASIC,6502-Basic,6809-Basic;", // 7,8
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"-;",
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"O9B,Baud Rate tty,115200,38400,19200,9600,4800,2400;", // 9,10,11
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"OC,Serial Port,UART,USER_IO;", // 12 Add serial port selection
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"OD,Storage Controller,SD Controller,Image Controller;", // 13 Select storage controller
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"-;",
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"RE,Reset;", // 14
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"V,v",`BUILD_DATE
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};
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////////////////// HPS I/O ///////////////////
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wire [1:0] buttons;
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wire [31:0] status;
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wire PS2_CLK;
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wire PS2_DAT;
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wire forced_scandoubler;
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wire [31:0] sd_lba;
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din;
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wire sd_buff_wr;
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wire sd_ack_conf;
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wire img_mounted;
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wire img_readonly;
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wire [63:0] img_size;
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hps_io #(
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.STRLEN($size(CONF_STR)>>3),
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.PS2DIV (2000)
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) hps_io
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(
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.clk_sys(CLK_50M),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.forced_scandoubler(forced_scandoubler),
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.ps2_kbd_clk_out(PS2_CLK),
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.ps2_kbd_data_out(PS2_DAT),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_ack_conf(sd_ack_conf),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.img_mounted(img_mounted),
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.img_readonly(img_readonly),
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.img_size(img_size),
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.uart_mode(16'b000_11111_000_11111)
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);
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/////////////////////// CLOCKS ///////////////////////////////
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wire clk_sys, locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.locked(locked)
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);
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///////////////// RESET /////////////////////////
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wire reset = RESET | status[0] | buttons[1] | status[14] | (status[15] && img_mounted);
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///////////////// SDCARD ////////////////////////
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// SD card interface signal declarations
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// _sd suffix for SD controller signals
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// _img suffix for image controller signals
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// _mux suffix for multiplexed signals
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wire sdclk_sd, sdmosi_sd, sdcs_sd; // SD controller outputs
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wire sdclk_img, sdmosi_img, sdcs_img; // Image controller outputs
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wire driveLED_sd, driveLED_img; // Drive activity indicators
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// Multiplexed signals that route to physical SD interface
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wire sdclk_mux, sdmosi_mux, sdcs_mux; // Multiplexed control signals
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wire sdmiso_mux; // Multiplexed data input
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wire driveLED_mux; // Multiplexed activity indicator
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// Controller selection - determines which controller drives SD interface
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wire sd_ctrl_sel = status[14]; // 0=SD controller, 1=image controller
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// Multiplex between SD and image controller outputs
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assign sdclk_mux = sd_ctrl_sel ? sdclk_img : sdclk_sd; // Clock output
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assign sdmosi_mux = sd_ctrl_sel ? sdmosi_img : sdmosi_sd; // Data output to SD
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assign sdcs_mux = sd_ctrl_sel ? sdcs_img : sdcs_sd; // Chip select
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assign driveLED_mux = sd_ctrl_sel ? driveLED_img : driveLED_sd; // Activity LED
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// MISO input routing - selects between SD card and virtual SD based on vsd_sel
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assign sdmiso_mux = vsd_sel ? vsdmiso : SD_MISO;
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// Virtual SD interface enable
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reg vsd_sel = 0;
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always @(posedge clk_sys) if(img_mounted) vsd_sel <= |img_size;
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// Map multiplexed signals to physical SD interface
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// High-Z when virtual SD not selected
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// old code
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//assign SD_SCK = vsd_sel ? sdclk_mux : 1'bZ; // SD clock
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//assign SD_MOSI = vsd_sel ? sdmosi_mux : 1'bZ; // SD data out
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//assign SD_CS = vsd_sel ? sdcs_mux : 1'bZ; // SD chip select
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// Keep physical SD enabled when using SD controller
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assign SD_SCK = (vsd_sel || !sd_ctrl_sel) ? sdclk_mux : 1'bZ;
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assign SD_MOSI = (vsd_sel || !sd_ctrl_sel) ? sdmosi_mux : 1'bZ;
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assign SD_CS = (vsd_sel || !sd_ctrl_sel) ? sdcs_mux : 1'bZ;
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// Virtual SD card implementation
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sd_card sd_card
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(
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.*,
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.clk_spi(clk_sys),
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.sdhc(1),
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.sck(sdclk_mux),
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.ss(sdcs_mux | ~vsd_sel),
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.mosi(sdmosi_mux),
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.miso(vsdmiso)
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);
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// Drive activity detection
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reg sd_act;
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always @(posedge clk_sys) begin
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reg old_mosi, old_miso;
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integer timeout = 0;
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old_mosi <= sdmosi_mux;
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old_miso <= sdmiso_mux;
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sd_act <= 0;
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if(timeout < 1000000) begin
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timeout <= timeout + 1;
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sd_act <= 1;
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end
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if((old_mosi ^ sdmosi_mux) || (old_miso ^ sdmiso_mux)) timeout <= 0;
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end
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// Map drive LED to system LED output
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assign LED_USER = vsd_sel & sd_act;
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assign LED_DISK = {2{~driveLED_mux}};
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///////////////////////////////////////////////////
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assign CLK_VIDEO = clk_sys;
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typedef enum {cpuZ80CPM='b00, cpuZ80Basic='b01, cpu6502Basic='b10, cpu6809Basic='b11} cpu_type_enum;
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wire [1:0] cpu_type = status[8:7];
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typedef enum {baud115200='b000, baud38400='b001, baud19200='b010, baud9600='b011, baud4800='b100, baud2400='b101} baud_rate_enum;
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wire [2:0] baud_rate = status[11:9];
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wire hblank, vblank;
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wire hs, vs;
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wire [1:0] r,g,b;
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wire [3:0] _hblank, _vblank;
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wire [3:0] _hs, _vs;
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wire [1:0] _r[3:0], _g[3:0], _b[3:0];
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wire [3:0] _driveLED;
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wire [3:0] _CE_PIXEL;
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wire [3:0] _SD_CS;
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wire [3:0] _SD_MOSI;
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wire [3:0] _SD_SCK;
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wire [3:0] _txd[3:0];
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wire serial_rx = (status[12] ? USER_IN[0] : UART_RXD);
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wire serial_tx;
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assign UART_TXD = status[12] ? 1'b1 : serial_tx;
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assign USER_OUT[1] = status[12] ? serial_tx : 1'b1;
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always_comb
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begin
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hblank <= _hblank[cpu_type];
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vblank <= _vblank[cpu_type];
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hs <= _hs[cpu_type];
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vs <= _vs[cpu_type];
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r <= _r[cpu_type][1:0];
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g <= _g[cpu_type][1:0];
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b <= _b[cpu_type][1:0];
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CE_PIXEL <= _CE_PIXEL[cpu_type];
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serial_tx <= _txd[cpu_type];
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end
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// Add baud rate selection logic - add this before the microcomputer instances:
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reg [15:0] baud_increment;
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always @(*) begin
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case(baud_rate)
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baud115200: baud_increment = 16'd2416; // 115200
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baud38400: baud_increment = 16'd805; // 38400
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baud19200: baud_increment = 16'd403; // 19200
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baud9600: baud_increment = 16'd201; // 9600
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baud4800: baud_increment = 16'd101; // 4800
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baud2400: baud_increment = 16'd50; // 2400
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default: baud_increment = 16'd2416; // Default to 115200
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endcase
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end
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/*
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reg [6:0] test;
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reg [4:0] mycnt;
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initial test = 0;
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initial mycnt = 0;
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always @(posedge clk_sys) begin
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if (mycnt>25) begin
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test <= test + 1'b1;
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mycnt <= 0;
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end
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else begin
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mycnt <= mycnt + 1'b1;
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end
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USER_OUT[0] <= test[0];
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USER_OUT[1] <= test[1];
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USER_OUT[2] <= test[2];
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USER_OUT[3] <= test[3];
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USER_OUT[4] <= test[4];
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USER_OUT[5] <= test[5];
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USER_OUT[6] <= test[6];
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end
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*/
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MicrocomputerZ80CPM MicrocomputerZ80CPM
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(
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.N_RESET(~reset & cpu_type == cpuZ80CPM),
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.clk(cpu_type == cpuZ80CPM ? clk_sys : 0),
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.baud_increment(baud_increment),
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.R(_r[0][1:0]),
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.G(_g[0][1:0]),
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.B(_b[0][1:0]),
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.HS(_hs[0]),
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.VS(_vs[0]),
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.hBlank(_hblank[0]),
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.vBlank(_vblank[0]),
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.cepix(_CE_PIXEL[0]),
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.ps2Clk(PS2_CLK),
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.ps2Data(PS2_DAT),
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.sdCS(sdcs_sd), // SD controller chip select output
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.sdMOSI(sdmosi_sd), // SD controller data output
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.sdMISO(sdmiso_mux), // Multiplexed SD data input
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.sdSCLK(sdclk_sd), // SD controller clock output
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.driveLED(driveLED_sd),
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.sd_ctrl_sel(sd_ctrl_sel),
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.rxd1(serial_rx),
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.txd1(_txd[0]),
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// CH376s via USERIO
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.usbSCLK (USER_OUT[2]),
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.usbMISO (USER_IN[3]),
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.usbMOSI (USER_OUT[4]),
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.usbCS (USER_OUT[5])
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);
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MicrocomputerZ80Basic MicrocomputerZ80Basic
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(
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.N_RESET(~reset & cpu_type == cpuZ80Basic),
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.clk(cpu_type == cpuZ80Basic ? clk_sys : 0),
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.baud_increment(baud_increment),
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.R(_r[1][1:0]),
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.G(_g[1][1:0]),
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.B(_b[1][1:0]),
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.HS(_hs[1]),
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.VS(_vs[1]),
|
||
.hBlank(_hblank[1]),
|
||
.vBlank(_vblank[1]),
|
||
.cepix(_CE_PIXEL[1]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(_SD_CS[1]),
|
||
.sdMOSI(_SD_MOSI[1]),
|
||
.sdMISO(sdmiso),
|
||
.sdSCLK(_SD_SCK[1]),
|
||
.driveLED(_driveLED[1]),
|
||
.rxd1 (serial_rx),
|
||
.txd1 (_txd[1])
|
||
);
|
||
|
||
Microcomputer6502Basic Microcomputer6502Basic
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpu6502Basic),
|
||
.clk(cpu_type == cpu6502Basic ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[2][1:0]),
|
||
.G(_g[2][1:0]),
|
||
.B(_b[2][1:0]),
|
||
.HS(_hs[2]),
|
||
.VS(_vs[2]),
|
||
.hBlank(_hblank[2]),
|
||
.vBlank(_vblank[2]),
|
||
.cepix(_CE_PIXEL[2]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(_SD_CS[2]),
|
||
.sdMOSI(_SD_MOSI[2]),
|
||
.sdMISO(sdmiso),
|
||
.sdSCLK(_SD_SCK[2]),
|
||
.driveLED(_driveLED[2]),
|
||
.rxd1 (serial_rx),
|
||
.txd1 (_txd[2])
|
||
);
|
||
|
||
//Reset is not working (even on the original Grant's 6809)
|
||
Microcomputer6809Basic Microcomputer6809Basic
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpu6809Basic),
|
||
.clk(cpu_type == cpu6809Basic ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[3][1:0]),
|
||
.G(_g[3][1:0]),
|
||
.B(_b[3][1:0]),
|
||
.HS(_hs[3]),
|
||
.VS(_vs[3]),
|
||
.hBlank(_hblank[3]),
|
||
.vBlank(_vblank[3]),
|
||
.cepix(_CE_PIXEL[3]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(_SD_CS[3]),
|
||
.sdMOSI(_SD_MOSI[3]),
|
||
.sdMISO(sdmiso),
|
||
.sdSCLK(_SD_SCK[3]),
|
||
.driveLED(_driveLED[3]),
|
||
.rxd1 (serial_rx),
|
||
.txd1 (_txd[3])
|
||
);
|
||
|
||
video_cleaner video_cleaner
|
||
(
|
||
.clk_vid(CLK_VIDEO),
|
||
.ce_pix(CE_PIXEL),
|
||
|
||
.R({4{r}}),
|
||
.G({4{g}}),
|
||
.B({4{b}}),
|
||
.HSync(hs),
|
||
.VSync(vs),
|
||
.HBlank(hblank),
|
||
.VBlank(vblank),
|
||
|
||
.VGA_R(VGA_R),
|
||
.VGA_G(VGA_G),
|
||
.VGA_B(VGA_B),
|
||
.VGA_VS(VGA_VS),
|
||
.VGA_HS(VGA_HS),
|
||
.VGA_DE(VGA_DE)
|
||
);
|
||
|
||
|
||
endmodule
|