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Merge pull request #2 from S0urceror/master

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MultiComp works now with Images and UART
This commit is contained in:
Cyril Venditti
2021-01-13 10:32:59 -05:00
committed by GitHub
parent 49f42e4b83 3521a480de
commit e35a7aaf64
136 changed files with 35015 additions and 9553 deletions
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6
.gitignore vendored Normal file
View File

@@ -0,0 +1,6 @@
db/*
incremental_db/*
output_files/*
.DS_Store
**/pll_sim/*
**/*.bak

3
Components/INTERNALRAM/InternalRam64K.qip
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@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "InternalRam64K.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "InternalRam64K.cmp"]

70
Components/INTERNALRAM/InternalRam64K.vhd
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@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
-- File Name: InternalRam4K.vhd
-- File Name: InternalRam64K.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -14,32 +14,33 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY internalram64k IS
ENTITY InternalRam64K IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -55,33 +56,6 @@ ARCHITECTURE SYN OF internalram64k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
@@ -89,7 +63,7 @@ BEGIN
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 65536,
@@ -97,6 +71,7 @@ BEGIN
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 16,
width_a => 8,
width_byteena_a => 1
@@ -131,7 +106,7 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
@@ -146,13 +121,13 @@ END SYN;
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
@@ -160,15 +135,16 @@ END SYN;
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

666
Components/SDCARD/sd_controller.vhd
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@@ -18,19 +18,92 @@
--
-- Grant Searle
-- eMail address available on my main web page link above.
-- Minor changes by foofoobedoo@gmail.com
-- Additional functionality to provide SDHC support and 25 MHz SPI-clock by Rienk Koolstra.
--
-- This design uses the SPI interface and supports "standard capacity" (SDSC) and
-- "high capacity" (SDHC) cards.
-- updated by Rienk Koolstra to accept SDHC cards. Note: this implementation does not slow down the
-- interface during the init phase. The standard requires a maximum clock of 400 KHz during this
-- phase, to allow for "older" cards (read MMC) I have found this slowdown to be unnecessary for
-- all cards I tested. I am clocking this interface at 50 MHz (25 MHz SPI clock) with solid
-- results, YMMV!
-- Address Register
-- 0 SDDATA read/write data
-- 1 SDSTATUS read
-- 1 SDCONTROL write
-- 2 SDLBA0 write-only
-- 3 SDLBA1 write-only
-- 4 SDLBA2 write-only (only bits 6:0 are valid)
--
-- For both SDSC and SDHC (high capacity) cards, the block size is 512bytes (9-bit value) and the
-- SDLBA registers select the block number. SDLBA2 is most significant, SDLBA0 is least significant.
--
-- For SDSC, the read/write address parameter is a 512-byte aligned byte address. ie, it has 9 low
-- address bits explicitly set to 0. 23 of the 24 programmable address bits select the 512-byte block.
-- This gives an address capacity of 2^23 * 512 = 4GB .. BUT maximum SDSC capacity is 2GByte.
--
-- The SDLBA registers are used like this:
--
-- 31 30 29 28.27 26 25 24.23 22 21 20.19 18 17 16.15 14 13 12.11 10 09 08.07 06 05 04.03 02 01 00
--+------- SDLBA2 -----+------- SDLBA1 --------+------- SDLBA0 --------+ 0 0 0 0 0 0 0 0 0
--
-- For SDHC cards, the read/write address parameter is the ordinal number of 512-byte block ie, the
-- 9 low address bits are implicity 0. The 24 programmable address bits select the 512-byte block.
-- This gives an address capacity of 2^24 * 512 = 8GByte. SDHC can be upto 32GByte but this design
-- can only access the low 8GByte (could add SDLBA3 to get the extra address lines if required).
--
-- The SDLBA registers are used like this:
--
-- 31 30 29 28.27 26 25 24.23 22 21 20.19 18 17 16.15 14 13 12.11 10 09 08.07 06 05 04.03 02 01 00
-- 0 0 0 0 0 0 0 0+---------- SDLBA2 -----+------- SDLBA1 --------+------- SDLBA0 --------+
--
-- The end result of all this is that the addressing looks the same for SDSC and SDHC cards.
--
-- SDSTATUS (RO)
-- b7 Write Data Byte can be accepted
-- b6 Read Data Byte available
-- b5 Block Busy
-- b4 Init Busy
-- b3 Unused. Read 0
-- b2 Unused. Read 0
-- b1 Unused. Read 0
-- b0 Unused. Read 0
--
-- SDCONTROL (WO)
-- b7:0 0x00 Read block
-- 0x01 Write block
--
--
-- To read a 512-byte block from the SDCARD:
-- Wait until SDSTATUS=0x80 (ensures previous cmd has completed)
-- Write SDLBA0, SDLBA1 SDLBA2 to select block index to read from
-- Write 0 to SDCONTROL to issue read command
-- Loop 512 times:
-- Wait until SDSTATUS=0xE0 (read byte ready, block busy)
-- Read byte from SDDATA
--
-- To write a 512-byte block to the SDCARD:
-- Wait until SDSTATUS=0x80 (ensures previous cmd has completed)
-- Write SDLBA0, SDLBA1 SDLBA2 to select block index to write to
-- Write 1 to SDCONTROL to issue write command
-- Loop 512 times:
-- Wait until SDSTATUS=0xA0 (block busy)
-- Write byte to SDDATA
--
-- At HW level each data transfer is 515 bytes: a start byte, 512 data bytes,
-- 2 CRC bytes. CRC need not be valid in SPI mode, *except* for CMD0.
--
-- SDCARD specification can be downloaded from
-- https://www.sdcard.org/downloads/pls/
-- All you need is the "Part 1 Physical Layer Simplified Specification"
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity sd_controller is
generic (
constant CLKEDGE_DIVIDER : integer := 100 -- 50MHz / 100 gives edges at 500kHz ie output
-- or sdSCLK of 250kHz to be used during init phase
);
port (
sdCS : out std_logic;
sdMOSI : out std_logic;
@@ -42,7 +115,7 @@ port (
dataIn : in std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0);
regAddr : in std_logic_vector(2 downto 0);
clk : in std_logic; -- twice the spi clk;
clk : in std_logic;
driveLED : out std_logic := '1'
);
@@ -53,20 +126,19 @@ type states is (
rst,
init,
cmd0,
regreq,
cmd8,
cmd55,
acmd41,
poll_cmd,
cmd58,
cardsel,
stby, -- wait for read or write pulse
idle, -- wait for read or write pulse
read_block_cmd,
read_block_wait,
read_block_data,
send_cmd,
send_regreq,
receive_ocr_wait,
receive_ocr,
receive_byte_wait,
receive_byte,
write_block_cmd,
@@ -77,16 +149,19 @@ type states is (
);
-- one start byte, plus 512 bytes of data, plus two FF end bytes (CRC)
-- one start byte, plus 512 bytes of data, plus two ff end bytes (crc)
constant write_data_size : integer := 515;
signal state, return_state : states;
signal sclk_sig : std_logic := '0';
signal cmd_out : std_logic_vector(55 downto 0);
signal recv_data : std_logic_vector(7 downto 0);
signal ocr_data : std_logic_vector(39 downto 0);
-- at different times holds 8-bit data, 8-bit R1 response or 40-bit R7 response
signal recv_data : std_logic_vector(39 downto 0);
signal clkCount : std_logic_vector(5 downto 0);
signal clkEn : std_logic;
signal HighSpeed : std_logic := '0'; -- flag to switch to 25 MHz operation and back
signal status : std_logic_vector(7 downto 0) := x"00";
signal block_read : std_logic := '0';
@@ -107,7 +182,7 @@ signal host_read_flag : std_logic := '0';
signal sd_write_flag : std_logic := '0';
signal host_write_flag : std_logic := '0';
signal init_busy : std_logic := '0';
signal init_busy : std_logic := '1';
signal block_busy : std_logic := '0';
signal address: std_logic_vector(31 downto 0) :=x"00000000";
@@ -115,11 +190,24 @@ signal address: std_logic_vector(31 downto 0) :=x"00000000";
signal led_on_count : integer range 0 to 200;
begin
process(n_wr)
clock_enable: process(clk)
begin
-- SDSC byte address 0..8 (first 9 bits) always zero because each sector is 512 bytes
if rising_edge(clk) then
if clkCount < (CLKEDGE_DIVIDER - 1) then
clkCount <= clkCount + 1;
else
clkCount <= (others=>'0');
end if;
end if;
end process;
clkEn <= '1' when ( clkCount = 0 ) or ( HighSpeed = '1' ) else '0';
wr_adrs_reg: process(n_wr)
begin
-- sdsc address 0..8 (first 9 bits) always zero because each sector is 512 bytes
if rising_edge(n_wr) then
if sdhc = '0' then -- SDSC card
if sdhc = '0' then -- SDSC card
if regAddr = "010" then
address(16 downto 9) <= dataIn;
elsif regAddr = "011" then
@@ -127,12 +215,12 @@ begin
elsif regAddr = "100" then
address(31 downto 25) <= dataIn(6 downto 0);
end if;
else -- SDHC card
-- SDHC block address. starts at bit 0
else -- SDHC card
-- SDHC address is the 512 bytes block address. starts at bit 0
if regAddr = "010" then
address(7 downto 0) <= dataIn; -- 128 k
address(7 downto 0) <= dataIn; -- 128 k
elsif regAddr = "011" then
address(15 downto 8) <= dataIn; -- 32 M
address(15 downto 8) <= dataIn; -- 32 M
elsif regAddr = "100" then
address(23 downto 16) <= dataIn; -- addresses upto 8 G
end if;
@@ -140,12 +228,13 @@ begin
end if;
end process;
dataOut <=
dout when regAddr = "000"
else status when regAddr = "001"
else "00000000";
-- output data is MUXed externally based on CS so only need to
-- drive 0 by default if dataOut is being ORed externally
dataOut <= dout when regAddr = "000" else
status when regAddr = "001" else
x"00";
process(n_wr)
wr_dat_reg: process(n_wr)
begin
if rising_edge(n_wr) then
if (regAddr = "000") and (sd_write_flag = host_write_flag) then
@@ -155,7 +244,7 @@ begin
end if;
end process;
process(n_rd)
rd_dat_reg: process(n_rd)
begin
if rising_edge(n_rd) then
if (regAddr = "000") and (sd_read_flag /= host_read_flag) then
@@ -164,33 +253,22 @@ begin
end if;
end process;
process(n_wr, block_start_ack,init_busy)
wr_cmd_reg: process(n_wr, block_start_ack,init_busy)
begin
if init_busy='1' then
block_read <= '0';
elsif block_start_ack='1' then
if init_busy='1' or block_start_ack='1' then
block_read <= '0';
block_write <= '0';
elsif rising_edge(n_wr) then
if regAddr = "001" and dataIn = "00000000" then
block_read <= '1';
end if;
end if;
end process;
process(n_wr, block_start_ack,init_busy)
begin
if init_busy='1' then
block_write <= '0';
elsif block_start_ack='1' then
block_write <= '0';
elsif rising_edge(n_wr) then
if regAddr = "001" and dataIn = "00000001" then
block_write <= '1';
end if;
end if;
end process;
process(clk,n_reset)
fsm: process(clk, clkEn, n_reset)
variable byte_counter : integer range 0 to write_data_size;
variable bit_counter : integer range 0 to 160;
begin
@@ -198,281 +276,271 @@ begin
state <= rst;
sclk_sig <= '0';
sdCS <= '1';
elsif rising_edge(clk) then
HighSpeed <= '0';
elsif rising_edge(clk) and clkEn = '1' then
case state is
when rst =>
sd_read_flag <= host_read_flag;
sd_write_flag <= host_write_flag;
sclk_sig <= '0';
cmd_out <= (others => '1');
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
bit_counter := 160;
sdCS <= '1';
state <= init;
when rst =>
-- HighSpeed <= '0';
sd_read_flag <= host_read_flag;
sd_write_flag <= host_write_flag;
sclk_sig <= '0';
cmd_out <= (others => '1');
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
bit_counter := 160;
sdCS <= '1';
state <= init;
init_busy <= '1';
block_start_ack <= '0';
when init => -- cs=1, send 80 clocks, cs=0
init_busy <= '1';
if (bit_counter = 0) then
sdCS <= '0';
state <= cmd0;
else
bit_counter := bit_counter - 1;
sclk_sig <= not sclk_sig;
end if;
when cmd0 =>
cmd_out <= x"ff400000000095"; -- GO_IDLE_STATE here, Select SPI
bit_counter := 55;
return_state <= regreq;
state <= send_cmd;
when regreq =>
cmd_out <= x"ff48000001aa87"; -- SEND_IF_COND, VHS=0001 (bit 16-19)
bit_counter := 55;
return_state <= cmd55;
state <= send_regreq;
when cmd55 =>
cmd_out <= x"ff770000000001"; -- APP_CMD
bit_counter := 55;
return_state <= acmd41;
state <= send_cmd;
when acmd41 =>
cmd_out <= x"ff694000000077"; -- SD_SEND_OP_COND, HCS=1 (bit 30)
bit_counter := 55;
return_state <= poll_cmd;
state <= send_cmd;
when poll_cmd =>
if (recv_data(0) = '0') then
state <= cmd58;
else
state <= cmd55;
end if;
when cmd58 =>
cmd_out <= x"ff7a00000000fd"; -- READ_OCR
bit_counter := 55;
return_state <= cardsel;
state <= send_regreq;
when cardsel =>
if (ocr_data(31) = '0' ) then -- power up not completed
state <= cmd58; -- repeat command
else
if (ocr_data(30) = '1' ) then -- CCS bit
sdhc <= '1';
else
sdhc <= '0';
end if;
state <= stby;
end if;
when stby =>
sd_read_flag <= host_read_flag;
sd_write_flag <= host_write_flag;
sclk_sig <= '0';
cmd_out <= (others => '1');
data_sig <= (others => '1');
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
block_busy <= '0';
init_busy <= '0';
dout <= (others => '0');
if (block_read = '1') then
state <= read_block_cmd;
block_start_ack <= '1';
elsif (block_write='1') then
state <= write_block_cmd;
block_start_ack <= '1';
else
state <= stby;
end if;
when read_block_cmd =>
block_busy <= '1';
block_start_ack <= '0';
cmd_out <= x"ff" & x"51" & address & x"ff";
bit_counter := 55;
return_state <= read_block_wait;
state <= send_cmd;
-- wait until data token read (= 11111110)
when read_block_wait =>
if (sclk_sig='0' and sdMISO='0') then
state <= receive_byte;
byte_counter := 513; -- data plus crc
bit_counter := 8; -- ???????????????????????????????
return_state <= read_block_data;
end if;
sclk_sig <= not sclk_sig;
when read_block_data =>
if (byte_counter = 1) then -- crc byte 1 - ignore
byte_counter := byte_counter - 1;
return_state <= read_block_data;
bit_counter := 7;
state <= receive_byte;
elsif (byte_counter = 0) then -- crc byte 2 - ignore
bit_counter := 7;
return_state <= stby;
state <= receive_byte;
elsif (sd_read_flag /= host_read_flag) then
state <= read_block_data; -- stay here until previous byte read
else
byte_counter := byte_counter - 1;
return_state <= read_block_data;
bit_counter := 7;
state <= receive_byte;
end if;
when send_cmd =>
if (sclk_sig = '1') then -- sending command
if (bit_counter = 0) then -- command sent
state <= receive_byte_wait;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when send_regreq =>
if (sclk_sig = '1') then -- sending command
if (bit_counter = 0) then -- command sent
state <= receive_ocr_wait;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when receive_ocr_wait =>
if (sclk_sig = '0') then
if (sdMISO = '0') then -- wait for zero bit
ocr_data <= (others => '0');
bit_counter := 38; -- already read bit 39
state <= receive_ocr;
end if;
end if;
sclk_sig <= not sclk_sig;
when receive_ocr =>
if (sclk_sig = '0') then
ocr_data <= ocr_data(38 downto 0) & sdMISO; -- read next bit
when init => -- cs=1, send 80 clocks, cs=0
if (bit_counter = 0) then
state <= return_state;
sdCS <= '0';
state <= cmd0;
else
bit_counter := bit_counter - 1;
sclk_sig <= not sclk_sig;
end if;
end if;
sclk_sig <= not sclk_sig;
when cmd0 =>
cmd_out <= x"ff400000000095"; -- GO_IDLE_STATE here, Select SPI
bit_counter := 55;
return_state <= cmd8;
state <= send_cmd;
when receive_byte_wait =>
if (sclk_sig = '0') then
if (sdMISO = '0') then -- wait for start of frame
recv_data <= (others => '0');
if (response_mode='0') then -- data mode
bit_counter := 3; -- already read bits 7..4
else -- command mode
bit_counter := 6; -- already read bit 7
end if;
when cmd8 =>
cmd_out <= x"ff48000001aa87"; -- SEND_IF_COND
bit_counter := 55;
return_state <= cmd55;
state <= send_regreq;
-- cmd55 is the "prefix" command for ACMDs
when cmd55 =>
cmd_out <= x"ff770000000001"; -- APP_CMD
bit_counter := 55;
return_state <= acmd41;
state <= send_cmd;
when acmd41 =>
cmd_out <= x"ff694000000077"; -- SD_SEND_OP_COND
bit_counter := 55;
return_state <= poll_cmd;
state <= send_cmd;
when poll_cmd =>
if (recv_data(0) = '0') then
state <= cmd58;
else
-- still busy; go round and do it again
state <= cmd55;
end if;
when cmd58 =>
cmd_out <= x"ff7a00000000fd"; -- READ_OCR
bit_counter := 55;
return_state <= cardsel;
state <= send_regreq;
when cardsel =>
if (recv_data(31) = '0' ) then -- power up not completed
state <= cmd58;
else
sdhc <= recv_data(30); -- CCS bit
state <= idle;
end if;
when idle =>
HighSpeed <= '1';
sd_read_flag <= host_read_flag;
sd_write_flag <= host_write_flag;
sclk_sig <= '0';
cmd_out <= (others => '1');
data_sig <= (others => '1');
byte_counter := 0;
cmd_mode <= '1'; -- 0=data, 1=command
response_mode <= '1'; -- 0=data, 1=command
block_busy <= '0';
init_busy <= '0';
dout <= (others => '0');
if (block_read = '1') then
state <= read_block_cmd;
block_start_ack <= '1';
elsif (block_write='1') then
state <= write_block_cmd;
block_start_ack <= '1';
else
state <= idle;
end if;
when read_block_cmd =>
block_busy <= '1';
block_start_ack <= '0';
cmd_out <= x"ff" & x"51" & address & x"ff"; -- CMD17 read single block
bit_counter := 55;
return_state <= read_block_wait;
state <= send_cmd;
-- wait until data token read (= 11111110)
when read_block_wait =>
if (sclk_sig='0' and sdMISO='0') then
state <= receive_byte;
byte_counter := 513; -- data plus crc
bit_counter := 8; -- ???????????????????????????????
return_state <= read_block_data;
end if;
sclk_sig <= not sclk_sig;
when read_block_data =>
if (byte_counter = 1) then -- crc byte 1 - ignore
byte_counter := byte_counter - 1;
return_state <= read_block_data;
bit_counter := 7;
state <= receive_byte;
elsif (byte_counter = 0) then -- crc byte 2 - ignore
bit_counter := 7;
return_state <= idle;
state <= receive_byte;
elsif (sd_read_flag /= host_read_flag) then
state <= read_block_data; -- stay here until previous byte read
else
byte_counter := byte_counter - 1;
return_state <= read_block_data;
bit_counter := 7;
state <= receive_byte;
end if;
end if;
sclk_sig <= not sclk_sig;
when receive_byte =>
if (sclk_sig = '0') then
recv_data <= recv_data(6 downto 0) & sdMISO; -- read next bit
if (bit_counter = 0) then
state <= return_state;
-- if real data received then flag it (byte counter = 0 for both crc bytes)
if return_state= read_block_data and byte_counter > 0 then
sd_read_flag <= not sd_read_flag;
dout <= recv_data;
when send_cmd =>
if (sclk_sig = '1') then -- sending command
if (bit_counter = 0) then -- command sent
state <= receive_byte_wait;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when send_regreq =>
if (sclk_sig = '1') then -- sending command
if (bit_counter = 0) then -- command sent
state <= receive_ocr_wait;
else
bit_counter := bit_counter - 1;
cmd_out <= cmd_out(54 downto 0) & '1';
end if;
end if;
sclk_sig <= not sclk_sig;
when receive_ocr_wait =>
if (sclk_sig = '0') then
if (sdMISO = '0') then -- wait for zero bit
recv_data <= (others => '0');
bit_counter := 38; -- already read bit 39
state <= receive_byte;
end if;
end if;
sclk_sig <= not sclk_sig;
when receive_byte_wait =>
if (sclk_sig = '0') then
if (sdMISO = '0') then -- wait for start bit
recv_data <= (others => '0');
if (response_mode='0') then -- data mode
bit_counter := 3; -- already read bits 7..4
else -- command mode
bit_counter := 6; -- already read bit 7 (start bit)
end if;
state <= receive_byte;
end if;
end if;
sclk_sig <= not sclk_sig;
-- read 8-bit data or 8-bit R1 response or 40-bit R7 response
when receive_byte =>
if (sclk_sig = '0') then
recv_data <= recv_data(38 downto 0) & sdMISO; -- read next bit
if (bit_counter = 0) then
state <= return_state;
-- if real data received then flag it (byte counter = 0 for both crc bytes)
if return_state= read_block_data and byte_counter > 0 then
sd_read_flag <= not sd_read_flag;
dout <= recv_data(7 downto 0);
end if;
else
bit_counter := bit_counter - 1;
end if;
end if;
sclk_sig <= not sclk_sig;
when write_block_cmd =>
block_busy <= '1';
block_start_ack <= '0';
cmd_mode <= '1';
cmd_out <= x"ff" & x"58" & address & x"ff"; -- CMD24 write single block
bit_counter := 55;
return_state <= write_block_init;
state <= send_cmd;
when write_block_init =>
cmd_mode <= '0';
byte_counter := write_data_size;
state <= write_block_data;
when write_block_data =>
if byte_counter = 0 then
state <= receive_byte_wait;
return_state <= write_block_wait;
response_mode <= '0';
else
bit_counter := bit_counter - 1;
if ((byte_counter = 2) or (byte_counter = 1)) then
data_sig <= x"ff"; -- two crc bytes
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
elsif byte_counter = write_data_size then
data_sig <= x"fe"; -- start byte, single block
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
elsif host_write_flag /= sd_write_flag then -- only send if flag set
data_sig <= din_latched;
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
sd_write_flag <= not sd_write_flag;
end if;
end if;
end if;
sclk_sig <= not sclk_sig;
when write_block_cmd =>
block_busy <= '1';
block_start_ack <= '0';
cmd_mode <= '1';
cmd_out <= x"ff" & x"58" & address & x"ff"; -- single block
bit_counter := 55;
return_state <= write_block_init;
state <= send_cmd;
when write_block_init =>
cmd_mode <= '0';
byte_counter := write_data_size;
state <= write_block_data;
when write_block_data =>
if byte_counter = 0 then
state <= receive_byte_wait;
return_state <= write_block_wait;
response_mode <= '0';
else
if ((byte_counter = 2) or (byte_counter = 1)) then
data_sig <= x"ff"; -- two crc bytes
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
elsif byte_counter = write_data_size then
data_sig <= x"fe"; -- start byte, single block
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
elsif host_write_flag /= sd_write_flag then -- only send if flag set
data_sig <= din_latched;
bit_counter := 7;
state <= write_block_byte;
byte_counter := byte_counter - 1;
sd_write_flag <= not sd_write_flag;
when write_block_byte =>
if (sclk_sig = '1') then
if bit_counter=0 then
state <= write_block_data;
else
data_sig <= data_sig(6 downto 0) & '1';
bit_counter := bit_counter - 1;
end if;
end if;
end if;
sclk_sig <= not sclk_sig;
when write_block_byte =>
if (sclk_sig = '1') then
if bit_counter=0 then
state <= write_block_data;
else
data_sig <= data_sig(6 downto 0) & '1';
bit_counter := bit_counter - 1;
when write_block_wait =>
cmd_mode <= '1';
response_mode <= '1';
if sclk_sig='0' then
if sdMISO='1' then
state <= idle;
end if;
end if;
end if;
sclk_sig <= not sclk_sig;
sclk_sig <= not sclk_sig;
when write_block_wait =>
cmd_mode <= '1';
response_mode <= '1';
if sclk_sig='0' then
if sdMISO='1' then
state <= stby;
end if;
end if;
sclk_sig <= not sclk_sig;
when others =>
state <= stby;
end case;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
sdSCLK <= sclk_sig;
@@ -484,11 +552,11 @@ begin
status(4) <= init_busy;
-- Make sure the drive LED is on for a visible amount of time
process (clk, block_busy,init_busy)
ctl_led: process (clk, block_busy,init_busy)
begin
if block_busy='1' or init_busy = '1' then
led_on_count <= 200; -- ensure on for at least 200ms (assuming 1MHz clk)
driveLED <= '0';
led_on_count <= 200; -- ensure on for at least 200ms (assuming 1MHz clk)
driveLED <= '0';
elsif (rising_edge(clk)) then
if led_on_count>0 then
led_on_count <= led_on_count-1;

3
Components/TERMINAL/CGABoldRomReduced.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "CGABoldRomReduced.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "CGABoldRomReduced.cmp"]

62
Components/TERMINAL/CGABoldRomReduced.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY CGABoldRomReduced IS
PORT
@@ -53,40 +54,16 @@ ARCHITECTURE SYN OF cgaboldromreduced IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../Components/TERMINAL/CGAFontBoldReduced.HEX",
intended_device_family => "Cyclone II",
init_file => "./Components/TERMINAL/CGAFontBoldReduced.HEX",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
@@ -123,11 +100,11 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Components/TERMINAL/CGAFontBoldReduced.HEX"
-- Retrieval info: PRIVATE: MIFfilename STRING "./Components/TERMINAL/CGAFontBoldReduced.HEX"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -139,10 +116,11 @@ END SYN;
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Components/TERMINAL/CGAFontBoldReduced.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./Components/TERMINAL/CGAFontBoldReduced.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"

3
Components/TERMINAL/DisplayRam1K.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "DisplayRam1K.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "DisplayRam1K.cmp"]

85
Components/TERMINAL/DisplayRam1K.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY DisplayRam1K IS
PORT
@@ -60,48 +61,6 @@ ARCHITECTURE SYN OF displayram1k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
@@ -114,7 +73,7 @@ BEGIN
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
@@ -125,6 +84,8 @@ BEGIN
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 8,
@@ -134,13 +95,13 @@ BEGIN
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
clock0 => clock,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
@@ -178,7 +139,7 @@ END SYN;
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
@@ -218,7 +179,7 @@ END SYN;
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
@@ -229,6 +190,8 @@ END SYN;
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

3
Components/TERMINAL/DisplayRam2K.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "DisplayRam2K.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "DisplayRam2K.cmp"]

85
Components/TERMINAL/DisplayRam2K.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY DisplayRam2K IS
PORT
@@ -60,48 +61,6 @@ ARCHITECTURE SYN OF displayram2k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
@@ -114,7 +73,7 @@ BEGIN
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
@@ -125,6 +84,8 @@ BEGIN
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
@@ -134,13 +95,13 @@ BEGIN
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
clock0 => clock,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
@@ -178,7 +139,7 @@ END SYN;
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
@@ -218,7 +179,7 @@ END SYN;
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
@@ -229,6 +190,8 @@ END SYN;
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

64
Components/USB/ch376s.v Normal file
View File

@@ -0,0 +1,64 @@
module ch376s_module
(
// interface
input clk, // input clock
input rd,
input wr,
input reset,
input a0,
// SPI wires
output sck, // SCK
output sdcs, // SCS
output sdo, // MOSI
input sdi, // MISO
// data
input [7:0] din,
output[7:0] dout
);
reg [2:0] mycnt;
initial mycnt = 0;
always @(posedge clk) begin
mycnt <= mycnt + 1'b1;
end
assign sck = mycnt[0];
assign sdo = mycnt[1];
assign sdcs = mycnt[2];
/*
wire _ready;
wire [7:0] _dout;
spi SPI_Master
(
// Control/Data Signals,
.clk (clk), // FPGA Clock
.reset (reset),
.ready (_ready),
// TX (MOSI) Signals
.din (din), // Byte to transmit on MOSI
.wr (wr), // Data Valid Pulse with i_TX_Byte
// RX (MISO) Signals
.dout (_dout), // Byte received on MISO
.rd (rd),
// SPI Interface
.sck (sck),
.sdi (sdi),
.sdo (sdo),
.sdcs (sdcs)
);
// zero when not rd
// when a0 is 1 show status, bit 0 signals ready state.
// when a0 is 0 show received data
assign dout = (rd ? (a0 ? {7'b0000000,_ready} : _dout) : 8'b00000000);
*/
endmodule

89
Components/USB/spi_master_simple.v Normal file
View File

@@ -0,0 +1,89 @@
// part of NeoGS project (c) 2007-2008 NedoPC
//
// SPI mode 0 8-bit master module
//
// short diagram for speed=0 (Fclk/Fspi=2, no rdy shown)
//
// clk: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (positive edges)
// counter: 00|00|00|10|11|12|13|14|15|16|17|18|19|1A|1B|1C|1D|1E|1F|00|00|00 // internal!
// sck: ___________/``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\_______
// sdo: --------< do7 | do6 | do5 | do4 | do3 | do2 | do1 | do0 >-------
// sdi: --------< di7 | di6 | di5 | di4 | di3 | di2 | di1 | di0 >-------
// bsync: ________/`````\_________________________________________________
// start: _____/``\_______________________________________________________
// din: -----<IN>-------------------------------------------------------
// dout: old old old old old old old old old old old old old | new new new
//
// data on sdo must be latched by slave on rising sck edge. data on sdo changes on falling edge of sck
//
// data from sdi is latched by master on positive edge of sck, while slave changes it on falling edge.
// WARNING: slave must emit valid di7 bit BEFORE first pulse on sck!
//
// start is synchronous pulse, which starts all transfer and also latches din data on the same clk edge
// as it is registered high. start can be given anytime (only when speed=0),
// so it is functioning then as synchronous reset. when speed!=0, there is global enable for majority of
// flipflops in the module, so start can't be accepted at any time
//
// dout updates with freshly received data at the clk edge in which sck goes high for the last time, thus
// latching last bit on sdi.
//
// sdo emits last bit shifted out after the transfer end
module spi
(
// interface
input clk, // system clock
input rd,
input wr,
input reset,
// SPI wires
output sck, // SCK
output sdcs, // SCS
output reg sdo, // MOSI
input sdi, // MISO
// data
input [7:0] din,
output reg [7:0] dout,
// output
output ready // start strobe, 1 clock length
);
reg [4:0] counter;
assign sck = counter[0];
assign sdcs = 1'b0; // slave always selected
assign ready = counter[4]; // 0 - transmission in progress
always @(posedge clk) begin
reg [7:0] shift;
if (reset) begin
counter[4] <= 5'b0;
end
else if (wr) begin
counter <= 5'b0;
sdo <= din[7];
shift[7:1] <= din[6:0];
end
else if (!ready) begin
counter <= counter + 5'd1;
// shift in (rising edge of SCK)
if (!sck) begin
shift[0] <= sdi;
if (&counter[3:1]) dout <= {shift[7:1], sdi};
end
// shift out (falling edge of sck)
if (sck) begin
sdo <= shift[7];
shift[7:1] <= shift[6:0]; // last bit remains after end of exchange
end
end
end
endmodule

6
Microcomputer6502Basic.vhd
View File

@@ -187,9 +187,9 @@ port map (
io2 : entity work.bufferedUART
port map(
clk => clk,
n_wr => n_interface1CS or cpuClock or n_WR,
n_rd => n_interface1CS or cpuClock or (not n_WR),
n_int => n_int1,
n_wr => n_interface2CS or cpuClock or n_WR,
n_rd => n_interface2CS or cpuClock or (not n_WR),
n_int => n_int2,
regSel => cpuAddress(0),
dataIn => cpuDataOut,
dataOut => interface2DataOut,

6
Microcomputer6809Basic.vhd
View File

@@ -185,9 +185,9 @@ port map (
io2 : entity work.bufferedUART
port map(
clk => clk,
n_wr => n_interface1CS or cpuClock or n_WR,
n_rd => n_interface1CS or cpuClock or (not n_WR),
n_int => n_int1,
n_wr => n_interface2CS or cpuClock or n_WR,
n_rd => n_interface2CS or cpuClock or (not n_WR),
n_int => n_int2,
regSel => cpuAddress(0),
dataIn => cpuDataOut,
dataOut => interface2DataOut,

6
MicrocomputerZ80Basic.vhd
View File

@@ -188,9 +188,9 @@ port map (
io2 : entity work.bufferedUART
port map(
clk => clk,
n_wr => n_interface1CS or cpuClock or n_WR,
n_rd => n_interface1CS or cpuClock or (not n_WR),
n_int => n_int1,
n_wr => n_interface2CS or n_ioWR,
n_rd => n_interface2CS or n_ioRD,
n_int => n_int2,
regSel => cpuAddress(0),
dataIn => cpuDataOut,
dataOut => interface2DataOut,

179
MicrocomputerZ80CPM.vhd
View File

@@ -20,11 +20,11 @@ use IEEE.STD_LOGIC_UNSIGNED.all;
entity MicrocomputerZ80CPM is
port(
N_RESET : in std_logic;
clk : in std_logic;
N_RESET : in std_logic;
clk : in std_logic;
sramData : inout std_logic_vector(7 downto 0);
sramAddress : out std_logic_vector(15 downto 0);
sramAddress : out std_logic_vector(15 downto 0);
n_sRamWE : out std_logic;
n_sRamCS : out std_logic;
n_sRamOE : out std_logic;
@@ -39,74 +39,103 @@ entity MicrocomputerZ80CPM is
txd2 : out std_logic;
rts2 : out std_logic;
videoSync : out std_logic;
videoSync : out std_logic;
video : out std_logic;
R : out std_logic_vector(1 downto 0);
G : out std_logic_vector(1 downto 0);
B : out std_logic_vector(1 downto 0);
HS : out std_logic;
VS : out std_logic;
hBlank : out std_logic;
vBlank : out std_logic;
cepix : out std_logic;
VS : out std_logic;
hBlank : out std_logic;
vBlank : out std_logic;
cepix : out std_logic;
ps2Clk : in std_logic;
ps2Data : in std_logic;
ps2Clk : in std_logic;
ps2Data : in std_logic;
sdCS : out std_logic;
sdMOSI : out std_logic;
sdMISO : in std_logic;
sdSCLK : out std_logic;
driveLED : out std_logic :='1'
sdMOSI : out std_logic;
sdMISO : in std_logic;
sdSCLK : out std_logic;
driveLED : out std_logic :='1';
usbCS : out std_logic;
usbMOSI : out std_logic;
usbMISO : in std_logic;
usbSCLK : out std_logic
);
end MicrocomputerZ80CPM;
architecture struct of MicrocomputerZ80CPM is
signal n_WR : std_logic;
signal n_RD : std_logic;
signal cpuAddress : std_logic_vector(15 downto 0);
signal cpuDataOut : std_logic_vector(7 downto 0);
signal cpuDataIn : std_logic_vector(7 downto 0);
signal n_WR : std_logic;
signal n_RD : std_logic;
signal cpuAddress : std_logic_vector(15 downto 0);
signal cpuDataOut : std_logic_vector(7 downto 0);
signal cpuDataIn : std_logic_vector(7 downto 0);
signal basRomData : std_logic_vector(7 downto 0);
signal basRomData : std_logic_vector(7 downto 0);
signal internalRam1DataOut : std_logic_vector(7 downto 0);
signal internalRam2DataOut : std_logic_vector(7 downto 0);
signal interface1DataOut : std_logic_vector(7 downto 0);
signal interface2DataOut : std_logic_vector(7 downto 0);
signal sdCardDataOut : std_logic_vector(7 downto 0);
signal ch376sDataOut : std_logic_vector(7 downto 0);
signal sdCardDataOut : std_logic_vector(7 downto 0);
signal n_memWR : std_logic :='1';
signal n_memWR : std_logic :='1';
signal n_memRD : std_logic :='1';
signal n_ioWR : std_logic :='1';
signal n_ioRD : std_logic :='1';
signal n_ioWR : std_logic :='1';
signal n_ioRD : std_logic :='1';
signal n_MREQ : std_logic :='1';
signal n_IORQ : std_logic :='1';
signal n_MREQ : std_logic :='1';
signal n_IORQ : std_logic :='1';
signal n_int1 : std_logic :='1';
signal n_int2 : std_logic :='1';
signal n_int1 : std_logic :='1';
signal n_int2 : std_logic :='1';
signal n_externalRamCS : std_logic :='1';
signal n_internalRam1CS : std_logic :='1';
signal n_internalRam2CS : std_logic :='1';
signal n_basRomCS : std_logic :='1';
signal n_basRomCS : std_logic :='1';
signal n_interface1CS : std_logic :='1';
signal n_interface2CS : std_logic :='1';
signal n_sdCardCS : std_logic :='1';
signal n_ch376sCS : std_logic :='1';
signal n_sdCardCS : std_logic :='1';
signal serialClkCount : std_logic_vector(15 downto 0);
signal cpuClkCount : std_logic_vector(5 downto 0);
signal sdClkCount : std_logic_vector(5 downto 0);
signal sdClkCount : std_logic_vector(5 downto 0);
signal cpuClock : std_logic;
signal serialClock : std_logic;
signal sdClock : std_logic;
signal sdClock : std_logic;
--CPM
signal n_RomActive : std_logic := '0';
component ch376s_module is
port (
-- interface
clk : in std_logic;
rd : in std_logic;
wr : in std_logic;
reset : in std_logic;
a0 : in std_logic;
-- SPI wires
sck : out std_logic;
sdcs : out std_logic;
sdo : out std_logic; -- reg
sdi : in std_logic;
-- data
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0) -- reg
);
end component;
begin
--CPM
-- Disable ROM if out 38. Re-enable when (asynchronous) reset pressed
@@ -174,12 +203,12 @@ port map (
-- RGB video signals
hSync => HS,
vSync => VS,
videoR0 => R(1),
videoR1 => R(0),
videoG0 => G(1),
videoG1 => G(0),
videoB0 => B(1),
videoB1 => B(0),
videoR0 => R(1),
videoR1 => R(0),
videoG0 => G(1),
videoG1 => G(0),
videoB0 => B(1),
videoB1 => B(0),
hBlank => hBlank,
vBlank => vBlank,
cepix => cepix,
@@ -196,16 +225,14 @@ port map (
dataOut => interface1DataOut,
ps2Clk => ps2Clk,
ps2Data => ps2Data
);
io2 : entity work.bufferedUART
port map(
clk => clk,
n_wr => n_interface1CS or cpuClock or n_WR,
n_rd => n_interface1CS or cpuClock or (not n_WR),
n_int => n_int1,
n_wr => n_interface2CS or n_ioWR,
n_rd => n_interface2CS or n_ioRD,
n_int => n_int2,
regSel => cpuAddress(0),
dataIn => cpuDataOut,
dataOut => interface2DataOut,
@@ -220,46 +247,64 @@ port map(
sd1 : entity work.sd_controller
port map(
sdCS => sdCS,
sdMOSI => sdMOSI,
sdMISO => sdMISO,
sdSCLK => sdSCLK,
n_wr => n_sdCardCS or n_ioWR,
n_rd => n_sdCardCS or n_ioRD,
n_reset => N_RESET,
dataIn => cpuDataOut,
dataOut => sdCardDataOut,
regAddr => cpuAddress(2 downto 0),
driveLED => driveLED,
clk => sdClock -- twice the spi clk
sdCS => sdCS,
sdMOSI => sdMOSI,
sdMISO => sdMISO,
sdSCLK => sdSCLK,
n_wr => n_sdCardCS or n_ioWR,
n_rd => n_sdCardCS or n_ioRD,
n_reset => N_RESET,
dataIn => cpuDataOut,
dataOut => sdCardDataOut,
regAddr => cpuAddress(2 downto 0),
driveLED=> driveLED,
clk => clk -- 50 MHz clock = 25 MHz SPI clock
);
usb : ch376s_module
port map (
sdcs => usbCS,
sdo => usbMOSI,
sdi => usbMISO,
sck => usbSCLK,
wr => not (n_ch376sCS or n_ioWR),
rd => not (n_ch376sCS or n_ioRD),
dout => ch376sDataOut,
din => cpuDataOut,
a0 => cpuAddress (0),
reset => not (N_RESET),
clk => sdClock -- twice the spi clk
);
-- ____________________________________________________________________________________
-- MEMORY READ/WRITE LOGIC GOES HERE
n_ioWR <= n_WR or n_IORQ;
n_ioWR <= n_WR or n_IORQ;
n_memWR <= n_WR or n_MREQ;
n_ioRD <= n_RD or n_IORQ;
n_ioRD <= n_RD or n_IORQ;
n_memRD <= n_RD or n_MREQ;
-- ____________________________________________________________________________________
-- CHIP SELECTS GO HERE
n_basRomCS <= '0' when cpuAddress(15 downto 13) = "000" and n_RomActive = '0' else '1'; --8K at bottom of memory
n_interface1CS <= '0' when cpuAddress(7 downto 1) = "1000000" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $80-$81
n_interface2CS <= '0' when cpuAddress(7 downto 1) = "1000001" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $82-$83
n_ch376sCS <= '0' when cpuAddress(7 downto 1) = "0010000" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $20-$21
n_sdCardCS <= '0' when cpuAddress(7 downto 3) = "10001" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 8 Bytes $88-$8F
n_internalRam1CS <= not n_basRomCS; -- Full Internal RAM - 64 K
-- ____________________________________________________________________________________
-- BUS ISOLATION GOES HERE
cpuDataIn <=
interface1DataOut when n_interface1CS = '0' else
interface2DataOut when n_interface2CS = '0' else
ch376sDataOut when n_ch376sCS = '0' else
sdCardDataOut when n_sdCardCS = '0' else
basRomData when n_basRomCS = '0' else
internalRam1DataOut when n_internalRam1CS= '0' else
@@ -272,6 +317,8 @@ x"FF";
-- SUB-CIRCUIT CLOCK SIGNALS
serialClock <= serialClkCount(15);
--sdClock <= clk;
process (clk)
begin
if rising_edge(clk) then
@@ -281,23 +328,23 @@ begin
else
cpuClkCount <= (others=>'0');
end if;
if cpuClkCount < 2 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
if cpuClkCount < 4 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
cpuClock <= '0';
else
cpuClock <= '1';
end if;
if sdClkCount < 49 then -- 1MHz
if sdClkCount < 16 then -- 5MHz
sdClkCount <= sdClkCount + 1;
else
sdClkCount <= (others=>'0');
end if;
if sdClkCount < 25 then
sdClock <= '0';
else
sdClock <= '1';
end if;
sdClock <= sdClkCount (3); -- divide by 8 = 6.25 Mhz
--usbCS <= sdClkCount (4);
--usbMOSI <= sdClkCount (3);
--usbSCLK <= sdClkCount (2);
-- Serial clock DDS
-- 50MHz master input clock:

4
MultiComp.qpf
View File

@@ -19,12 +19,12 @@
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 09:46:14 June 22, 2018
# Date created = 16:36:47 November 15, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "09:46:14 June 22, 2018"
DATE = "16:36:47 November 15, 2020"
# Revisions

313
MultiComp.qsf
View File

@@ -23,24 +23,18 @@
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
@@ -50,11 +44,40 @@ set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
#set_global_assignment -name VERILOG_MACRO "ARCADE_SYS=1"
#set_global_assignment -name VERILOG_MACRO "USE_FB=1"
#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1"
#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1"
#do not enable DEBUG_NOHDMI in release!
# set_global_assignment -name VERILOG_MACRO "DEBUG_NOHDMI=1"
source sys/sys.tcl
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
@@ -63,100 +86,28 @@ set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
set_location_assignment PIN_U14 -to IO_SCL
set_location_assignment PIN_AG9 -to IO_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S*
set_location_assignment PIN_AF17 -to USER_IO[6]
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
set_location_assignment PIN_AH7 -to SDCD_SPDIF
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
@@ -172,7 +123,6 @@ set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
@@ -191,88 +141,42 @@ set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_AE15 -to SD_SPI_CS
set_location_assignment PIN_AH8 -to SD_SPI_MISO
set_location_assignment PIN_AG8 -to SD_SPI_CLK
set_location_assignment PIN_U13 -to SD_SPI_MOSI
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
@@ -308,18 +212,10 @@ set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
@@ -336,10 +232,6 @@ set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
@@ -348,12 +240,64 @@ set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_hps_location_assignment HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -to spi
set_hps_location_assignment HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -to uart
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
source sys/sys_analog.tcl
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
set_global_assignment -name VERILOG_FILE Components/USB/spi_master_simple.v
set_global_assignment -name VERILOG_FILE Components/USB/ch376s.v
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name SYSTEMVERILOG_FILE MultiComp.sv
set_global_assignment -name VHDL_FILE Components/M6809/cpu09l.vhd
set_global_assignment -name VHDL_FILE Components/TERMINAL/SBCTextDisplayRGB.vhd
@@ -383,4 +327,5 @@ set_global_assignment -name QIP_FILE ROMS/Z80/Z80_CPM_BASIC_ROM.qip
set_global_assignment -name VHDL_FILE MicrocomputerZ80CPM.vhd
set_global_assignment -name VHDL_FILE Microcomputer6502Basic.vhd
set_global_assignment -name VHDL_FILE Microcomputer6809Basic.vhd
set_global_assignment -name VHDL_FILE MicrocomputerZ80Basic.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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MultiComp.qws Normal file
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323
MultiComp.sv
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@@ -36,7 +36,7 @@ module emu
input RESET,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
inout [45:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
@@ -55,6 +55,35 @@ module emu
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
/*
// Use framebuffer from DDRAM (USE_FB=1 in qsf)
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of 16 bytes.
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
*/
output LED_USER, // 1 - ON, 0 - OFF.
@@ -64,13 +93,21 @@ module emu
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
input TAPE_IN,
// SD-SPI
//ADC
inout [3:0] ADC_BUS,
//SD-SPI SECONDARY SDCARD
output SD_SCK,
output SD_MOSI,
input SD_MISO,
@@ -101,33 +138,64 @@ module emu
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign LED_USER = 0;
assign UART_RTS = UART_CTS;
assign UART_DTR = UART_DSR;
assign LED_USER = vsd_sel & sd_act;
assign LED_DISK = ~driveLED;
assign LED_POWER = 0;
assign BUTTONS = 0;
assign VIDEO_ARX = 4;
assign VIDEO_ARY = 3;
assign VGA_SL = 0;
assign VGA_F1 = 0;
assign AUDIO_S = 0;
assign AUDIO_L = 0;
assign AUDIO_R = 0;
assign AUDIO_MIX = 0;
// enable input on USER_IO[3] for ch376s MISO
assign USER_OUT[3] = 1'b1;
`include "build_id.v"
localparam CONF_STR = {
"MultiComp;;",
"S,IMG;",
"OE,Reset after Mount,No,Yes;",
"-;",
"O78,CPU-ROM,Z80-CP/M,6502-Basic,6809-Basic;",
"O78,CPU-ROM,Z80-CP/M,Z80-BASIC,6502-Basic,6809-Basic;",
"-;",
"V,v1.1.",`BUILD_DATE
"RA,Reset;",
"V,v",`BUILD_DATE
};
////////////////// HPS I/O ///////////////////
wire [1:0] buttons;
wire [31:0] status;
@@ -146,8 +214,14 @@ wire [7:0] sd_buff_dout;
wire [7:0] sd_buff_din;
wire sd_buff_wr;
wire sd_ack_conf;
wire img_mounted;
wire img_readonly;
wire [63:0] img_size;
hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
hps_io #(
.STRLEN($size(CONF_STR)>>3),
.PS2DIV (2000)
) hps_io
(
.clk_sys(CLK_50M),
.HPS_BUS(HPS_BUS),
@@ -159,18 +233,91 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.forced_scandoubler(forced_scandoubler),
.ps2_kbd_clk_out(PS2_CLK),
.ps2_kbd_data_out(PS2_DAT)
.ps2_kbd_data_out(PS2_DAT),
.sd_lba(sd_lba),
.sd_rd(sd_rd),
.sd_wr(sd_wr),
.sd_ack(sd_ack),
.sd_ack_conf(sd_ack_conf),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din(sd_buff_din),
.sd_buff_wr(sd_buff_wr),
.img_mounted(img_mounted),
.img_readonly(img_readonly),
.img_size(img_size),
.uart_mode(16'b000_11111_000_11111)
);
/////////////////////// CLOCKS ///////////////////////////////
wire clk_sys, locked;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.locked(locked)
);
///////////////// RESET /////////////////////////
wire reset = RESET | status[0] | buttons[1];
wire reset = RESET | status[0] | buttons[1] | status[10] | (status[14] && img_mounted);
///////////////// SDCARD ////////////////////////
wire sdclk;
wire sdmosi;
wire sdmiso = vsd_sel ? vsdmiso : SD_MISO;
wire sdss;
wire vsdmiso;
reg vsd_sel = 0;
always @(posedge clk_sys) if(img_mounted) vsd_sel <= |img_size;
sd_card sd_card
(
.*,
.clk_spi(clk_sys),
.sdhc(1),
.sck(sdclk),
.ss(sdss | ~vsd_sel),
.mosi(sdmosi),
.miso(vsdmiso)
);
assign SD_CS = sdss | vsd_sel;
assign SD_SCK = sdclk & ~vsd_sel;
assign SD_MOSI = sdmosi & ~vsd_sel;
reg sd_act;
always @(posedge clk_sys) begin
reg old_mosi, old_miso;
integer timeout = 0;
old_mosi <= sdmosi;
old_miso <= sdmiso;
sd_act <= 0;
if(timeout < 1000000) begin
timeout <= timeout + 1;
sd_act <= 1;
end
if((old_mosi ^ sdmosi) || (old_miso ^ sdmiso)) timeout <= 0;
end
///////////////////////////////////////////////////
assign CLK_VIDEO = CLK_50M;
assign CLK_VIDEO = clk_sys;
typedef enum {cpuZ80CPM='b00, cpu6502Basic='b01, cpu6809Basic='b10} cpu_type_enum;
typedef enum {cpuZ80CPM='b00, cpuZ80Basic='b01, cpu6502Basic='b10, cpu6809Basic='b11} cpu_type_enum;
wire [1:0] cpu_type = status[8:7];
wire hblank, vblank;
@@ -178,56 +325,87 @@ wire hs, vs;
wire [1:0] r,g,b;
wire driveLED;
wire [2:0] _hblank, _vblank;
wire [2:0] _hs, _vs;
wire [1:0] _r[2:0], _g[2:0], _b[2:0];
wire [2:0] _CE_PIXEL;
wire [2:0] _SD_CS;
wire [2:0] _SD_MOSI;
wire [2:0] _SD_SCK;
wire [2:0] _driveLED;
wire [3:0] _hblank, _vblank;
wire [3:0] _hs, _vs;
wire [1:0] _r[3:0], _g[3:0], _b[3:0];
wire [3:0] _driveLED;
wire [3:0] _CE_PIXEL;
wire [3:0] _SD_CS;
wire [3:0] _SD_MOSI;
wire [3:0] _SD_SCK;
wire [3:0] _txd[3:0];
always_comb
begin
hblank <= _hblank[cpu_type];
vblank <= _vblank[cpu_type];
hs <= _hs[cpu_type];
vs <= _vs[cpu_type];
r <= _r[cpu_type][1:0];
g <= _g[cpu_type][1:0];
b <= _b[cpu_type][1:0];
CE_PIXEL <= _CE_PIXEL[cpu_type];
SD_CS <= _SD_CS[cpu_type];
SD_MOSI <= _SD_MOSI[cpu_type];
SD_SCK <= _SD_SCK[cpu_type];
vs <= _vs[cpu_type];
r <= _r[cpu_type][1:0];
g <= _g[cpu_type][1:0];
b <= _b[cpu_type][1:0];
CE_PIXEL <= _CE_PIXEL[cpu_type];
sdss <= _SD_CS[cpu_type];
sdmosi <= _SD_MOSI[cpu_type];
sdclk <= _SD_SCK[cpu_type];
driveLED <= _driveLED[cpu_type];
UART_TXD <= _txd[cpu_type];
end
/*
reg [6:0] test;
reg [4:0] mycnt;
initial test = 0;
initial mycnt = 0;
always @(posedge clk_sys) begin
if (mycnt>25) begin
test <= test + 1'b1;
mycnt <= 0;
end
else begin
mycnt <= mycnt + 1'b1;
end
USER_OUT[0] <= test[0];
USER_OUT[1] <= test[1];
USER_OUT[2] <= test[2];
USER_OUT[3] <= test[3];
USER_OUT[4] <= test[4];
USER_OUT[5] <= test[5];
USER_OUT[6] <= test[6];
end
*/
MicrocomputerZ80CPM MicrocomputerZ80CPM
(
.N_RESET(~reset & cpu_type == cpuZ80CPM),
.clk(cpu_type == cpuZ80CPM ? CLK_50M : 0),
.R(_r[0][1:0]),
.G(_g[0][1:0]),
.B(_b[0][1:0]),
.HS(_hs[0]),
.VS(_vs[0]),
.hBlank(_hblank[0]),
.vBlank(_vblank[0]),
.cepix(_CE_PIXEL[0]),
.ps2Clk(PS2_CLK),
.ps2Data(PS2_DAT),
.sdCS(_SD_CS[0]),
.sdMOSI(_SD_MOSI[0]),
.sdMISO(SD_MISO),
.sdSCLK(_SD_SCK[0]),
.driveLED(_driveLED[0])
.N_RESET (~reset & cpu_type == cpuZ80CPM),
.clk (cpu_type == cpuZ80CPM ? clk_sys : 0),
.R (_r[0][1:0]),
.G (_g[0][1:0]),
.B (_b[0][1:0]),
.HS (_hs[0]),
.VS (_vs[0]),
.hBlank (_hblank[0]),
.vBlank (_vblank[0]),
.cepix (_CE_PIXEL[0]),
.ps2Clk (PS2_CLK),
.ps2Data (PS2_DAT),
.sdCS (_SD_CS[0]),
.sdMOSI (_SD_MOSI[0]),
.sdMISO (sdmiso),
.sdSCLK (_SD_SCK[0]),
.driveLED (_driveLED[0]),
.rxd1 (UART_RXD),
.txd1 (_txd[0]),
// CH376s via USERIO
.usbSCLK (USER_OUT[2]),
.usbMISO (USER_IN[3]),
.usbMOSI (USER_OUT[4]),
.usbCS (USER_OUT[5])
);
Microcomputer6502Basic Microcomputer6502Basic
MicrocomputerZ80Basic MicrocomputerZ80Basic
(
.N_RESET(~reset & cpu_type == cpu6502Basic),
.clk(cpu_type == cpu6502Basic ? CLK_50M : 0),
.N_RESET(~reset & cpu_type == cpuZ80Basic),
.clk(cpu_type == cpuZ80Basic ? clk_sys : 0),
.R(_r[1][1:0]),
.G(_g[1][1:0]),
.B(_b[1][1:0]),
@@ -240,16 +418,17 @@ Microcomputer6502Basic Microcomputer6502Basic
.ps2Data(PS2_DAT),
.sdCS(_SD_CS[1]),
.sdMOSI(_SD_MOSI[1]),
.sdMISO(SD_MISO),
.sdMISO(sdmiso),
.sdSCLK(_SD_SCK[1]),
.driveLED(_driveLED[1])
.driveLED(_driveLED[1]),
.rxd1 (UART_RXD),
.txd1 (_txd[1])
);
//Reset is not working (even on the original Grant's 6809)
Microcomputer6809Basic Microcomputer6809Basic
Microcomputer6502Basic Microcomputer6502Basic
(
.N_RESET(~reset & cpu_type == cpu6809Basic),
.clk(cpu_type == cpu6809Basic ? CLK_50M : 0),
.N_RESET(~reset & cpu_type == cpu6502Basic),
.clk(cpu_type == cpu6502Basic ? clk_sys : 0),
.R(_r[2][1:0]),
.G(_g[2][1:0]),
.B(_b[2][1:0]),
@@ -262,9 +441,35 @@ Microcomputer6809Basic Microcomputer6809Basic
.ps2Data(PS2_DAT),
.sdCS(_SD_CS[2]),
.sdMOSI(_SD_MOSI[2]),
.sdMISO(SD_MISO),
.sdMISO(sdmiso),
.sdSCLK(_SD_SCK[2]),
.driveLED(_driveLED[2])
.driveLED(_driveLED[2]),
.rxd1 (UART_RXD),
.txd1 (_txd[2])
);
//Reset is not working (even on the original Grant's 6809)
Microcomputer6809Basic Microcomputer6809Basic
(
.N_RESET(~reset & cpu_type == cpu6809Basic),
.clk(cpu_type == cpu6809Basic ? clk_sys : 0),
.R(_r[3][1:0]),
.G(_g[3][1:0]),
.B(_b[3][1:0]),
.HS(_hs[3]),
.VS(_vs[3]),
.hBlank(_hblank[3]),
.vBlank(_vblank[3]),
.cepix(_CE_PIXEL[3]),
.ps2Clk(PS2_CLK),
.ps2Data(PS2_DAT),
.sdCS(_SD_CS[3]),
.sdMOSI(_SD_MOSI[3]),
.sdMISO(sdmiso),
.sdSCLK(_SD_SCK[3]),
.driveLED(_driveLED[3]),
.rxd1 (UART_RXD),
.txd1 (_txd[3])
);
video_cleaner video_cleaner

23
README.md
View File

@@ -2,9 +2,15 @@ MISTer MultiComp
================
Port of Grant Searle's MultiComp to the MiSTer.
The MiSTer OSD allows the access to three machines:
## Z80 CP/M - SD card needed in I/O Board:
Updated by S0urceror to use MiSTer image files, use all 4 machine types and have the MiSTer
UART connected to serial interface 2 of the core. The latter allows to use the core remotely.
The MiSTer OSD allows the access to four machines:
## Z80 CP/M:
You can now use both an external SDCard and/or select the image file within MiSTer. Whatever you like.
For convenience you can use the Multicomp FPGA - CP/M Demo Disk from Obsolescence Guaranteed:
http://obsolescence.wixsite.com/obsolescence/multicomp-fpga-cpm-demo-disk
@@ -14,6 +20,19 @@ https://github.com/MiSTer-devel/Main_MiSTer/wiki/IO-Board
Using CP/M - from Grant Searle website:
http://searle.hostei.com/grant/Multicomp/cpm/fpgaCPM.html#UsingTheMachine
## Z80 Basic:
SGN, INT, ABS ,USR, FRE, INP, POS, SQR, RND ,LOG, EXP, COS, SIN, TAN, ATN, PEEK ,DEEK ,LEN, STR$, VAL ,ASC, CHR$ ,LEFT$,
RIGHT$, MID$, END, FOR, NEXT, DATA, INPUT, DIM, READ, LET, GOTO, RUN, IF, RESTORE, GOSUB, RETURN, REM, STOP, OUT, ON,
NULL, WAIT, DEF, POKE, DOKE, LINES, CLS, WIDTH, MONITOR, PRINT, CONT, LIST, CLEAR, NEW, TAB, TO, FN, SPC, THEN, NOT,
STEP, +, -, *, /, ^, AND, OR, >, <, =
PLUS my additional implementations here (making it version 4.7b):
HEX$(nn) - convert a SIGNED integer (-32768 to +32767) to a string containing the hex value
BIN$(nn) - convert a SIGNED integer (-32768 to +32767) to a string containing the binary value
&Hnn - interpret the value after the &H as a HEX value (signed 16 bit)
&Bnn - interpret the value after the &B as a BINARY value (signed 16 bit)
## 6502 Basic - No SD card support (No CSAVE/CLOAD):
END, FOR, NEXT, DATA, INPUT, DIM, READ, LET, GOTO, RUN, IF, RESTORE, GOSUB, RETURN, REM, STOP, ON, NULL, WAIT, DEF, POKE, PRINT,
CONT, LIST, CLEAR, NEW, TAB(, TO, FN, SPC(, THEN, NOT, STEP, SGN, INT, ABS, USR, FRE, POS, SQR, RND, LOG, EXP, COS, SIN, TAN, ATN,

3
ROMS/6502/M6502_BASIC_ROM.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "M6502_BASIC_ROM.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "M6502_BASIC_ROM.cmp"]

62
ROMS/6502/M6502_BASIC_ROM.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY M6502_BASIC_ROM IS
PORT
@@ -53,40 +54,16 @@ ARCHITECTURE SYN OF m6502_basic_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../ROMS/6502/BASIC.HEX",
intended_device_family => "Cyclone II",
init_file => "./ROMS/6502/BASIC.HEX",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
@@ -123,11 +100,11 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../ROMS/6502/BASIC.HEX"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMS/6502/BASIC.HEX"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -139,10 +116,11 @@ END SYN;
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../ROMS/6502/BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMS/6502/BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"

3
ROMS/6809/M6809_EXT_BASIC_ROM.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "M6809_EXT_BASIC_ROM.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "M6809_EXT_BASIC_ROM.cmp"]

62
ROMS/6809/M6809_EXT_BASIC_ROM.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY M6809_EXT_BASIC_ROM IS
PORT
@@ -53,40 +54,16 @@ ARCHITECTURE SYN OF m6809_ext_basic_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../ROMS/6809/EXT_BASIC_NO_USING.hex",
intended_device_family => "Cyclone",
init_file => "./ROMS/6809/EXT_BASIC_NO_USING.hex",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
@@ -123,11 +100,11 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../ROMS/6809/EXT_BASIC_NO_USING.hex"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMS/6809/EXT_BASIC_NO_USING.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -139,10 +116,11 @@ END SYN;
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../ROMS/6809/EXT_BASIC_NO_USING.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMS/6809/EXT_BASIC_NO_USING.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"

3
ROMS/Z80/Z80_BASIC_ROM.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Z80_BASIC_ROM.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Z80_BASIC_ROM.cmp"]

62
ROMS/Z80/Z80_BASIC_ROM.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY Z80_BASIC_ROM IS
PORT
@@ -53,40 +54,16 @@ ARCHITECTURE SYN OF z80_basic_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../ROMS/Z80/BASIC.HEX",
intended_device_family => "Cyclone",
init_file => "./ROMS/Z80/BASIC.HEX",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
@@ -123,11 +100,11 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../ROMS/Z80/BASIC.HEX"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMS/Z80/BASIC.HEX"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -139,10 +116,11 @@ END SYN;
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../ROMS/Z80/BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMS/Z80/BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"

3
ROMS/Z80/Z80_CPM_BASIC_ROM.qip
View File

@@ -1,4 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Z80_CPM_BASIC_ROM.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Z80_CPM_BASIC_ROM.cmp"]

62
ROMS/Z80/Z80_CPM_BASIC_ROM.vhd
View File

@@ -14,30 +14,31 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.altera_mf_components.all;
ENTITY Z80_CPM_BASIC_ROM IS
PORT
@@ -53,40 +54,16 @@ ARCHITECTURE SYN OF z80_cpm_basic_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../ROMS/Z80/CPM_BASIC.HEX",
intended_device_family => "Cyclone",
init_file => "./ROMS/Z80/CPM_BASIC.HEX",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
@@ -123,11 +100,11 @@ END SYN;
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../ROMS/Z80/CPM_BASIC.HEX"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMS/Z80/CPM_BASIC.HEX"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -139,10 +116,11 @@ END SYN;
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../ROMS/Z80/CPM_BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMS/Z80/CPM_BASIC.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"

BIN
Z80 CPM and bootloader (basmon)/TASM.EXE Normal file
View File

Binary file not shown.

1709
Z80 CPM and bootloader (basmon)/TASM.TXT Normal file
View File

File diff suppressed because it is too large Load Diff

579
Z80 CPM and bootloader (basmon)/TASM80.TAB Normal file
View File

@@ -0,0 +1,579 @@
"TASM Z80 Assembler. "
/****************************************************************************
/* $Id: tasm80.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the Z80 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Carl A. Wall, VE3APY.
/*
/* Class bits assigned as follows:
/* Bit-0 = Z80 (base instruction set)
/* Bit-1 = HD64180 (extended instructions)
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */
/*-------------------------------------------*/
ADC A,(HL) 8E 1 NOP 1
ADC A,(IX*) 8EDD 3 ZIX 1
ADC A,(IY*) 8EFD 3 ZIX 1
ADC A,A 8F 1 NOP 1
ADC A,B 88 1 NOP 1
ADC A,C 89 1 NOP 1
ADC A,D 8A 1 NOP 1
ADC A,E 8B 1 NOP 1
ADC A,H 8C 1 NOP 1
ADC A,L 8D 1 NOP 1
ADC A,* CE 2 NOP 1
ADC HL,BC 4AED 2 NOP 1
ADC HL,DE 5AED 2 NOP 1
ADC HL,HL 6AED 2 NOP 1
ADC HL,SP 7AED 2 NOP 1
ADD A,(HL) 86 1 NOP 1
ADD A,(IX*) 86DD 3 ZIX 1
ADD A,(IY*) 86FD 3 ZIX 1
ADD A,A 87 1 NOP 1
ADD A,B 80 1 NOP 1
ADD A,C 81 1 NOP 1
ADD A,D 82 1 NOP 1
ADD A,E 83 1 NOP 1
ADD A,H 84 1 NOP 1
ADD A,L 85 1 NOP 1
ADD A,* C6 2 NOP 1
ADD HL,BC 09 1 NOP 1
ADD HL,DE 19 1 NOP 1
ADD HL,HL 29 1 NOP 1
ADD HL,SP 39 1 NOP 1
ADD IX,BC 09DD 2 NOP 1
ADD IX,DE 19DD 2 NOP 1
ADD IX,IX 29DD 2 NOP 1
ADD IX,SP 39DD 2 NOP 1
ADD IY,BC 09FD 2 NOP 1
ADD IY,DE 19FD 2 NOP 1
ADD IY,IY 29FD 2 NOP 1
ADD IY,SP 39FD 2 NOP 1
AND (HL) A6 1 NOP 1
AND (IX*) A6DD 3 ZIX 1
AND (IY*) A6FD 3 ZIX 1
AND A A7 1 NOP 1
AND B A0 1 NOP 1
AND C A1 1 NOP 1
AND D A2 1 NOP 1
AND E A3 1 NOP 1
AND H A4 1 NOP 1
AND L A5 1 NOP 1
AND * E6 2 NOP 1
BIT *,(HL) 46CB 2 ZBIT 1
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600
BIT *,A 47CB 2 ZBIT 1
BIT *,B 40CB 2 ZBIT 1
BIT *,C 41CB 2 ZBIT 1
BIT *,D 42CB 2 ZBIT 1
BIT *,E 43CB 2 ZBIT 1
BIT *,H 44CB 2 ZBIT 1
BIT *,L 45CB 2 ZBIT 1
CALL C,* DC 3 NOP 1
CALL M,* FC 3 NOP 1
CALL NC,* D4 3 NOP 1
CALL NZ,* C4 3 NOP 1
CALL P,* F4 3 NOP 1
CALL PE,* EC 3 NOP 1
CALL PO,* E4 3 NOP 1
CALL Z,* CC 3 NOP 1
CALL * CD 3 NOP 1
CCF "" 3F 1 NOP 1
CP (HL) BE 1 NOP 1
CP (IX*) BEDD 3 ZIX 1
CP (IY*) BEFD 3 ZIX 1
CP A BF 1 NOP 1
CP B B8 1 NOP 1
CP C B9 1 NOP 1
CP D BA 1 NOP 1
CP E BB 1 NOP 1
CP H BC 1 NOP 1
CP L BD 1 NOP 1
CP * FE 2 NOP 1
CPD "" A9ED 2 NOP 1
CPDR "" B9ED 2 NOP 1
CPIR "" B1ED 2 NOP 1
CPI "" A1ED 2 NOP 1
CPL "" 2F 1 NOP 1
DAA "" 27 1 NOP 1
DEC (HL) 35 1 NOP 1
DEC (IX*) 35DD 3 ZIX 1
DEC (IY*) 35FD 3 ZIX 1
DEC A 3D 1 NOP 1
DEC B 05 1 NOP 1
DEC BC 0B 1 NOP 1
DEC C 0D 1 NOP 1
DEC D 15 1 NOP 1
DEC DE 1B 1 NOP 1
DEC E 1D 1 NOP 1
DEC H 25 1 NOP 1
DEC HL 2B 1 NOP 1
DEC IX 2BDD 2 NOP 1
DEC IY 2BFD 2 NOP 1
DEC L 2D 1 NOP 1
DEC SP 3B 1 NOP 1
DI "" F3 1 NOP 1
DJNZ * 10 2 R1 1
EI "" FB 1 NOP 1
EX (SP),HL E3 1 NOP 1
EX (SP),IX E3DD 2 NOP 1
EX (SP),IY E3FD 2 NOP 1
EX AF,AF' 08 1 NOP 1
EX DE,HL EB 1 NOP 1
EXX "" D9 1 NOP 1
HALT "" 76 1 NOP 1
IM 0 46ED 2 NOP 1
IM 1 56ED 2 NOP 1
IM 2 5EED 2 NOP 1
IN A,(C) 78ED 2 NOP 1
IN B,(C) 40ED 2 NOP 1
IN C,(C) 48ED 2 NOP 1
IN D,(C) 50ED 2 NOP 1
IN E,(C) 58ED 2 NOP 1
IN H,(C) 60ED 2 NOP 1
IN L,(C) 68ED 2 NOP 1
IN A,(*) DB 2 NOP 1
IN0 A,(*) 38ED 3 NOP 2
IN0 B,(*) 00ED 3 NOP 2
IN0 C,(*) 08ED 3 NOP 2
IN0 D,(*) 10ED 3 NOP 2
IN0 E,(*) 18ED 3 NOP 2
IN0 H,(*) 20ED 3 NOP 2
IN0 L,(*) 28ED 3 NOP 2
INC (HL) 34 1 NOP 1
INC (IX*) 34DD 3 ZIX 1
INC (IY*) 34FD 3 ZIX 1
INC A 3C 1 NOP 1
INC B 04 1 NOP 1
INC BC 03 1 NOP 1
INC C 0C 1 NOP 1
INC D 14 1 NOP 1
INC DE 13 1 NOP 1
INC E 1C 1 NOP 1
INC H 24 1 NOP 1
INC HL 23 1 NOP 1
INC IX 23DD 2 NOP 1
INC IY 23FD 2 NOP 1
INC L 2C 1 NOP 1
INC SP 33 1 NOP 1
IND "" AAED 2 NOP 1
INDR "" BAED 2 NOP 1
INI "" A2ED 2 NOP 1
INIR "" B2ED 2 NOP 1
JP (HL) E9 1 NOP 1
JP (IX) E9DD 2 NOP 1
JP (IY) E9FD 2 NOP 1
JP C,* DA 3 NOP 1
JP M,* FA 3 NOP 1
JP NC,* D2 3 NOP 1
JP NZ,* C2 3 NOP 1
JP P,* F2 3 NOP 1
JP PE,* EA 3 NOP 1
JP PO,* E2 3 NOP 1
JP Z,* CA 3 NOP 1
JP * C3 3 NOP 1
JR C,* 38 2 R1 1
JR NC,* 30 2 R1 1
JR NZ,* 20 2 R1 1
JR Z,* 28 2 R1 1
JR * 18 2 R1 1
LD (BC),A 02 1 NOP 1
LD (DE),A 12 1 NOP 1
LD (HL),A 77 1 NOP 1
LD (HL),B 70 1 NOP 1
LD (HL),C 71 1 NOP 1
LD (HL),D 72 1 NOP 1
LD (HL),E 73 1 NOP 1
LD (HL),H 74 1 NOP 1
LD (HL),L 75 1 NOP 1
LD (HL),* 36 2 NOP 1
LD (IX*),A 77DD 3 ZIX 1
LD (IX*),B 70DD 3 ZIX 1
LD (IX*),C 71DD 3 ZIX 1
LD (IX*),D 72DD 3 ZIX 1
LD (IX*),E 73DD 3 ZIX 1
LD (IX*),H 74DD 3 ZIX 1
LD (IX*),L 75DD 3 ZIX 1
LD (IX*),* 36DD 4 ZIX 1
LD (IY*),A 77FD 3 ZIX 1
LD (IY*),B 70FD 3 ZIX 1
LD (IY*),C 71FD 3 ZIX 1
LD (IY*),D 72FD 3 ZIX 1
LD (IY*),E 73FD 3 ZIX 1
LD (IY*),H 74FD 3 ZIX 1
LD (IY*),L 75FD 3 ZIX 1
LD (IY*),* 36FD 4 ZIX 1
LD (*),A 32 3 NOP 1
LD (*),BC 43ED 4 NOP 1
LD (*),DE 53ED 4 NOP 1
LD (*),HL 22 3 NOP 1
LD (*),IX 22DD 4 NOP 1
LD (*),IY 22FD 4 NOP 1
LD (*),SP 73ED 4 NOP 1
LD A,(BC) 0A 1 NOP 1
LD A,(DE) 1A 1 NOP 1
LD A,(HL) 7E 1 NOP 1
LD A,(IX*) 7EDD 3 ZIX 1
LD A,(IY*) 7EFD 3 ZIX 1
LD A,A 7F 1 NOP 1
LD A,B 78 1 NOP 1
LD A,C 79 1 NOP 1
LD A,D 7A 1 NOP 1
LD A,E 7B 1 NOP 1
LD A,H 7C 1 NOP 1
LD A,I 57ED 2 NOP 1
LD A,L 7D 1 NOP 1
LD A,R 5FED 2 NOP 1
LD A,(*) 3A 3 NOP 1
LD A,* 3E 2 NOP 1
LD B,(HL) 46 1 NOP 1
LD B,(IX*) 46DD 3 ZIX 1
LD B,(IY*) 46FD 3 ZIX 1
LD B,A 47 1 NOP 1
LD B,B 40 1 NOP 1
LD B,C 41 1 NOP 1
LD B,D 42 1 NOP 1
LD B,E 43 1 NOP 1
LD B,H 44 1 NOP 1
LD B,L 45 1 NOP 1
LD B,* 06 2 NOP 1
LD BC,(*) 4BED 4 NOP 1
LD BC,* 01 3 NOP 1
LD C,(HL) 4E 1 NOP 1
LD C,(IX*) 4EDD 3 ZIX 1
LD C,(IY*) 4EFD 3 ZIX 1
LD C,A 4F 1 NOP 1
LD C,B 48 1 NOP 1
LD C,C 49 1 NOP 1
LD C,D 4A 1 NOP 1
LD C,E 4B 1 NOP 1
LD C,H 4C 1 NOP 1
LD C,L 4D 1 NOP 1
LD C,* 0E 2 NOP 1
LD D,(HL) 56 1 NOP 1
LD D,(IX*) 56DD 3 ZIX 1
LD D,(IY*) 56FD 3 ZIX 1
LD D,A 57 1 NOP 1
LD D,B 50 1 NOP 1
LD D,C 51 1 NOP 1
LD D,D 52 1 NOP 1
LD D,E 53 1 NOP 1
LD D,H 54 1 NOP 1
LD D,L 55 1 NOP 1
LD D,* 16 2 NOP 1
LD DE,(*) 5BED 4 NOP 1
LD DE,* 11 3 NOP 1
LD E,(HL) 5E 1 NOP 1
LD E,(IX*) 5EDD 3 ZIX 1
LD E,(IY*) 5EFD 3 ZIX 1
LD E,A 5F 1 NOP 1
LD E,B 58 1 NOP 1
LD E,C 59 1 NOP 1
LD E,D 5A 1 NOP 1
LD E,E 5B 1 NOP 1
LD E,H 5C 1 NOP 1
LD E,L 5D 1 NOP 1
LD E,* 1E 2 NOP 1
LD H,(HL) 66 1 NOP 1
LD H,(IX*) 66DD 3 ZIX 1
LD H,(IY*) 66FD 3 ZIX 1
LD H,A 67 1 NOP 1
LD H,B 60 1 NOP 1
LD H,C 61 1 NOP 1
LD H,D 62 1 NOP 1
LD H,E 63 1 NOP 1
LD H,H 64 1 NOP 1
LD H,L 65 1 NOP 1
LD H,* 26 2 NOP 1
LD HL,(*) 2A 3 NOP 1
LD HL,* 21 3 NOP 1
LD I,A 47ED 2 NOP 1
LD IX,(*) 2ADD 4 NOP 1
LD IX,* 21DD 4 NOP 1
LD IY,(*) 2AFD 4 NOP 1
LD IY,* 21FD 4 NOP 1
LD L,(HL) 6E 1 NOP 1
LD L,(IX*) 6EDD 3 ZIX 1
LD L,(IY*) 6EFD 3 ZIX 1
LD L,A 6F 1 NOP 1
LD L,B 68 1 NOP 1
LD L,C 69 1 NOP 1
LD L,D 6A 1 NOP 1
LD L,E 6B 1 NOP 1
LD L,H 6C 1 NOP 1
LD L,L 6D 1 NOP 1
LD L,* 2E 2 NOP 1
LD R,A 4FED 2 NOP 1
LD SP,(*) 7BED 4 NOP 1
LD SP,HL F9 1 NOP 1
LD SP,IX F9DD 2 NOP 1
LD SP,IY F9FD 2 NOP 1
LD SP,* 31 3 NOP 1
LDD "" A8ED 2 NOP 1
LDDR "" B8ED 2 NOP 1
LDI "" A0ED 2 NOP 1
LDIR "" B0ED 2 NOP 1
NEG "" 44ED 2 NOP 1
NOP "" 00 1 NOP 1
MLT BC 4CED 2 NOP 2
MLT DE 5CED 2 NOP 2
MLT HL 6CED 2 NOP 2
MLT SP 7CED 2 NOP 2
OR (HL) B6 1 NOP 1
OR (IX*) B6DD 3 ZIX 1
OR (IY*) B6FD 3 ZIX 1
OR A B7 1 NOP 1
OR B B0 1 NOP 1
OR C B1 1 NOP 1
OR D B2 1 NOP 1
OR E B3 1 NOP 1
OR H B4 1 NOP 1
OR L B5 1 NOP 1
OR * F6 2 NOP 1
OTDM "" 8BED 2 NOP 2
OTDMR "" 9BED 2 NOP 2
OTDR "" BBED 2 NOP 1
OTIM "" 83ED 2 NOP 2
OTIMR "" 93ED 2 NOP 2
OTIR "" B3ED 2 NOP 1
OUT (C),A 79ED 2 NOP 1
OUT (C),B 41ED 2 NOP 1
OUT (C),C 49ED 2 NOP 1
OUT (C),D 51ED 2 NOP 1
OUT (C),E 59ED 2 NOP 1
OUT (C),H 61ED 2 NOP 1
OUT (C),L 69ED 2 NOP 1
OUT (*),A D3 2 NOP 1
OUT0 (*),A 39ED 3 NOP 2
OUT0 (*),B 01ED 3 NOP 2
OUT0 (*),C 09ED 3 NOP 2
OUT0 (*),D 11ED 3 NOP 2
OUT0 (*),E 19ED 3 NOP 2
OUT0 (*),H 21ED 3 NOP 2
OUT0 (*),L 29ED 3 NOP 2
OUTD "" ABED 2 NOP 1
OUTI "" A3ED 2 NOP 1
POP AF F1 1 NOP 1
POP BC C1 1 NOP 1
POP DE D1 1 NOP 1
POP HL E1 1 NOP 1
POP IX E1DD 2 NOP 1
POP IY E1FD 2 NOP 1
PUSH AF F5 1 NOP 1
PUSH BC C5 1 NOP 1
PUSH DE D5 1 NOP 1
PUSH HL E5 1 NOP 1
PUSH IX E5DD 2 NOP 1
PUSH IY E5FD 2 NOP 1
RES *,(HL) 86CB 2 ZBIT 1
RES *,(IX*) CBDD 4 ZBIT 1 0 8600
RES *,(IY*) CBFD 4 ZBIT 1 0 8600
RES *,A 87CB 2 ZBIT 1
RES *,B 80CB 2 ZBIT 1
RES *,C 81CB 2 ZBIT 1
RES *,D 82CB 2 ZBIT 1
RES *,E 83CB 2 ZBIT 1
RES *,H 84CB 2 ZBIT 1
RES *,L 85CB 2 ZBIT 1
RET "" C9 1 NOP 1
RET C D8 1 NOP 1
RET M F8 1 NOP 1
RET NC D0 1 NOP 1
RET NZ C0 1 NOP 1
RET P F0 1 NOP 1
RET PE E8 1 NOP 1
RET PO E0 1 NOP 1
RET Z C8 1 NOP 1
RETI "" 4DED 2 NOP 1
RETN "" 45ED 2 NOP 1
RL (HL) 16CB 2 NOP 1
RL (IX*) CBDD 4 ZIX 1 0 1600
RL (IY*) CBFD 4 ZIX 1 0 1600
RL A 17CB 2 NOP 1
RL B 10CB 2 NOP 1
RL C 11CB 2 NOP 1
RL D 12CB 2 NOP 1
RL E 13CB 2 NOP 1
RL H 14CB 2 NOP 1
RL L 15CB 2 NOP 1
RLA "" 17 1 NOP 1
RLC (HL) 06CB 2 NOP 1
RLC (IX*) CBDD 4 ZIX 1 0 0600
RLC (IY*) CBFD 4 ZIX 1 0 0600
RLC A 07CB 2 NOP 1
RLC B 00CB 2 NOP 1
RLC C 01CB 2 NOP 1
RLC D 02CB 2 NOP 1
RLC E 03CB 2 NOP 1
RLC H 04CB 2 NOP 1
RLC L 05CB 2 NOP 1
RLCA "" 07 1 NOP 1
RLD "" 6FED 2 NOP 1
RR (HL) 1ECB 2 NOP 1
RR (IX*) CBDD 4 ZIX 1 0 1E00
RR (IY*) CBFD 4 ZIX 1 0 1E00
RR A 1FCB 2 NOP 1
RR B 18CB 2 NOP 1
RR C 19CB 2 NOP 1
RR D 1ACB 2 NOP 1
RR E 1BCB 2 NOP 1
RR H 1CCB 2 NOP 1
RR L 1DCB 2 NOP 1
RRA "" 1F 1 NOP 1
RRC (HL) 0ECB 2 NOP 1
RRC (IX*) CBDD 4 ZIX 1 0 0E00
RRC (IY*) CBFD 4 ZIX 1 0 0E00
RRC A 0FCB 2 NOP 1
RRC B 08CB 2 NOP 1
RRC C 09CB 2 NOP 1
RRC D 0ACB 2 NOP 1
RRC E 0BCB 2 NOP 1
RRC H 0CCB 2 NOP 1
RRC L 0DCB 2 NOP 1
RRCA "" 0F 1 NOP 1
RRD "" 67ED 2 NOP 1
RST 00H C7 1 NOP 1
RST 08H CF 1 NOP 1
RST 10H D7 1 NOP 1
RST 18H DF 1 NOP 1
RST 20H E7 1 NOP 1
RST 28H EF 1 NOP 1
RST 30H F7 1 NOP 1
RST 38H FF 1 NOP 1
SBC A,(HL) 9E 1 NOP 1
SBC A,(IX*) 9EDD 3 ZIX 1
SBC A,(IY*) 9EFD 3 ZIX 1
SBC A,A 9F 1 NOP 1
SBC A,B 98 1 NOP 1
SBC A,C 99 1 NOP 1
SBC A,D 9A 1 NOP 1
SBC A,E 9B 1 NOP 1
SBC A,H 9C 1 NOP 1
SBC A,L 9D 1 NOP 1
SBC HL,BC 42ED 2 NOP 1
SBC HL,DE 52ED 2 NOP 1
SBC HL,HL 62ED 2 NOP 1
SBC HL,SP 72ED 2 NOP 1
SBC A,* DE 2 NOP 1
SCF "" 37 1 NOP 1
SET *,(HL) C6CB 2 ZBIT 1
SET *,(IX*) CBDD 4 ZBIT 1 0 C600
SET *,(IY*) CBFD 4 ZBIT 1 0 C600
SET *,A C7CB 2 ZBIT 1
SET *,B C0CB 2 ZBIT 1
SET *,C C1CB 2 ZBIT 1
SET *,D C2CB 2 ZBIT 1
SET *,E C3CB 2 ZBIT 1
SET *,H C4CB 2 ZBIT 1
SET *,L C5CB 2 ZBIT 1
SLA (HL) 26CB 2 NOP 1
SLA (IX*) CBDD 4 ZIX 1 0 2600
SLA (IY*) CBFD 4 ZIX 1 0 2600
SLA A 27CB 2 NOP 1
SLA B 20CB 2 NOP 1
SLA C 21CB 2 NOP 1
SLA D 22CB 2 NOP 1
SLA E 23CB 2 NOP 1
SLA H 24CB 2 NOP 1
SLA L 25CB 2 NOP 1
SLP "" 76ED 2 NOP 2
SRA (HL) 2ECB 2 NOP 1
SRA (IX*) CBDD 4 ZIX 1 0 2E00
SRA (IY*) CBFD 4 ZIX 1 0 2E00
SRA A 2FCB 2 NOP 1
SRA B 28CB 2 NOP 1
SRA C 29CB 2 NOP 1
SRA D 2ACB 2 NOP 1
SRA E 2BCB 2 NOP 1
SRA H 2CCB 2 NOP 1
SRA L 2DCB 2 NOP 1
SRL (HL) 3ECB 2 NOP 1
SRL (IX*) CBDD 4 ZIX 1 0 3E00
SRL (IY*) CBFD 4 ZIX 1 0 3E00
SRL A 3FCB 2 NOP 1
SRL B 38CB 2 NOP 1
SRL C 39CB 2 NOP 1
SRL D 3ACB 2 NOP 1
SRL E 3BCB 2 NOP 1
SRL H 3CCB 2 NOP 1
SRL L 3DCB 2 NOP 1
SUB (HL) 96 1 NOP 1
SUB (IX*) 96DD 3 ZIX 1
SUB (IY*) 96FD 3 ZIX 1
SUB A 97 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB * D6 2 NOP 1
TST A 3CED 2 NOP 2
TST B 04ED 2 NOP 2
TST C 0CED 2 NOP 2
TST D 14ED 2 NOP 2
TST E 1CED 2 NOP 2
TST H 24ED 2 NOP 2
TST L 2CED 2 NOP 2
TST (HL) 34ED 2 NOP 2
TST * 64ED 3 NOP 2
TSTIO * 74ED 3 NOP 2
XOR (HL) AE 1 NOP 1
XOR (IX*) AEDD 3 ZIX 1
XOR (IY*) AEFD 3 ZIX 1
XOR A AF 1 NOP 1
XOR B A8 1 NOP 1
XOR C A9 1 NOP 1
XOR D AA 1 NOP 1
XOR E AB 1 NOP 1
XOR H AC 1 NOP 1
XOR L AD 1 NOP 1
XOR * EE 2 NOP 1

199
Z80 CPM and bootloader (basmon)/TASM_RELNOTES.TXT Normal file
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TASM RELEASE NOTES
RELEASE DATE/VERSION DESCRIPTION
-----------------------------------------------------------------------
10/01/85 Version 2.0 First version with external table def files.
01/01/86 Version 2.1 Added '*=' and '=' directives as
alternatives to .ORG and .EQU (for
more complete MOS Technology compatibility).
Enhanced parsing algorithm so it can
deal with more than one variable expression.
Added -d option
02/14/86 Version 2.2 Modified so instruction set definition
tables don't need to be compiled in.
Added 8051 tables.
Increased the number of labels allowed.
03/31/87 Version 2.3 Fixed bug that prevented location 0xffff
from being used and written to object file.
Most changes in wrtobj() and pr_hextab().
05/01/87 Version 2.4 Added multiple byte opcode support.
Added shift/or operation capability to
args from instruction set definition table.
Converted to MS C version 3.0
Added hashing to instruction set table
lookups to speed up.
11/01/87 Version 2.5 Added DB and DW directives.
Added escape capability in TEXT strings.
Fixed inst_lookup function to treat the
multiple wild card case a little better
Added 8080/8085 and Z80 tables.
Added sorting on label table.
Increased size of read buffer.
Speed enhancements.
Added DEFCONT (macro continuation) directive.
Converted to Microsoft C 5.0 compiler.
Added 6805 table (and related modops).
Added Z80 bit modop.
Minor speed up.
Fixed bug that enters infinite loop
when a macro invocation has no closing paren.
Added some three arg MODOPs.
8/15/88 Version 2.6.1 Added CODES/NOCODES directives
Fixed bug preventing directives in multiple
statement lines.
2.6.2 Added COMB_NIBBLE and COMB_NIBBLE_SWAP MODOPS
2/1/89 Version 2.7 Removed ad hoc heap and now use malloc()
Added MSFIRST and LSFIRST directives.
Added EXPORT directive.
Added symbol table file (-s flag).
Added NSEG/CSEG/BSEG/DSEG/XSEG directives
and the SYM/AVSYM directives to support
the Avocet avsim51 simulator.
Added support for TMS320.
Added -r flag to set read buffer size.
Converted expression evaluation from
signed 16 bit to signed 32 bit (enabling
apparent ability to use signed or unsigned
16 bit values).
4/20/89 Version 2.7.1 Return 0x20000 for undefined labels so that
(label+x) type stuff won't confuse zero
page addressing.
Added duplicate label error message on pass 1.
6/20/89 Version 2.7.2 Improved macro expansion capability.
No expansion in comments.
Context sensitive identifiers.
Revised exit codes.
6/27/89 Version 2.7.3 Added -a flag for strict error checking:
(1) No outer parens around expressions.
(2) Error message if unused argbytes remain
(3) Duplicate labels
Fixed so ']' can terminate expressions.
Removed parse() from tasm.c
8/19/89 Version 2.7.4 Added Motorola hex object format.
Fixed bug that complained when \ immediately
followed a opcode with no args.
Slightly improved error reporting (Errorbuf).
10/31/89 Version 2.7.5 Added TMS7000 support.
Fixed argv[] bug (only dimensioned to 10 in pass1.
12/23/89 Version 2.7.6 Improved handling of % (modulo vs binary
prefix ambiguity).
Fixed list so lines with more than
6 bytes go on second line.
03/04/90 Version 2.7.7 Fixed bug that left off 2 bytes if ORG
went backwards and all 64K was used.
Added a command line option to ignore
case on labels.
Added a couple MODOP rules for TMS9900.
Allow double quoted text strings for BYTE.
04/15/90 Version 2.7.8 Fixed expression evaluator bug (paren popping)
and changed expression evaluator to a more
conventional left to right evaluation order.
Added TURBOC ifdef's (from Lance Jump).
08/20/90 Version 2.8 Primarily a documentation update.
Added error check for AJMP/ACALL off of
current 2K block (8051).
10/15/90 Version 2.8.1 Minor speed up in label searching.
Fixed word addressing for TMS320
Version 2.8.2 Local labels.
More label table format options (long form
suppress local labels).
11/30/90 Version 2.8.3 Turbo C conversion.
DS directive added.
12/27/90 Version 2.8.4 Added COMMENTCHAR directive to change the
comment indicator in the first column.
This was done to support the assembly
files from the small C compiler (sc11)
for the 68CH11.
02/14/91 Version 2.8.5 Added LOCALLABELCHAR directive to
override the default "_" as the
prefix for local labels.
03/18/91 Version 2.8.6 Added some MODOPs in support of TMS320C25
04/20/91 Version 2.8.7 Fixed sign extend bug in CSWAP modop.
Increased MAXLABS to 10000 for big version.
05/05/91 Version 2.8.8 Fixed pointer bug in debug output in sort_labels().
05/20/91 Version 2.9 TMS320C25 table along with some MODOP enhancements
for it.
TASMTABS.DOC updated (but not TASM.DOC)
08/09/91 Version 2.9.1 Nested conditionals.
04/01/92 Version 2.9.2 Fixed long label clobber problem in
find_label() and save_label. Syntax
errors could result in a comment line
after an instruction being lumped together
with a label resulting in a long label.
The label functions were not testing for
labels that exceed the specified size.
Added CHK directive.
Added REL3 MODOD to support uPD75xxx.
Delinting and more ANSIfication.
Modifications due to feedback from B Provo:
Added FILL directive.
Allow multiple labels for EXPORT directive.
Allow address with END directive.
TASM.DOC update
11/25/92 Version 2.9.3 Improved error reporting for mismatched quotes.
Disallow the single quote character constants.
Convert to BCC++ 3.1
Provide filename,linenum on all error messages.
Modify format of error messages for compatibility
with the Brief editor.
Added ECHO directive to send output to console.
Performance improvements in macro processing.
"Type Safe" conversion (compatible with C++).
Improved error reporting for imbalanced ifdefs.
01/29/93 Version 2.9.4 Added rules for 8096 (I1,I2,I3,I4,I5,I6).
Generate error message on forward reference
in EQUate statements.
Eliminated -a option for enabling the detection
of branches of 2K page for 8051. This
is now built into the table.
Allow white space in double quotes for BYTE
directive. This previously worked for TEXT,
but not BYTE.
Fixed defect with Z80 4 byte indexed instructions.
Fixed macro defect. If the macro definition has
args but the invocation does not some garbage
gets expanded into the source line.
Z80 OTDR opcode was incorrect.
Z80 IN0/OUT0/INA instructions did not require
the parens around the args.
Some experimental support for windows verson of TASM.
10/24/93 Version 3.0 Documentation update. TASM.DOC, TASMTABS.DOC
and RELNOTES.DOC updated, but the functionality
remains unchanged from version 2.9.4.
06/16/94 Version 3.0.1 SPR 1006: Multiple macros on the same line
SPR 1007: -c with >8000h bytes used goes bonkers
SPR 1009: waddr correction for BLOCK/DS
SPR 1011: Escaped quotes in TEXT


8
Z80 CPM and bootloader (basmon)/_ASSEMBLE.BAT Normal file
View File

@@ -0,0 +1,8 @@
tasm -80 source\basMon.asm hexFiles\basMon.hex
tasm -80 source\cbios128.asm hexFiles\cbios128.hex
tasm -80 source\cpm22.asm hexFiles\cpm22.hex
tasm -80 source\form128.asm hexFiles\form128.hex
tasm -80 source\putsys.asm hexFiles\putsys.hex
tasm -80 source\download.asm hexFiles\download.hex
pause

343
Z80 CPM and bootloader (basmon)/hexFiles/BASMON.HEX Normal file
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@@ -0,0 +1,343 @@
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0001 0000 ;==================================================================================
0002 0000 ; Contents of this file are copyright Grant Searle
0003 0000 ; Blocking/unblocking routines are the published version by Digital Research
0004 0000 ; (bugfixed, as found on the web)
0005 0000 ;
0006 0000 ; You have permission to use this for NON COMMERCIAL USE ONLY
0007 0000 ; If you wish to use it elsewhere, please include an acknowledgement to myself.
0008 0000 ;
0009 0000 ; http://searle.hostei.com/grant/index.html
0010 0000 ;
0011 0000 ; eMail: home.micros01@btinternet.com
0012 0000 ;
0013 0000 ; If the above don't work, please perform an Internet search to see if I have
0014 0000 ; updated the web page hosting service.
0015 0000 ;
0016 0000 ;==================================================================================
0017 0000
0018 0000 ccp .EQU 0D000h ; Base of CCP.
0019 0000 bdos .EQU ccp + 0806h ; Base of BDOS.
0020 0000 bios .EQU ccp + 1600h ; Base of BIOS.
0021 0000
0022 0000 ; Set CP/M low memory datA, vector and buffer addresses.
0023 0000
0024 0000 iobyte .EQU 03h ; Intel standard I/O definition byte.
0025 0000 userdrv .EQU 04h ; Current user number and drive.
0026 0000 tpabuf .EQU 80h ; Default I/O buffer and command line storage.
0027 0000
0028 0000
0029 0000 SD_DATA .EQU 088H
0030 0000 SD_CONTROL .EQU 089H
0031 0000 SD_STATUS .EQU 089H
0032 0000 SD_LBA0 .EQU 08AH
0033 0000 SD_LBA1 .EQU 08BH
0034 0000 SD_LBA2 .EQU 08CH
0035 0000
0036 0000 RTS_HIGH .EQU 0D5H
0037 0000 RTS_LOW .EQU 095H
0038 0000
0039 0000 ACIA0_D .EQU $81
0040 0000 ACIA0_C .EQU $80
0041 0000 ACIA1_D .EQU $83
0042 0000 ACIA1_C .EQU $82
0043 0000
0044 0000 nmi .EQU 66H
0045 0000
0046 0000 blksiz .equ 4096 ;CP/M allocation size
0047 0000 hstsiz .equ 512 ;host disk sector size
0048 0000 hstspt .equ 32 ;host disk sectors/trk
0049 0000 hstblk .equ hstsiz/128 ;CP/M sects/host buff
0050 0000 cpmspt .equ hstblk * hstspt ;CP/M sectors/track
0051 0000 secmsk .equ hstblk-1 ;sector mask
0052 0000 ;compute sector mask
0053 0000 ;secshf .equ 2 ;log2(hstblk)
0054 0000
0055 0000 wrall .equ 0 ;write to allocated
0056 0000 wrdir .equ 1 ;write to directory
0057 0000 wrual .equ 2 ;write to unallocated
0058 0000
0059 0000 LF .EQU 0AH ;line feed
0060 0000 FF .EQU 0CH ;form feed
0061 0000 CR .EQU 0DH ;carriage RETurn
0062 0000
0063 0000 ;================================================================================================
0064 0000
0065 E600 .ORG bios ; BIOS origin.
0066 E600
0067 E600 ;================================================================================================
0068 E600 ; BIOS jump table.
0069 E600 ;================================================================================================
0070 E600 C3 51 E7 JP boot ; 0 Initialize.
0071 E603 C3 B5 E7 wboote: JP wboot ; 1 Warm boot.
0072 E606 C3 1D E8 JP const ; 2 Console status.
0073 E609 C3 58 E8 JP conin ; 3 Console input.
0074 E60C C3 96 E8 JP conout ; 4 Console OUTput.
0075 E60F C3 7E E8 JP list ; 5 List OUTput.
0076 E612 C3 8A E8 JP punch ; 6 punch OUTput.
0077 E615 C3 4C E8 JP reader ; 7 Reader input.
0078 E618 C3 EF E8 JP home ; 8 Home disk.
0079 E61B C3 C7 E8 JP seldsk ; 9 Select disk.
0080 E61E C3 FB E8 JP settrk ; 10 Select track.
0081 E621 C3 00 E9 JP setsec ; 11 Select sector.
0082 E624 C3 05 E9 JP setdma ; 12 Set DMA ADDress.
0083 E627 C3 0D E9 JP read ; 13 Read 128 bytes.
0084 E62A C3 21 E9 JP write ; 14 Write 128 bytes.
0085 E62D C3 C4 E8 JP listst ; 15 List status.
0086 E630 C3 0A E9 JP sectran ; 16 Sector translate.
0087 E633
0088 E633 ;================================================================================================
0089 E633 ; Disk parameter headers for disk 0 to 15
0090 E633 ;================================================================================================
0091 E633 dpbase:
0092 E633 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb0,0000h,alv00
0092 E639 00000DEB33E700008DEB
0093 E643 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv01
0093 E649 00000DEB42E700008EEC
0094 E653 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv02
0094 E659 00000DEB42E700008FED
0095 E663 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv03
0095 E669 00000DEB42E7000090EE
0096 E673 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv04
0096 E679 00000DEB42E7000091EF
0097 E683 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv05
0097 E689 00000DEB42E7000092F0
0098 E693 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv06
0098 E699 00000DEB42E7000093F1
0099 E6A3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv07
0099 E6A9 00000DEB42E7000094F2
0100 E6B3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv08
0100 E6B9 00000DEB42E7000095F3
0101 E6C3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv09
0101 E6C9 00000DEB42E7000096F4
0102 E6D3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv10
0102 E6D9 00000DEB42E7000097F5
0103 E6E3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv11
0103 E6E9 00000DEB42E7000098F6
0104 E6F3 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv12
0104 E6F9 00000DEB42E7000099F7
0105 E703 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv13
0105 E709 00000DEB42E700009AF8
0106 E713 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv14
0106 E719 00000DEB42E700009BF9
0107 E723 000000000000 .DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv15
0107 E729 00000DEB42E700009CFA
0108 E733
0109 E733 ; First drive has a reserved track for CP/M
0110 E733 dpb0:
0111 E733 80 00 .DW 128 ;SPT - sectors per track
0112 E735 05 .DB 5 ;BSH - block shift factor
0113 E736 1F .DB 31 ;BLM - block mask
0114 E737 01 .DB 1 ;EXM - Extent mask
0115 E738 FB 07 .DW 2043 ; (2047-4) DSM - Storage size (blocks - 1)
0116 E73A FF 01 .DW 511 ;DRM - Number of directory entries - 1
0117 E73C F0 .DB 240 ;AL0 - 1 bit set per directory block
0118 E73D 00 .DB 0 ;AL1 - "
0119 E73E 00 00 .DW 0 ;CKS - DIR check vector size (DRM+1)/4 (0=fixed disk)
0120 E740 01 00 .DW 1 ;OFF - Reserved tracks
0121 E742
0122 E742 dpb:
0123 E742 80 00 .DW 128 ;SPT - sectors per track
0124 E744 05 .DB 5 ;BSH - block shift factor
0125 E745 1F .DB 31 ;BLM - block mask
0126 E746 01 .DB 1 ;EXM - Extent mask
0127 E747 FF 07 .DW 2047 ;DSM - Storage size (blocks - 1)
0128 E749 FF 01 .DW 511 ;DRM - Number of directory entries - 1
0129 E74B F0 .DB 240 ;AL0 - 1 bit set per directory block
0130 E74C 00 .DB 0 ;AL1 - "
0131 E74D 00 00 .DW 0 ;CKS - DIR check vector size (DRM+1)/4 (0=fixed disk)
0132 E74F 00 00 .DW 0 ;OFF - Reserved tracks
0133 E751
0134 E751 ;================================================================================================
0135 E751 ; Cold boot
0136 E751 ;================================================================================================
0137 E751
0138 E751 boot:
0139 E751 F3 DI ; Disable interrupts.
0140 E752 31 C1 FB LD SP,biosstack ; Set default stack.
0141 E755
0142 E755 ; Turn off ROM
0143 E755
0144 E755 3E 01 LD A,$01
0145 E757 D3 38 OUT ($38),A
0146 E759
0147 E759 3E 95 LD A,RTS_LOW
0148 E75B D3 80 OUT (ACIA0_C),A ; Initialise ACIA0
0149 E75D D3 82 OUT (ACIA1_C),A ; Initialise ACIA1
0150 E75F
0151 E75F CD F9 EA CALL printInline
0152 E762 0C .DB FF
0153 E763 43502F4D2042 .TEXT "CP/M BIOS 2.0 by G. Searle 2013"
0153 E769 494F5320322E3020627920472E20536561726C652032303133
0154 E782 0D 0A .DB CR,LF
0155 E784 0D 0A .DB CR,LF
0156 E786 43502F4D2032 .TEXT "CP/M 2.2 "
0156 E78C 2E3220
0157 E78F 28 63 29 .TEXT "(c)"
0158 E792 203139373920 .TEXT " 1979 by Digital Research"
0158 E798 6279204469676974616C205265736561726368
0159 E7AB 0D 0A 00 .DB CR,LF,0
0160 E7AE
0161 E7AE ; CALL sdPreamble??
0162 E7AE
0163 E7AE AF XOR a ; Clear I/O & drive bytes.
0164 E7AF 32 04 00 LD (userdrv),A
0165 E7B2 C3 F5 E7 JP gocpm
0166 E7B5
0167 E7B5 ;================================================================================================
0168 E7B5 ; Warm boot
0169 E7B5 ;================================================================================================
0170 E7B5
0171 E7B5 wboot:
0172 E7B5 F3 DI ; Disable interrupts.
0173 E7B6 31 C1 FB LD SP,biosstack ; Set default stack.
0174 E7B9
0175 E7B9 06 0B LD B,11 ; Number of sectors to reload
0176 E7BB
0177 E7BB 3E 00 LD A,0
0178 E7BD 32 C9 FB LD (hstsec),A
0179 E7C0 D3 8C OUT (SD_LBA2),A
0180 E7C2 D3 8B OUT (SD_LBA1),A
0181 E7C4
0182 E7C4 21 00 D0 LD HL,ccp
0183 E7C7
0184 E7C7 wbRdAllSecs:
0185 E7C7
0186 E7C7 DB 89 wBrdWait1: IN A,(SD_STATUS)
0187 E7C9 FE 80 CP 128
0188 E7CB 20 FA JR NZ,wBrdWait1
0189 E7CD
0190 E7CD 3A C9 FB LD A,(hstsec)
0191 E7D0 D3 8A OUT (SD_LBA0),A
0192 E7D2
0193 E7D2 3E 00 LD A,$00 ; 00 = Read block
0194 E7D4 D3 89 OUT (SD_CONTROL),A
0195 E7D6 C5 PUSH BC
0196 E7D7
0197 E7D7 0E 04 LD c,4
0198 E7D9 wBrd4secs:
0199 E7D9 06 80 LD b,128
0200 E7DB wBrdByte:
0201 E7DB
0202 E7DB DB 89 wBrdWait2: IN A,(SD_STATUS)
0203 E7DD FE E0 CP 224 ; Read byte waiting
0204 E7DF 20 FA JR NZ,wBrdWait2
0205 E7E1
0206 E7E1 DB 88 IN A,(SD_DATA)
0207 E7E3
0208 E7E3 77 LD (HL),A
0209 E7E4 23 INC HL
0210 E7E5 05 dec b
0211 E7E6 20 F3 JR NZ, wBrdByte
0212 E7E8
0213 E7E8 0D dec c
0214 E7E9 20 EE JR NZ,wBrd4secs
0215 E7EB
0216 E7EB 3A C9 FB LD A,(hstsec)
0217 E7EE 3C INC A
0218 E7EF 32 C9 FB LD (hstsec),A
0219 E7F2
0220 E7F2 C1 POP BC
0221 E7F3
0222 E7F3 10 D2 DJNZ wbRdAllSecs
0223 E7F5 ;================================================================================================
0224 E7F5 ; Common code for cold and warm boot
0225 E7F5 ;================================================================================================
0226 E7F5
0227 E7F5 gocpm:
0228 E7F5 AF xor a ;0 to accumulator
0229 E7F6 32 CB FB ld (hstact),a ;host buffer inactive
0230 E7F9 32 CD FB ld (unacnt),a ;clear unalloc count
0231 E7FC
0232 E7FC 21 80 00 LD HL,tpabuf ; Address of BIOS DMA buffer.
0233 E7FF 22 D6 FB LD (dmaAddr),HL
0234 E802 3E C3 LD A,0C3h ; Opcode for 'JP'.
0235 E804 32 00 00 LD (00h),A ; Load at start of RAM.
0236 E807 21 03 E6 LD HL,wboote ; Address of jump for a warm boot.
0237 E80A 22 01 00 LD (01h),HL
0238 E80D 32 05 00 LD (05h),A ; Opcode for 'JP'.
0239 E810 21 06 D8 LD HL,bdos ; Address of jump for the BDOS.
0240 E813 22 06 00 LD (06h),HL
0241 E816 3A 04 00 LD A,(userdrv) ; Save new drive number (0).
0242 E819 4F LD c,A ; Pass drive number in C.
0243 E81A
0244 E81A C3 00 D0 JP ccp ; Start CP/M by jumping to the CCP.
0245 E81D
0246 E81D ;================================================================================================
0247 E81D ; Console I/O routines
0248 E81D ;================================================================================================
0249 E81D
0250 E81D
0251 E81D ;------------------------------------------------------------------------------------------------
0252 E81D const:
0253 E81D 3A 03 00 LD A,(iobyte)
0254 E820 E6 0B AND 00001011b ; Mask off console and high bit of reader
0255 E822 FE 0A CP 00001010b ; redirected to reader on UR1/2 (Serial A)
0256 E824 28 0A JR Z,constA
0257 E826 FE 02 CP 00000010b ; redirected to reader on TTY/RDR (Serial B)
0258 E828 28 14 JR Z,constB
0259 E82A
0260 E82A E6 03 AND $03 ; remove the reader from the mask - only console bits then remain
0261 E82C FE 01 CP $01
0262 E82E 20 0E JR NZ,constB
0263 E830 constA:
0264 E830 DB 80 IN A,(ACIA0_C) ; Status byte
0265 E832 E6 01 AND $01
0266 E834 FE 00 CP $0 ; Z flag set if no char
0267 E836 28 03 JR Z, dataAEmpty
0268 E838 3E FF LD A,0FFH
0269 E83A C9 RET
0270 E83B dataAEmpty:
0271 E83B 3E 00 LD A,0
0272 E83D C9 RET
0273 E83E
0274 E83E
0275 E83E constB:
0276 E83E DB 82 IN A,(ACIA1_C) ; Status byte
0277 E840 E6 01 AND $01
0278 E842 FE 00 CP $0 ; Z flag set if no char
0279 E844 28 03 JR Z, dataBEmpty
0280 E846 3E FF LD A,0FFH
0281 E848 C9 RET
0282 E849 dataBEmpty:
0283 E849 3E 00 LD A,0
0284 E84B C9 RET
0285 E84C
0286 E84C ;------------------------------------------------------------------------------------------------
0287 E84C reader:
0288 E84C F5 PUSH AF
0289 E84D 3A 03 00 reader2: LD A,(iobyte)
0290 E850 E6 08 AND $08
0291 E852 FE 08 CP $08
0292 E854 20 1C JR NZ,coninB
0293 E856 18 0E JR coninA
0294 E858 ;------------------------------------------------------------------------------------------------
0295 E858 conin:
0296 E858 F5 PUSH AF
0297 E859 3A 03 00 LD A,(iobyte)
0298 E85C E6 03 AND $03
0299 E85E FE 02 CP $02
0300 E860 28 EB JR Z,reader2 ; "BAT:" redirect
0301 E862 FE 01 CP $01
0302 E864 20 0C JR NZ,coninB
0303 E866
0304 E866
0305 E866 coninA:
0306 E866 F1 POP AF
0307 E867 waitForCharA:
0308 E867 DB 80 IN A,(ACIA0_C) ; Status byte
0309 E869 E6 01 AND $01
0310 E86B FE 00 CP $0 ; Z flag set if no char
0311 E86D 28 F8 JR Z, waitForCharA
0312 E86F DB 81 IN A,(ACIA0_D)
0313 E871
0314 E871 C9 RET ; Char ready in A
0315 E872
0316 E872
0317 E872 coninB:
0318 E872 F1 POP AF
0319 E873 waitForCharB:
0320 E873 DB 82 IN A,(ACIA1_C) ; Status byte
0321 E875 E6 01 AND $01
0322 E877 FE 00 CP $0 ; Z flag set if no char
0323 E879 28 F8 JR Z, waitForCharB
0324 E87B DB 83 IN A,(ACIA1_D)
0325 E87D
0326 E87D C9 RET ; Char ready in A
0327 E87E
0328 E87E ;------------------------------------------------------------------------------------------------
0329 E87E F5 list: PUSH AF ; Store character
0330 E87F 3A 03 00 list2: LD A,(iobyte)
0331 E882 E6 C0 AND $C0
0332 E884 FE 40 CP $40
0333 E886 20 26 JR NZ,conoutB1
0334 E888 18 1A JR conoutA1
0335 E88A
0336 E88A ;------------------------------------------------------------------------------------------------
0337 E88A F5 punch: PUSH AF ; Store character
0338 E88B 3A 03 00 LD A,(iobyte)
0339 E88E E6 20 AND $20
0340 E890 FE 20 CP $20
0341 E892 20 1A JR NZ,conoutB1
0342 E894 18 0E JR conoutA1
0343 E896
0344 E896 ;------------------------------------------------------------------------------------------------
0345 E896 F5 conout: PUSH AF
0346 E897 3A 03 00 LD A,(iobyte)
0347 E89A E6 03 AND $03
0348 E89C FE 02 CP $02
0349 E89E 28 DF JR Z,list2 ; "BAT:" redirect
0350 E8A0 FE 01 CP $01
0351 E8A2 20 0A JR NZ,conoutB1
0352 E8A4
0353 E8A4 CD B8 E8 conoutA1: CALL CKACIA0 ; See if ACIA channel A is finished transmitting
0354 E8A7 28 FB JR Z,conoutA1 ; Loop until ACIA flag signals ready
0355 E8A9 79 LD A,C
0356 E8AA D3 81 OUT (ACIA0_D),A ; OUTput the character
0357 E8AC F1 POP AF
0358 E8AD C9 RET
0359 E8AE
0360 E8AE CD BE E8 conoutB1: CALL CKACIA1 ; See if ACIA channel B is finished transmitting
0361 E8B1 28 FB JR Z,conoutB1 ; Loop until ACIA flag signals ready
0362 E8B3 79 LD A,C
0363 E8B4 D3 83 OUT (ACIA1_D),A ; OUTput the character
0364 E8B6 F1 POP AF
0365 E8B7 C9 RET
0366 E8B8
0367 E8B8 ;------------------------------------------------------------------------------------------------
0368 E8B8 CKACIA0
0369 E8B8 DB 80 IN A,(ACIA0_C) ; Status byte D1=TX Buff Empty, D0=RX char ready
0370 E8BA 0F RRCA ; Rotates RX status into Carry Flag,
0371 E8BB CB 47 BIT 0,A ; Set Zero flag if still transmitting character
0372 E8BD C9 RET
0373 E8BE
0374 E8BE CKACIA1
0375 E8BE DB 82 IN A,(ACIA1_C) ; Status byte D1=TX Buff Empty, D0=RX char ready
0376 E8C0 0F RRCA ; Rotates RX status into Carry Flag,
0377 E8C1 CB 47 BIT 0,A ; Set Zero flag if still transmitting character
0378 E8C3 C9 RET
0379 E8C4
0380 E8C4 ;------------------------------------------------------------------------------------------------
0381 E8C4 3E FF listst: LD A,$FF ; Return list status of 0xFF (ready).
0382 E8C6 C9 RET
0383 E8C7
0384 E8C7 ;================================================================================================
0385 E8C7 ; Disk processing entry points
0386 E8C7 ;================================================================================================
0387 E8C7
0388 E8C7 seldsk:
0389 E8C7 21 00 00 LD HL,$0000
0390 E8CA 79 LD A,C
0391 E8CB FE 10 CP 16 ; 16 for 128MB disk, 8 for 64MB disk
0392 E8CD 38 0D jr C,chgdsk ; if invalid drive will give BDOS error
0393 E8CF 3A 04 00 LD A,(userdrv) ; so set the drive back to a:
0394 E8D2 B9 CP C ; If the default disk is not the same as the
0395 E8D3 C0 RET NZ ; selected drive then return,
0396 E8D4 AF XOR A ; else reset default back to a:
0397 E8D5 32 04 00 LD (userdrv),A ; otherwise will be stuck in a loop
0398 E8D8 32 C1 FB LD (sekdsk),A
0399 E8DB C9 ret
0400 E8DC
0401 E8DC 32 C1 FB chgdsk: LD (sekdsk),A
0402 E8DF CB 07 RLC a ;*2
0403 E8E1 CB 07 RLC a ;*4
0404 E8E3 CB 07 RLC a ;*8
0405 E8E5 CB 07 RLC a ;*16
0406 E8E7 21 33 E6 LD HL,dpbase
0407 E8EA 06 00 LD b,0
0408 E8EC 4F LD c,A
0409 E8ED 09 ADD HL,BC
0410 E8EE
0411 E8EE C9 RET
0412 E8EF
0413 E8EF ;------------------------------------------------------------------------------------------------
0414 E8EF home:
0415 E8EF 3A CC FB ld a,(hstwrt) ;check for pending write
0416 E8F2 B7 or a
0417 E8F3 20 03 jr nz,homed
0418 E8F5 32 CB FB ld (hstact),a ;clear host active flag
0419 E8F8 homed:
0420 E8F8 01 00 00 LD BC,0000h
0421 E8FB
0422 E8FB ;------------------------------------------------------------------------------------------------
0423 E8FB ED 43 C2 FB settrk: LD (sektrk),BC ; Set track passed from BDOS in register BC.
0424 E8FF C9 RET
0425 E900
0426 E900 ;------------------------------------------------------------------------------------------------
0427 E900 ED 43 C4 FB setsec: LD (seksec),BC ; Set sector passed from BDOS in register BC.
0428 E904 C9 RET
0429 E905
0430 E905 ;------------------------------------------------------------------------------------------------
0431 E905 ED 43 D6 FB setdma: LD (dmaAddr),BC ; Set DMA ADDress given by registers BC.
0432 E909 C9 RET
0433 E90A
0434 E90A ;------------------------------------------------------------------------------------------------
0435 E90A C5 sectran: PUSH BC
0436 E90B E1 POP HL
0437 E90C C9 RET
0438 E90D
0439 E90D ;------------------------------------------------------------------------------------------------
0440 E90D read:
0441 E90D ;read the selected CP/M sector
0442 E90D AF xor a
0443 E90E 32 CD FB ld (unacnt),a
0444 E911 3E 01 ld a,1
0445 E913 32 D4 FB ld (readop),a ;read operation
0446 E916 32 D3 FB ld (rsflag),a ;must read data
0447 E919 3E 02 ld a,wrual
0448 E91B 32 D5 FB ld (wrtype),a ;treat as unalloc
0449 E91E C3 88 E9 jp rwoper ;to perform the read
0450 E921
0451 E921
0452 E921 ;------------------------------------------------------------------------------------------------
0453 E921 write:
0454 E921 ;write the selected CP/M sector
0455 E921 AF xor a ;0 to accumulator
0456 E922 32 D4 FB ld (readop),a ;not a read operation
0457 E925 79 ld a,c ;write type in c
0458 E926 32 D5 FB ld (wrtype),a
0459 E929 FE 02 cp wrual ;write unallocated?
0460 E92B 20 17 jr nz,chkuna ;check for unalloc
0461 E92D ;
0462 E92D ; write to unallocated, set parameters
0463 E92D 3E 20 ld a,blksiz/128 ;next unalloc recs
0464 E92F 32 CD FB ld (unacnt),a
0465 E932 3A C1 FB ld a,(sekdsk) ;disk to seek
0466 E935 32 CE FB ld (unadsk),a ;unadsk = sekdsk
0467 E938 2A C2 FB ld hl,(sektrk)
0468 E93B 22 CF FB ld (unatrk),hl ;unatrk = sectrk
0469 E93E 3A C4 FB ld a,(seksec)
0470 E941 32 D1 FB ld (unasec),a ;unasec = seksec
0471 E944 ;
0472 E944 chkuna:
0473 E944 ; check for write to unallocated sector
0474 E944 3A CD FB ld a,(unacnt) ;any unalloc remain?
0475 E947 B7 or a
0476 E948 28 36 jr z,alloc ;skip if not
0477 E94A ;
0478 E94A ; more unallocated records remain
0479 E94A 3D dec a ;unacnt = unacnt-1
0480 E94B 32 CD FB ld (unacnt),a
0481 E94E 3A C1 FB ld a,(sekdsk) ;same disk?
0482 E951 21 CE FB ld hl,unadsk
0483 E954 BE cp (hl) ;sekdsk = unadsk?
0484 E955 C2 80 E9 jp nz,alloc ;skip if not
0485 E958 ;
0486 E958 ; disks are the same
0487 E958 21 CF FB ld hl,unatrk
0488 E95B CD 1F EA call sektrkcmp ;sektrk = unatrk?
0489 E95E C2 80 E9 jp nz,alloc ;skip if not
0490 E961 ;
0491 E961 ; tracks are the same
0492 E961 3A C4 FB ld a,(seksec) ;same sector?
0493 E964 21 D1 FB ld hl,unasec
0494 E967 BE cp (hl) ;seksec = unasec?
0495 E968 C2 80 E9 jp nz,alloc ;skip if not
0496 E96B ;
0497 E96B ; match, move to next sector for future ref
0498 E96B 34 inc (hl) ;unasec = unasec+1
0499 E96C 7E ld a,(hl) ;end of track?
0500 E96D FE 80 cp cpmspt ;count CP/M sectors
0501 E96F 38 09 jr c,noovf ;skip if no overflow
0502 E971 ;
0503 E971 ; overflow to next track
0504 E971 36 00 ld (hl),0 ;unasec = 0
0505 E973 2A CF FB ld hl,(unatrk)
0506 E976 23 inc hl
0507 E977 22 CF FB ld (unatrk),hl ;unatrk = unatrk+1
0508 E97A ;
0509 E97A noovf:
0510 E97A ;match found, mark as unnecessary read
0511 E97A AF xor a ;0 to accumulator
0512 E97B 32 D3 FB ld (rsflag),a ;rsflag = 0
0513 E97E 18 08 jr rwoper ;to perform the write
0514 E980 ;
0515 E980 alloc:
0516 E980 ;not an unallocated record, requires pre-read
0517 E980 AF xor a ;0 to accum
0518 E981 32 CD FB ld (unacnt),a ;unacnt = 0
0519 E984 3C inc a ;1 to accum
0520 E985 32 D3 FB ld (rsflag),a ;rsflag = 1
0521 E988
0522 E988 ;------------------------------------------------------------------------------------------------
0523 E988 rwoper:
0524 E988 ;enter here to perform the read/write
0525 E988 AF xor a ;zero to accum
0526 E989 32 D2 FB ld (erflag),a ;no errors (yet)
0527 E98C 3A C4 FB ld a,(seksec) ;compute host sector
0528 E98F B7 or a ;carry = 0
0529 E990 1F rra ;shift right
0530 E991 B7 or a ;carry = 0
0531 E992 1F rra ;shift right
0532 E993 32 CA FB ld (sekhst),a ;host sector to seek
0533 E996 ;
0534 E996 ; active host sector?
0535 E996 21 CB FB ld hl,hstact ;host active flag
0536 E999 7E ld a,(hl)
0537 E99A 36 01 ld (hl),1 ;always becomes 1
0538 E99C B7 or a ;was it already?
0539 E99D 28 21 jr z,filhst ;fill host if not
0540 E99F ;
0541 E99F ; host buffer active, same as seek buffer?
0542 E99F 3A C1 FB ld a,(sekdsk)
0543 E9A2 21 C6 FB ld hl,hstdsk ;same disk?
0544 E9A5 BE cp (hl) ;sekdsk = hstdsk?
0545 E9A6 20 11 jr nz,nomatch
0546 E9A8 ;
0547 E9A8 ; same disk, same track?
0548 E9A8 21 C7 FB ld hl,hsttrk
0549 E9AB CD 1F EA call sektrkcmp ;sektrk = hsttrk?
0550 E9AE 20 09 jr nz,nomatch
0551 E9B0 ;
0552 E9B0 ; same disk, same track, same buffer?
0553 E9B0 3A CA FB ld a,(sekhst)
0554 E9B3 21 C9 FB ld hl,hstsec ;sekhst = hstsec?
0555 E9B6 BE cp (hl)
0556 E9B7 28 24 jr z,match ;skip if match
0557 E9B9 ;
0558 E9B9 nomatch:
0559 E9B9 ;proper disk, but not correct sector
0560 E9B9 3A CC FB ld a,(hstwrt) ;host written?
0561 E9BC B7 or a
0562 E9BD C4 C4 EA call nz,writehst ;clear host buff
0563 E9C0 ;
0564 E9C0 filhst:
0565 E9C0 ;may have to fill the host buffer
0566 E9C0 3A C1 FB ld a,(sekdsk)
0567 E9C3 32 C6 FB ld (hstdsk),a
0568 E9C6 2A C2 FB ld hl,(sektrk)
0569 E9C9 22 C7 FB ld (hsttrk),hl
0570 E9CC 3A CA FB ld a,(sekhst)
0571 E9CF 32 C9 FB ld (hstsec),a
0572 E9D2 3A D3 FB ld a,(rsflag) ;need to read?
0573 E9D5 B7 or a
0574 E9D6 C4 95 EA call nz,readhst ;yes, if 1
0575 E9D9 AF xor a ;0 to accum
0576 E9DA 32 CC FB ld (hstwrt),a ;no pending write
0577 E9DD ;
0578 E9DD match:
0579 E9DD ;copy data to or from buffer
0580 E9DD 3A C4 FB ld a,(seksec) ;mask buffer number
0581 E9E0 E6 03 and secmsk ;least signif bits
0582 E9E2 6F ld l,a ;ready to shift
0583 E9E3 26 00 ld h,0 ;double count
0584 E9E5 29 add hl,hl
0585 E9E6 29 add hl,hl
0586 E9E7 29 add hl,hl
0587 E9E8 29 add hl,hl
0588 E9E9 29 add hl,hl
0589 E9EA 29 add hl,hl
0590 E9EB 29 add hl,hl
0591 E9EC ; hl has relative host buffer address
0592 E9EC 11 D8 FB ld de,hstbuf
0593 E9EF 19 add hl,de ;hl = host address
0594 E9F0 EB ex de,hl ;now in DE
0595 E9F1 2A D6 FB ld hl,(dmaAddr) ;get/put CP/M data
0596 E9F4 0E 80 ld c,128 ;length of move
0597 E9F6 3A D4 FB ld a,(readop) ;which way?
0598 E9F9 B7 or a
0599 E9FA 20 06 jr nz,rwmove ;skip if read
0600 E9FC ;
0601 E9FC ; write operation, mark and switch direction
0602 E9FC 3E 01 ld a,1
0603 E9FE 32 CC FB ld (hstwrt),a ;hstwrt = 1
0604 EA01 EB ex de,hl ;source/dest swap
0605 EA02 ;
0606 EA02 rwmove:
0607 EA02 ;C initially 128, DE is source, HL is dest
0608 EA02 1A ld a,(de) ;source character
0609 EA03 13 inc de
0610 EA04 77 ld (hl),a ;to dest
0611 EA05 23 inc hl
0612 EA06 0D dec c ;loop 128 times
0613 EA07 20 F9 jr nz,rwmove
0614 EA09 ;
0615 EA09 ; data has been moved to/from host buffer
0616 EA09 3A D5 FB ld a,(wrtype) ;write type
0617 EA0C FE 01 cp wrdir ;to directory?
0618 EA0E 3A D2 FB ld a,(erflag) ;in case of errors
0619 EA11 C0 ret nz ;no further processing
0620 EA12 ;
0621 EA12 ; clear host buffer for directory write
0622 EA12 B7 or a ;errors?
0623 EA13 C0 ret nz ;skip if so
0624 EA14 AF xor a ;0 to accum
0625 EA15 32 CC FB ld (hstwrt),a ;buffer written
0626 EA18 CD C4 EA call writehst
0627 EA1B 3A D2 FB ld a,(erflag)
0628 EA1E C9 ret
0629 EA1F
0630 EA1F ;------------------------------------------------------------------------------------------------
0631 EA1F ;Utility subroutine for 16-bit compare
0632 EA1F sektrkcmp:
0633 EA1F ;HL = .unatrk or .hsttrk, compare with sektrk
0634 EA1F EB ex de,hl
0635 EA20 21 C2 FB ld hl,sektrk
0636 EA23 1A ld a,(de) ;low byte compare
0637 EA24 BE cp (HL) ;same?
0638 EA25 C0 ret nz ;return if not
0639 EA26 ; low bytes equal, test high 1s
0640 EA26 13 inc de
0641 EA27 23 inc hl
0642 EA28 1A ld a,(de)
0643 EA29 BE cp (hl) ;sets flags
0644 EA2A C9 ret
0645 EA2B
0646 EA2B ;================================================================================================
0647 EA2B ; Convert track/head/sector into LBA for physical access to the disk
0648 EA2B ;================================================================================================
0649 EA2B setLBAaddr:
0650 EA2B 2A C7 FB LD HL,(hsttrk)
0651 EA2E CB 05 RLC L
0652 EA30 CB 05 RLC L
0653 EA32 CB 05 RLC L
0654 EA34 CB 05 RLC L
0655 EA36 CB 05 RLC L
0656 EA38 7D LD A,L
0657 EA39 E6 E0 AND 0E0H
0658 EA3B 6F LD L,A
0659 EA3C 3A C9 FB LD A,(hstsec)
0660 EA3F 85 ADD A,L
0661 EA40 32 9D FB LD (lba0),A
0662 EA43
0663 EA43 2A C7 FB LD HL,(hsttrk)
0664 EA46 CB 0D RRC L
0665 EA48 CB 0D RRC L
0666 EA4A CB 0D RRC L
0667 EA4C 7D LD A,L
0668 EA4D E6 1F AND 01FH
0669 EA4F 6F LD L,A
0670 EA50 CB 04 RLC H
0671 EA52 CB 04 RLC H
0672 EA54 CB 04 RLC H
0673 EA56 CB 04 RLC H
0674 EA58 CB 04 RLC H
0675 EA5A 7C LD A,H
0676 EA5B E6 20 AND 020H
0677 EA5D 67 LD H,A
0678 EA5E 3A C6 FB LD A,(hstdsk)
0679 EA61 CB 07 RLC a
0680 EA63 CB 07 RLC a
0681 EA65 CB 07 RLC a
0682 EA67 CB 07 RLC a
0683 EA69 CB 07 RLC a
0684 EA6B CB 07 RLC a
0685 EA6D E6 C0 AND 0C0H
0686 EA6F 84 ADD A,H
0687 EA70 85 ADD A,L
0688 EA71 32 9E FB LD (lba1),A
0689 EA74
0690 EA74 3A C6 FB LD A,(hstdsk)
0691 EA77 CB 0F RRC A
0692 EA79 CB 0F RRC A
0693 EA7B E6 03 AND 03H
0694 EA7D 32 9F FB LD (lba2),A
0695 EA80
0696 EA80 3E 00 LD a,00H
0697 EA82 32 A0 FB LD (lba3),A
0698 EA85
0699 EA85 ; Transfer LBA to disk (LBA3 not used on SD card)
0700 EA85 3A 9F FB LD A,(lba2)
0701 EA88 D3 8C OUT (SD_LBA2),A
0702 EA8A 3A 9E FB LD A,(lba1)
0703 EA8D D3 8B OUT (SD_LBA1),A
0704 EA8F 3A 9D FB LD A,(lba0)
0705 EA92 D3 8A OUT (SD_LBA0),A
0706 EA94 C9 RET
0707 EA95
0708 EA95 ;================================================================================================
0709 EA95 ; Read physical sector from host
0710 EA95 ;================================================================================================
0711 EA95
0712 EA95 readhst:
0713 EA95 F5 PUSH AF
0714 EA96 C5 PUSH BC
0715 EA97 E5 PUSH HL
0716 EA98
0717 EA98 DB 89 rdWait1: IN A,(SD_STATUS)
0718 EA9A FE 80 CP 128
0719 EA9C 20 FA JR NZ,rdWait1
0720 EA9E
0721 EA9E CD 2B EA CALL setLBAaddr
0722 EAA1
0723 EAA1 3E 00 LD A,$00 ; 00 = Read block
0724 EAA3 D3 89 OUT (SD_CONTROL),A
0725 EAA5
0726 EAA5 0E 04 LD c,4
0727 EAA7 21 D8 FB LD HL,hstbuf
0728 EAAA rd4secs:
0729 EAAA 06 80 LD b,128
0730 EAAC rdByte:
0731 EAAC
0732 EAAC DB 89 rdWait2: IN A,(SD_STATUS)
0733 EAAE FE E0 CP 224 ; Read byte waiting
0734 EAB0 20 FA JR NZ,rdWait2
0735 EAB2
0736 EAB2 DB 88 IN A,(SD_DATA)
0737 EAB4
0738 EAB4 77 LD (HL),A
0739 EAB5 23 INC HL
0740 EAB6 05 dec b
0741 EAB7 20 F3 JR NZ, rdByte
0742 EAB9 0D dec c
0743 EABA 20 EE JR NZ,rd4secs
0744 EABC
0745 EABC E1 POP HL
0746 EABD C1 POP BC
0747 EABE F1 POP AF
0748 EABF
0749 EABF AF XOR a
0750 EAC0 32 D2 FB ld (erflag),a
0751 EAC3 C9 RET
0752 EAC4
0753 EAC4
0754 EAC4 ;================================================================================================
0755 EAC4 ; Write physical sector to host
0756 EAC4 ;================================================================================================
0757 EAC4
0758 EAC4 writehst:
0759 EAC4 F5 PUSH AF
0760 EAC5 C5 PUSH BC
0761 EAC6 E5 PUSH HL
0762 EAC7
0763 EAC7 DB 89 wrWait1: IN A,(SD_STATUS)
0764 EAC9 FE 80 CP 128
0765 EACB 20 FA JR NZ,wrWait1
0766 EACD
0767 EACD CD 2B EA CALL setLBAaddr
0768 EAD0
0769 EAD0 3E 01 LD A,$01 ; 01 = Write block
0770 EAD2 D3 89 OUT (SD_CONTROL),A
0771 EAD4
0772 EAD4 0E 04 LD c,4
0773 EAD6 21 D8 FB LD HL,hstbuf
0774 EAD9 wr4secs:
0775 EAD9 06 80 LD b,128
0776 EADB wrByte:
0777 EADB
0778 EADB DB 89 wrWait2: IN A,(SD_STATUS)
0779 EADD FE A0 CP 160 ; Write buffer empty
0780 EADF 20 FA JR NZ,wrWait2
0781 EAE1
0782 EAE1 ; UPDATE S0urceror, inserted wait cycle between IN and OUT
0783 EAE1 ; to resolve unknown write issue in sd_controller.vhd in combination
0784 EAE1 ; with MISTer virtual SD interface sys/sd_card.sv
0785 EAE1 ; which results in hangs or write errors.
0786 EAE1 C5 push bc
0787 EAE2 06 32 ld b,50
0788 EAE4 _again:
0789 EAE4 10 FE djnz _again
0790 EAE6 C1 pop bc
0791 EAE7 ; END UPDATE
0792 EAE7
0793 EAE7 7E LD A,(HL)
0794 EAE8 D3 88 OUT (SD_DATA),A
0795 EAEA 23 INC HL
0796 EAEB 05 dec b
0797 EAEC 20 ED JR NZ, wrByte
0798 EAEE
0799 EAEE 0D dec c
0800 EAEF 20 E8 JR NZ,wr4secs
0801 EAF1
0802 EAF1 E1 POP HL
0803 EAF2 C1 POP BC
0804 EAF3 F1 POP AF
0805 EAF4
0806 EAF4 AF XOR a
0807 EAF5 32 D2 FB ld (erflag),a
0808 EAF8 C9 RET
0809 EAF9
0810 EAF9 ;================================================================================================
0811 EAF9 ; Utilities
0812 EAF9 ;================================================================================================
0813 EAF9
0814 EAF9 printInline:
0815 EAF9 E3 EX (SP),HL ; PUSH HL and put RET ADDress into HL
0816 EAFA F5 PUSH AF
0817 EAFB C5 PUSH BC
0818 EAFC 7E nextILChar: LD A,(HL)
0819 EAFD FE 00 CP 0
0820 EAFF 28 07 JR Z,endOfPrint
0821 EB01 4F LD C,A
0822 EB02 CD 96 E8 CALL conout ; Print to TTY
0823 EB05 23 iNC HL
0824 EB06 18 F4 JR nextILChar
0825 EB08 23 endOfPrint: INC HL ; Get past "null" terminator
0826 EB09 C1 POP BC
0827 EB0A F1 POP AF
0828 EB0B E3 EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
0829 EB0C C9 RET
0830 EB0D
0831 EB0D ;================================================================================================
0832 EB0D ; Data storage
0833 EB0D ;================================================================================================
0834 EB0D
0835 EB0D dirbuf: .ds 128 ;scratch directory area
0836 EB8D alv00: .ds 257 ;allocation vector 0
0837 EC8E alv01: .ds 257 ;allocation vector 1
0838 ED8F alv02: .ds 257 ;allocation vector 2
0839 EE90 alv03: .ds 257 ;allocation vector 3
0840 EF91 alv04: .ds 257 ;allocation vector 4
0841 F092 alv05: .ds 257 ;allocation vector 5
0842 F193 alv06: .ds 257 ;allocation vector 6
0843 F294 alv07: .ds 257 ;allocation vector 7
0844 F395 alv08: .ds 257 ;allocation vector 8
0845 F496 alv09: .ds 257 ;allocation vector 9
0846 F597 alv10: .ds 257 ;allocation vector 10
0847 F698 alv11: .ds 257 ;allocation vector 11
0848 F799 alv12: .ds 257 ;allocation vector 12
0849 F89A alv13: .ds 257 ;allocation vector 13
0850 F99B alv14: .ds 257 ;allocation vector 14
0851 FA9C alv15: .ds 257 ;allocation vector 15
0852 FB9D
0853 FB9D 00 lba0 .DB 00h
0854 FB9E 00 lba1 .DB 00h
0855 FB9F 00 lba2 .DB 00h
0856 FBA0 00 lba3 .DB 00h
0857 FBA1
0858 FBA1 .DS 020h ; Start of BIOS stack area.
0859 FBC1 biosstack: .EQU $
0860 FBC1
0861 FBC1 sekdsk: .ds 1 ;seek disk number
0862 FBC2 sektrk: .ds 2 ;seek track number
0863 FBC4 seksec: .ds 2 ;seek sector number
0864 FBC6 ;
0865 FBC6 hstdsk: .ds 1 ;host disk number
0866 FBC7 hsttrk: .ds 2 ;host track number
0867 FBC9 hstsec: .ds 1 ;host sector number
0868 FBCA ;
0869 FBCA sekhst: .ds 1 ;seek shr secshf
0870 FBCB hstact: .ds 1 ;host active flag
0871 FBCC hstwrt: .ds 1 ;host written flag
0872 FBCD ;
0873 FBCD unacnt: .ds 1 ;unalloc rec cnt
0874 FBCE unadsk: .ds 1 ;last unalloc disk
0875 FBCF unatrk: .ds 2 ;last unalloc track
0876 FBD1 unasec: .ds 1 ;last unalloc sector
0877 FBD2 ;
0878 FBD2 erflag: .ds 1 ;error reporting
0879 FBD3 rsflag: .ds 1 ;read sector flag
0880 FBD4 readop: .ds 1 ;1 if read operation
0881 FBD5 wrtype: .ds 1 ;write operation type
0882 FBD6 dmaAddr: .ds 2 ;last dma address
0883 FBD8 hstbuf: .ds 512 ;host buffer
0884 FDD8
0885 FDD8 hstBufEnd: .EQU $
0886 FDD8
0887 FDD8 biosEnd: .EQU $
0888 FDD8
0889 FDD8 ; Disable the ROM, pop the active IO port from the stack (supplied by monitor),
0890 FDD8 ; then start CP/M
0891 FDD8 popAndRun:
0892 FDD8 3E 01 LD A,$01
0893 FDDA D3 38 OUT ($38),A
0894 FDDC
0895 FDDC F1 POP AF
0896 FDDD FE 01 CP $01
0897 FDDF 28 04 JR Z,consoleAtB
0898 FDE1 3E 01 LD A,$01 ;(List is TTY:, Punch is TTY:, Reader is TTY:, Console is CRT:)
0899 FDE3 18 02 JR setIOByte
0900 FDE5 3E 00 consoleAtB: LD A,$00 ;(List is TTY:, Punch is TTY:, Reader is TTY:, Console is TTY:)
0901 FDE7 32 03 00 setIOByte: LD (iobyte),A
0902 FDEA C3 00 E6 JP bios
0903 FDED
0904 FDED
0905 FDED ;=================================================================================
0906 FDED ; Relocate TPA area from 4100 to 0100 then start CP/M
0907 FDED ; Used to manually transfer a loaded program after CP/M was previously loaded
0908 FDED ;=================================================================================
0909 FDED
0910 FFE8 .org 0FFE8H
0911 FFE8 3E 01 LD A,$01
0912 FFEA D3 38 OUT ($38),A
0913 FFEC
0914 FFEC 21 00 41 LD HL,04100H
0915 FFEF 11 00 01 LD DE,00100H
0916 FFF2 01 00 8F LD BC,08F00H
0917 FFF5 ED B0 LDIR
0918 FFF7 C3 00 E6 JP bios
0919 FFFA
0920 FFFA ;=================================================================================
0921 FFFA ; Normal start CP/M vector
0922 FFFA ;=================================================================================
0923 FFFA
0924 FFFE .ORG 0FFFEH
0925 FFFE D8 FD .dw popAndRun
0926 0000
0927 0000 .END
tasm: Number of errors = 0

96
Z80 CPM and bootloader (basmon)/source/CH376S.LST Normal file
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0001 0000 LF .EQU 0AH ;line feed
0002 0000 FF .EQU 0CH ;form feed
0003 0000 CR .EQU 0DH ;carriage RETurn
0004 0000 DOT .EQU '.'
0005 0000 CH375_CMD_CHECK_EXIST .EQU 06H
0006 0000 CH375_CMD_RESET_ALL .EQU 05H
0007 0000
0008 4000 .ORG 4000H
0009 4000
0010 4000 CD 5F 40 CALL printInline
0011 4003 436865636B20 .TEXT "Check CH376s communication"
0011 4009 43483337367320636F6D6D756E69636174696F6E
0012 401D 0D 0A 00 .DB CR,LF,0
0013 4020
0014 4020 CD 5F 40 CALL printInline
0015 4023 53656E642041 .TEXT "Send A"
0016 4029 0D 0A 00 .DB CR,LF,0
0017 402C
0018 402C ;ld a, CH375_CMD_RESET_ALL
0019 402C ;out (20h),a
0020 402C
0021 402C ;ld a, CH375_CMD_CHECK_EXIST
0022 402C ;out (20h),a
0023 402C 06 0A ld b, 10
0024 402E 3E AA ld a, 0AAH
0025 4030 _again:
0026 4030 D3 20 out (20h),a
0027 4032 C5 push bc
0028 4033 06 32 ld b, 50
0029 4035 _again2:
0030 4035 10 FE djnz _again2
0031 4037 C1 pop bc
0032 4038 10 F6 djnz _again
0033 403A ; receive result
0034 403A ;xor a
0035 403A ;out (20h),a
0036 403A ;in a, (20h)
0037 403A ;xor 255
0038 403A
0039 403A CD 5F 40 CALL printInline
0040 403D 526563656976 .TEXT "Received "
0040 4043 656420
0041 4046 00 .DB 0
0042 4047
0043 4047 CF RST 08H ; print contents of A
0044 4048
0045 4048 CD 5F 40 CALL printInline
0046 404B 0D 0A 00 .DB CR,LF,0
0047 404E
0048 404E C9 ret
0049 404F
0050 404F ; LOOPBACK TEST
0051 404F
0052 404F 06 39 ld b, 39h
0053 4051 outer:
0054 4051 78 ld a, b
0055 4052 FE 2F cp 2fh
0056 4054 C8 ret z
0057 4055 ; send out
0058 4055 D3 20 out (20h),a
0059 4057 ;inner:
0060 4057 ; ld a, DOT
0061 4057 ; rst 08h
0062 4057 ; in a, (21h)
0063 4057 ; bit 0,a
0064 4057 ; jr z, inner
0065 4057 AF xor a
0066 4058
0067 4058 ; read back
0068 4058 DB 20 in a, (20h)
0069 405A CF rst 08h ; should be 30h => 0..9
0070 405B
0071 405B 05 dec b
0072 405C 18 F3 jr outer
0073 405E
0074 405E C9 ret
0075 405F
0076 405F printInline:
0077 405F E3 EX (SP),HL ; PUSH HL and put RET ADDress into HL
0078 4060 F5 PUSH AF
0079 4061 C5 PUSH BC
0080 4062 7E nextILChar: LD A,(HL)
0081 4063 FE 00 CP 0
0082 4065 28 04 JR Z,endOfPrint
0083 4067 CF RST 08H
0084 4068 23 INC HL
0085 4069 18 F7 JR nextILChar
0086 406B 23 endOfPrint: INC HL ; Get past "null" terminator
0087 406C C1 POP BC
0088 406D F1 POP AF
0089 406E E3 EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
0090 406F C9 RET
0091 4070
0092 4070
0093 4070 .END
tasm: Number of errors = 0

88
Z80 CPM and bootloader (basmon)/source/CH376S~1.LST Normal file
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0001 0000 LF .EQU 0AH ;line feed
0002 0000 FF .EQU 0CH ;form feed
0003 0000 CR .EQU 0DH ;carriage RETurn
0004 0000 DOT .EQU '.'
0005 0000 CH375_CMD_CHECK_EXIST .EQU 06H
0006 0000 CH375_CMD_RESET_ALL .EQU 05H
0007 0000
0008 4000 .ORG 4000H
0009 4000
0010 4000 CD 64 40 CALL printInline
0011 4003 436865636B20 .TEXT "Check CH376s communication"
0011 4009 43483337367320636F6D6D756E69636174696F6E
0012 401D 0D 0A 00 .DB CR,LF,0
0013 4020
0014 4020 CD 64 40 CALL printInline
0015 4023 53656E642041 .TEXT "Send A"
0016 4029 0D 0A 00 .DB CR,LF,0
0017 402C
0018 402C 3E 05 ld a, CH375_CMD_RESET_ALL
0019 402E D3 20 out (20h),a
0020 4030
0021 4030 3E 06 ld a, CH375_CMD_CHECK_EXIST
0022 4032 D3 20 out (20h),a
0023 4034 3E 41 ld a, 'A'
0024 4036 D3 20 out (20h),a
0025 4038 ; receive result
0026 4038 AF xor a
0027 4039 D3 20 out (20h),a
0028 403B DB 20 in a, (20h)
0029 403D EE FF xor 255
0030 403F
0031 403F CD 64 40 CALL printInline
0032 4042 526563656976 .TEXT "Received "
0032 4048 656420
0033 404B 00 .DB 0
0034 404C
0035 404C CF RST 08H ; print contents of A
0036 404D
0037 404D CD 64 40 CALL printInline
0038 4050 0D 0A 00 .DB CR,LF,0
0039 4053
0040 4053 C9 ret
0041 4054
0042 4054 ; LOOPBACK TEST
0043 4054
0044 4054 06 39 ld b, 39h
0045 4056 outer:
0046 4056 78 ld a, b
0047 4057 FE 2F cp 2fh
0048 4059 C8 ret z
0049 405A ; send out
0050 405A D3 20 out (20h),a
0051 405C ;inner:
0052 405C ; ld a, DOT
0053 405C ; rst 08h
0054 405C ; in a, (21h)
0055 405C ; bit 0,a
0056 405C ; jr z, inner
0057 405C AF xor a
0058 405D
0059 405D ; read back
0060 405D DB 20 in a, (20h)
0061 405F CF rst 08h ; should be 30h => 0..9
0062 4060
0063 4060 05 dec b
0064 4061 18 F3 jr outer
0065 4063
0066 4063 C9 ret
0067 4064
0068 4064 printInline:
0069 4064 E3 EX (SP),HL ; PUSH HL and put RET ADDress into HL
0070 4065 F5 PUSH AF
0071 4066 C5 PUSH BC
0072 4067 7E nextILChar: LD A,(HL)
0073 4068 FE 00 CP 0
0074 406A 28 04 JR Z,endOfPrint
0075 406C CF RST 08H
0076 406D 23 INC HL
0077 406E 18 F7 JR nextILChar
0078 4070 23 endOfPrint: INC HL ; Get past "null" terminator
0079 4071 C1 POP BC
0080 4072 F1 POP AF
0081 4073 E3 EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
0082 4074 C9 RET
0083 4075
0084 4075
0085 4075 .END
tasm: Number of errors = 0

3781
Z80 CPM and bootloader (basmon)/source/CPM22.LST Normal file
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290
Z80 CPM and bootloader (basmon)/source/DOWNLOAD.LST Normal file
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@@ -0,0 +1,290 @@
0001 0000 ;==================================================================================
0002 0000 ; Contents of this file are copyright Grant Searle
0003 0000 ; HEX routine from Joel Owens.
0004 0000 ;
0005 0000 ; You have permission to use this for NON COMMERCIAL USE ONLY
0006 0000 ; If you wish to use it elsewhere, please include an acknowledgement to myself.
0007 0000 ;
0008 0000 ; http://searle.hostei.com/grant/index.html
0009 0000 ;
0010 0000 ; eMail: home.micros01@btinternet.com
0011 0000 ;
0012 0000 ; If the above don't work, please perform an Internet search to see if I have
0013 0000 ; updated the web page hosting service.
0014 0000 ;
0015 0000 ;==================================================================================
0016 0000
0017 0000 TPA .EQU 100H
0018 0000 REBOOT .EQU 0H
0019 0000 BDOS .EQU 5H
0020 0000 CONIO .EQU 6
0021 0000 CONINP .EQU 1
0022 0000 CONOUT .EQU 2
0023 0000 PSTRING .EQU 9
0024 0000 MAKEF .EQU 22
0025 0000 CLOSEF .EQU 16
0026 0000 WRITES .EQU 21
0027 0000 DELF .EQU 19
0028 0000 SETUSR .EQU 32
0029 0000
0030 0000 CR .EQU 0DH
0031 0000 LF .EQU 0AH
0032 0000
0033 0000 FCB .EQU 05CH
0034 0000 BUFF .EQU 080H
0035 0000
0036 0100 .ORG TPA
0037 0100
0038 0100
0039 0100 3E 00 LD A,0
0040 0102 32 6D 02 LD (buffPos),A
0041 0105 32 71 02 LD (checkSum),A
0042 0108 32 72 02 LD (byteCount),A
0043 010B 32 70 02 LD (printCount),A
0044 010E 21 80 00 LD HL,BUFF
0045 0111 22 6E 02 LD (buffPtr),HL
0046 0114
0047 0114
0048 0114 CD 39 02 WAITLT: CALL GETCHR
0049 0117 FE 55 CP 'U'
0050 0119 CA 2A 02 JP Z,SETUSER
0051 011C FE 3A CP ':'
0052 011E 20 F4 JR NZ,WAITLT
0053 0120
0054 0120
0055 0120 0E 13 LD C,DELF
0056 0122 11 5C 00 LD DE,FCB
0057 0125 CD 05 00 CALL BDOS
0058 0128
0059 0128 0E 16 LD C,MAKEF
0060 012A 11 5C 00 LD DE,FCB
0061 012D CD 05 00 CALL BDOS
0062 0130
0063 0130 GETHEX:
0064 0130 CD 39 02 CALL GETCHR
0065 0133 FE 3E CP '>'
0066 0135 28 61 JR Z,CLOSE
0067 0137 47 LD B,A
0068 0138 C5 PUSH BC
0069 0139 CD 39 02 CALL GETCHR
0070 013C C1 POP BC
0071 013D 4F LD C,A
0072 013E
0073 013E CD 4C 02 CALL BCTOA
0074 0141
0075 0141 47 LD B,A
0076 0142 3A 71 02 LD A,(checkSum)
0077 0145 80 ADD A,B
0078 0146 32 71 02 LD (checkSum),A
0079 0149 3A 72 02 LD A,(byteCount)
0080 014C 3C INC A
0081 014D 32 72 02 LD (byteCount),A
0082 0150
0083 0150 78 LD A,B
0084 0151
0085 0151 2A 6E 02 LD HL,(buffPtr)
0086 0154
0087 0154 77 LD (HL),A
0088 0155 23 INC HL
0089 0156 22 6E 02 LD (buffPtr),HL
0090 0159
0091 0159 3A 6D 02 LD A,(buffPos)
0092 015C 3C INC A
0093 015D 32 6D 02 LD (buffPos),A
0094 0160 FE 80 CP 80H
0095 0162
0096 0162 20 32 JR NZ,NOWRITE
0097 0164
0098 0164 0E 15 LD C,WRITES
0099 0166 11 5C 00 LD DE,FCB
0100 0169 CD 05 00 CALL BDOS
0101 016C 3E 2E LD A,'.'
0102 016E CD 45 02 CALL PUTCHR
0103 0171
0104 0171 ; New line every 8K (64 dots)
0105 0171 3A 70 02 LD A,(printCount)
0106 0174 3C INC A
0107 0175 FE 40 CP 64
0108 0177 20 0F JR NZ,noCRLF
0109 0179 32 70 02 LD (printCount),A
0110 017C 3E 0D LD A,CR
0111 017E CD 45 02 CALL PUTCHR
0112 0181 3E 0A LD A,LF
0113 0183 CD 45 02 CALL PUTCHR
0114 0186 3E 00 LD A,0
0115 0188 32 70 02 noCRLF: LD (printCount),A
0116 018B
0117 018B 21 80 00 LD HL,BUFF
0118 018E 22 6E 02 LD (buffPtr),HL
0119 0191
0120 0191 3E 00 LD A,0
0121 0193 32 6D 02 LD (buffPos),A
0122 0196 NOWRITE:
0123 0196 18 98 JR GETHEX
0124 0198
0125 0198
0126 0198 CLOSE:
0127 0198
0128 0198 3A 6D 02 LD A,(buffPos)
0129 019B FE 00 CP 0
0130 019D 28 0D JR Z,NOWRITE2
0131 019F
0132 019F 0E 15 LD C,WRITES
0133 01A1 11 5C 00 LD DE,FCB
0134 01A4 CD 05 00 CALL BDOS
0135 01A7 3E 2E LD A,'.'
0136 01A9 CD 45 02 CALL PUTCHR
0137 01AC
0138 01AC NOWRITE2:
0139 01AC 0E 10 LD C,CLOSEF
0140 01AE 11 5C 00 LD DE,FCB
0141 01B1 CD 05 00 CALL BDOS
0142 01B4
0143 01B4 ; Byte count (lower 8 bits)
0144 01B4 CD 39 02 CALL GETCHR
0145 01B7 47 LD B,A
0146 01B8 C5 PUSH BC
0147 01B9 CD 39 02 CALL GETCHR
0148 01BC C1 POP BC
0149 01BD 4F LD C,A
0150 01BE
0151 01BE CD 4C 02 CALL BCTOA
0152 01C1 47 LD B,A
0153 01C2 3A 72 02 LD A,(byteCount)
0154 01C5 90 SUB B
0155 01C6 FE 00 CP 0
0156 01C8 28 1A JR Z,byteCountOK
0157 01CA
0158 01CA 3E 0D LD A,CR
0159 01CC CD 45 02 CALL PUTCHR
0160 01CF 3E 0A LD A,LF
0161 01D1 CD 45 02 CALL PUTCHR
0162 01D4
0163 01D4 11 91 02 LD DE,countErrMess
0164 01D7 0E 09 LD C,PSTRING
0165 01D9 CD 05 00 CALL BDOS
0166 01DC
0167 01DC ; Sink remaining 2 bytes
0168 01DC CD 39 02 CALL GETCHR
0169 01DF CD 39 02 CALL GETCHR
0170 01E2
0171 01E2 18 3C JR FINISH
0172 01E4
0173 01E4 byteCountOK:
0174 01E4
0175 01E4 ; Checksum
0176 01E4 CD 39 02 CALL GETCHR
0177 01E7 47 LD B,A
0178 01E8 C5 PUSH BC
0179 01E9 CD 39 02 CALL GETCHR
0180 01EC C1 POP BC
0181 01ED 4F LD C,A
0182 01EE
0183 01EE CD 4C 02 CALL BCTOA
0184 01F1 47 LD B,A
0185 01F2 3A 71 02 LD A,(checkSum)
0186 01F5 90 SUB B
0187 01F6 FE 00 CP 0
0188 01F8 28 14 JR Z,checksumOK
0189 01FA
0190 01FA 3E 0D LD A,CR
0191 01FC CD 45 02 CALL PUTCHR
0192 01FF 3E 0A LD A,LF
0193 0201 CD 45 02 CALL PUTCHR
0194 0204
0195 0204 11 76 02 LD DE,chkErrMess
0196 0207 0E 09 LD C,PSTRING
0197 0209 CD 05 00 CALL BDOS
0198 020C 18 12 JR FINISH
0199 020E
0200 020E checksumOK:
0201 020E 3E 0D LD A,CR
0202 0210 CD 45 02 CALL PUTCHR
0203 0213 3E 0A LD A,LF
0204 0215 CD 45 02 CALL PUTCHR
0205 0218
0206 0218 11 73 02 LD DE,OKMess
0207 021B 0E 09 LD C,PSTRING
0208 021D CD 05 00 CALL BDOS
0209 0220
0210 0220
0211 0220
0212 0220 FINISH:
0213 0220 0E 20 LD C,SETUSR
0214 0222 1E 00 LD E,0
0215 0224 CD 05 00 CALL BDOS
0216 0227
0217 0227 C3 00 00 JP REBOOT
0218 022A
0219 022A
0220 022A SETUSER:
0221 022A CD 39 02 CALL GETCHR
0222 022D CD 65 02 CALL HEX2VAL
0223 0230 5F LD E,A
0224 0231 0E 20 LD C,SETUSR
0225 0233 CD 05 00 CALL BDOS
0226 0236 C3 14 01 JP WAITLT
0227 0239
0228 0239
0229 0239 ; Get a char into A
0230 0239 ;GETCHR: LD C,CONINP
0231 0239 ; CALL BDOS
0232 0239 ; RET
0233 0239
0234 0239 ; Wait for a char into A (no echo)
0235 0239 GETCHR:
0236 0239 1E FF LD E,$FF
0237 023B 0E 06 LD C,CONIO
0238 023D CD 05 00 CALL BDOS
0239 0240 FE 00 CP 0
0240 0242 28 F5 JR Z,GETCHR
0241 0244 C9 RET
0242 0245
0243 0245 ; Write A to output
0244 0245 0E 02 PUTCHR: LD C,CONOUT
0245 0247 5F LD E,A
0246 0248 CD 05 00 CALL BDOS
0247 024B C9 RET
0248 024C
0249 024C
0250 024C ;------------------------------------------------------------------------------
0251 024C ; Convert ASCII characters in B C registers to a byte value in A
0252 024C ;------------------------------------------------------------------------------
0253 024C 78 BCTOA LD A,B ; Move the hi order byte to A
0254 024D D6 30 SUB $30 ; Take it down from Ascii
0255 024F FE 0A CP $0A ; Are we in the 0-9 range here?
0256 0251 38 02 JR C,BCTOA1 ; If so, get the next nybble
0257 0253 D6 07 SUB $07 ; But if A-F, take it down some more
0258 0255 07 BCTOA1 RLCA ; Rotate the nybble from low to high
0259 0256 07 RLCA ; One bit at a time
0260 0257 07 RLCA ; Until we
0261 0258 07 RLCA ; Get there with it
0262 0259 47 LD B,A ; Save the converted high nybble
0263 025A 79 LD A,C ; Now get the low order byte
0264 025B D6 30 SUB $30 ; Convert it down from Ascii
0265 025D FE 0A CP $0A ; 0-9 at this point?
0266 025F 38 02 JR C,BCTOA2 ; Good enough then, but
0267 0261 D6 07 SUB $07 ; Take off 7 more if it's A-F
0268 0263 80 BCTOA2 ADD A,B ; Add in the high order nybble
0269 0264 C9 RET
0270 0265
0271 0265 ; Change Hex in A to actual value in A
0272 0265 D6 30 HEX2VAL SUB $30
0273 0267 FE 0A CP $0A
0274 0269 D8 RET C
0275 026A D6 07 SUB $07
0276 026C C9 RET
0277 026D
0278 026D
0279 026D 00 buffPos .DB 0H
0280 026E 00 00 buffPtr .DW 0000H
0281 0270 00 printCount .DB 0H
0282 0271 00 checkSum .DB 0H
0283 0272 00 byteCount .DB 0H
0284 0273 4F 4B 24 OKMess .BYTE "OK$"
0285 0276 3D3D3D3D3D3DchkErrMess .BYTE "======Checksum Error======$"
0285 027C 436865636B73756D204572726F723D3D3D3D3D3D24
0286 0291 3D3D3D3D3D3DcountErrMess .BYTE "======File Length Error======$"
0286 0297 46696C65204C656E677468204572726F723D3D3D3D3D3D24
0287 02AF .END
tasm: Number of errors = 0

230
Z80 CPM and bootloader (basmon)/source/FORM128.LST Normal file
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@@ -0,0 +1,230 @@
0001 0000 ;==================================================================================
0002 0000 ; Contents of this file are copyright Grant Searle
0003 0000 ;
0004 0000 ; You have permission to use this for NON COMMERCIAL USE ONLY
0005 0000 ; If you wish to use it elsewhere, please include an acknowledgement to myself.
0006 0000 ;
0007 0000 ; http://searle.hostei.com/grant/index.html
0008 0000 ;
0009 0000 ; eMail: home.micros01@btinternet.com
0010 0000 ;
0011 0000 ; If the above don't work, please perform an Internet search to see if I have
0012 0000 ; updated the web page hosting service.
0013 0000 ;
0014 0000 ;==================================================================================
0015 0000
0016 0000 numDrives .EQU 15 ; Not including A:
0017 0000
0018 0000
0019 0000 SD_DATA .EQU 088H
0020 0000 SD_CONTROL .EQU 089H
0021 0000 SD_STATUS .EQU 089H
0022 0000 SD_LBA0 .EQU 08AH
0023 0000 SD_LBA1 .EQU 08BH
0024 0000 SD_LBA2 .EQU 08CH
0025 0000
0026 0000 LF .EQU 0AH ;line feed
0027 0000 FF .EQU 0CH ;form feed
0028 0000 CR .EQU 0DH ;carriage RETurn
0029 0000
0030 0000 ;====================================================================================
0031 0000
0032 5000 .ORG 5000H ; Format program origin.
0033 5000
0034 5000
0035 5000 CD D5 50 CALL printInline
0036 5003 43502F4D2046 .TEXT "CP/M Formatter 2.0 by G. Searle 2013"
0036 5009 6F726D617474657220322E3020627920472E20536561726C652032303133
0037 5027 0D 0A 00 .DB CR,LF,0
0038 502A
0039 502A 3E 41 LD A,'A'
0040 502C 32 E7 50 LD (drvName),A
0041 502F
0042 502F ; There are 512 directory entries per disk, 4 DIR entries per sector
0043 502F ; So 128 x 128 byte sectors are to be initialised
0044 502F ; The drive uses 512 byte sectors, so 32 x 512 byte sectors per disk
0045 502F ; require initialisation
0046 502F
0047 502F ;Drive 0 (A:) is slightly different due to reserved track, so DIR sector starts at 32
0048 502F 3A E7 50 LD A,(drvName)
0049 5032 CF RST 08H ; Print drive letter
0050 5033 3C INC A
0051 5034 32 E7 50 LD (drvName),A
0052 5037
0053 5037 3E 20 LD A,$20
0054 5039 32 E6 50 LD (secNo),A
0055 503C
0056 503C processSectorA:
0057 503C
0058 503C 3A E6 50 LD A,(secNo)
0059 503F D3 8A OUT (SD_LBA0),A
0060 5041 3E 00 LD A,0
0061 5043 D3 8B OUT (SD_LBA1),A
0062 5045 3E 00 LD A,0
0063 5047 D3 8C OUT (SD_LBA2),A
0064 5049 3E E0 LD a,$E0
0065 504B
0066 504B CD A7 50 call writehst
0067 504E
0068 504E 3A E6 50 LD A,(secNo)
0069 5051 3C INC A
0070 5052 32 E6 50 LD (secNo),A
0071 5055 FE 40 CP $40
0072 5057 20 E3 JR NZ, processSectorA
0073 5059
0074 5059
0075 5059
0076 5059 ;Drive 1 onwards (B: etc) don't have reserved tracks, so sector starts at 0
0077 5059
0078 5059 11 40 00 LD DE,$0040 ; HL increment
0079 505C 21 40 00 LD HL,$0040 ; H = LBA2, L=LBA1, initialise for drive 1 (B:)
0080 505F
0081 505F 06 0F LD B,numDrives
0082 5061
0083 5061 processDirs:
0084 5061
0085 5061 3A E7 50 LD A,(drvName)
0086 5064 CF RST 08H ; Print drive letter
0087 5065 3C INC A
0088 5066 32 E7 50 LD (drvName),A
0089 5069
0090 5069 3E 00 LD A,0
0091 506B 32 E6 50 LD (secNo),A
0092 506E
0093 506E processSector:
0094 506E 3A E6 50 LD A,(secNo)
0095 5071 D3 8A OUT (SD_LBA0),A
0096 5073 7D LD A,L
0097 5074 D3 8B OUT (SD_LBA1),A
0098 5076 7C LD A,H
0099 5077 D3 8C OUT (SD_LBA2),A
0100 5079
0101 5079 CD A7 50 call writehst
0102 507C
0103 507C 3A E6 50 LD A,(secNo)
0104 507F 3C INC A
0105 5080 32 E6 50 LD (secNo),A
0106 5083 FE 20 CP $20
0107 5085 20 E7 JR NZ, processSector
0108 5087
0109 5087 19 ADD HL,DE
0110 5088
0111 5088 05 DEC B
0112 5089 20 D6 JR NZ,processDirs
0113 508B
0114 508B CD D5 50 CALL printInline
0115 508E 0D 0A .DB CR,LF
0116 5090 466F726D6174 .TEXT "Formatting complete"
0116 5096 74696E6720636F6D706C657465
0117 50A3 0D 0A 00 .DB CR,LF,0
0118 50A6
0119 50A6 C9 RET
0120 50A7
0121 50A7 ;================================================================================================
0122 50A7 ; Write physical sector to host
0123 50A7 ;================================================================================================
0124 50A7
0125 50A7 writehst:
0126 50A7 F5 PUSH AF
0127 50A8 C5 PUSH BC
0128 50A9 E5 PUSH HL
0129 50AA
0130 50AA DB 89 wrWait1: IN A,(SD_STATUS)
0131 50AC FE 80 CP 128
0132 50AE 20 FA JR NZ,wrWait1
0133 50B0
0134 50B0 ;CALL setLBAaddr
0135 50B0
0136 50B0 3E 01 LD A,$01 ; 01 = Write block
0137 50B2 D3 89 OUT (SD_CONTROL),A
0138 50B4
0139 50B4 0E 04 LD c,4
0140 50B6 wr4secs:
0141 50B6 21 E8 50 LD HL,dirData
0142 50B9 06 80 LD b,128
0143 50BB wrByte:
0144 50BB DB 89 wrWait2: IN A,(SD_STATUS)
0145 50BD FE A0 CP 160 ; Write buffer empty
0146 50BF 20 FA JR NZ,wrWait2
0147 50C1
0148 50C1 ;LD A,'.'
0149 50C1 ;RST 08H
0150 50C1
0151 50C1 ; UPDATE S0urceror, inserted wait cycle between IN and OUT
0152 50C1 ; to resolve unknown write issue in sd_controller.vhd in combination
0153 50C1 ; with MISTer virtual SD interface sys/sd_card.sv
0154 50C1 ; which results in hangs or write errors.
0155 50C1 C5 push bc
0156 50C2 06 32 ld b,50
0157 50C4 _again:
0158 50C4 10 FE djnz _again
0159 50C6 C1 pop bc
0160 50C7 ; END UPDATE
0161 50C7
0162 50C7 7E LD A,(HL)
0163 50C8 D3 88 OUT (SD_DATA),A
0164 50CA
0165 50CA 23 INC HL
0166 50CB 05 dec b
0167 50CC 20 ED JR NZ, wrByte
0168 50CE
0169 50CE 0D dec c
0170 50CF 20 E5 JR NZ,wr4secs
0171 50D1
0172 50D1 E1 POP HL
0173 50D2 C1 POP BC
0174 50D3 F1 POP AF
0175 50D4
0176 50D4 ;XOR a
0177 50D4 ;ld (erflag),a
0178 50D4 C9 RET
0179 50D5
0180 50D5 ;================================================================================================
0181 50D5 ; Utilities
0182 50D5 ;================================================================================================
0183 50D5
0184 50D5 printInline:
0185 50D5 E3 EX (SP),HL ; PUSH HL and put RET ADDress into HL
0186 50D6 F5 PUSH AF
0187 50D7 C5 PUSH BC
0188 50D8 7E nextILChar: LD A,(HL)
0189 50D9 FE 00 CP 0
0190 50DB 28 04 JR Z,endOfPrint
0191 50DD CF RST 08H
0192 50DE 23 INC HL
0193 50DF 18 F7 JR nextILChar
0194 50E1 23 endOfPrint: INC HL ; Get past "null" terminator
0195 50E2 C1 POP BC
0196 50E3 F1 POP AF
0197 50E4 E3 EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
0198 50E5 C9 RET
0199 50E6
0200 50E6
0201 50E6 00 secNo .db 0
0202 50E7 00 drvName .db 0
0203 50E8
0204 50E8
0205 50E8 ; Directory data for 1 x 128 byte sector
0206 50E8 dirData:
0207 50E8 E52020202020 .DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
0207 50EE 20202020202000000000
0208 50F8 000000000000 .DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
0208 50FE 00000000000000000000
0209 5108
0210 5108 E52020202020 .DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
0210 510E 20202020202000000000
0211 5118 000000000000 .DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
0211 511E 00000000000000000000
0212 5128
0213 5128 E52020202020 .DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
0213 512E 20202020202000000000
0214 5138 000000000000 .DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
0214 513E 00000000000000000000
0215 5148
0216 5148 E52020202020 .DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
0216 514E 20202020202000000000
0217 5158 000000000000 .DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
0217 515E 00000000000000000000
0218 5168
0219 5168 .END
tasm: Number of errors = 0

166
Z80 CPM and bootloader (basmon)/source/PUTSYS.LST Normal file
View File

@@ -0,0 +1,166 @@
0001 0000 ;==================================================================================
0002 0000 ; Contents of this file are copyright Grant Searle
0003 0000 ;
0004 0000 ; You have permission to use this for NON COMMERCIAL USE ONLY
0005 0000 ; If you wish to use it elsewhere, please include an acknowledgement to myself.
0006 0000 ;
0007 0000 ; http://searle.hostei.com/grant/index.html
0008 0000 ;
0009 0000 ; eMail: home.micros01@btinternet.com
0010 0000 ;
0011 0000 ; If the above don't work, please perform an Internet search to see if I have
0012 0000 ; updated the web page hosting service.
0013 0000 ;
0014 0000 ;==================================================================================
0015 0000
0016 0000 loadAddr .EQU 0D000h
0017 0000 numSecs .EQU 24 ; Number of 512 sectors to be loaded
0018 0000
0019 0000 SD_DATA .EQU 088H
0020 0000 SD_CONTROL .EQU 089H
0021 0000 SD_STATUS .EQU 089H
0022 0000 SD_LBA0 .EQU 08AH
0023 0000 SD_LBA1 .EQU 08BH
0024 0000 SD_LBA2 .EQU 08CH
0025 0000
0026 0000 LF .EQU 0AH ;line feed
0027 0000 FF .EQU 0CH ;form feed
0028 0000 CR .EQU 0DH ;carriage RETurn
0029 0000
0030 0000 ;================================================================================================
0031 0000
0032 5000 .ORG 5000H ; Loader origin.
0033 5000
0034 5000 CD BA 50 CALL printInline
0035 5003 43502F4D2053 .TEXT "CP/M System Transfer by G. Searle 2012-13"
0035 5009 797374656D205472616E7366657220627920472E20536561726C6520323031322D3133
0036 502C 0D 0A 00 .DB CR,LF,0
0037 502F
0038 502F 06 18 LD B,numSecs
0039 5031
0040 5031 3E 00 LD A,0
0041 5033 32 CB 50 LD (lba0),A
0042 5036 32 CC 50 ld (lba1),A
0043 5039 32 CD 50 ld (lba2),A
0044 503C 32 CE 50 ld (lba3),A
0045 503F 21 00 D0 LD HL,loadAddr
0046 5042 22 CF 50 LD (dmaAddr),HL
0047 5045 processSectors:
0048 5045
0049 5045 CD 8C 50 call writehst
0050 5048
0051 5048 11 00 02 LD DE,0200H
0052 504B 2A CF 50 LD HL,(dmaAddr)
0053 504E 19 ADD HL,DE
0054 504F 22 CF 50 LD (dmaAddr),HL
0055 5052 3A CB 50 LD A,(lba0)
0056 5055 3C INC A
0057 5056 32 CB 50 LD (lba0),A
0058 5059
0059 5059 10 EA djnz processSectors
0060 505B
0061 505B CD BA 50 CALL printInline
0062 505E 0D 0A .DB CR,LF
0063 5060 53797374656D .TEXT "System transfer complete"
0063 5066 207472616E7366657220636F6D706C657465
0064 5078 0D 0A 00 .DB CR,LF,0
0065 507B
0066 507B C9 RET
0067 507C
0068 507C ; =========================================================================
0069 507C ; Disk routines as used in CBIOS
0070 507C ; =========================================================================
0071 507C setLBAaddr:
0072 507C 3A CD 50 LD A,(lba2)
0073 507F D3 8C OUT (SD_LBA2),A
0074 5081 3A CC 50 LD A,(lba1)
0075 5084 D3 8B OUT (SD_LBA1),A
0076 5086 3A CB 50 LD A,(lba0)
0077 5089 D3 8A OUT (SD_LBA0),A
0078 508B C9 ret
0079 508C
0080 508C ;================================================================================================
0081 508C ; Write physical sector to host
0082 508C ;================================================================================================
0083 508C
0084 508C writehst:
0085 508C F5 PUSH AF
0086 508D C5 PUSH BC
0087 508E E5 PUSH HL
0088 508F
0089 508F DB 89 wrWait1: IN A,(SD_STATUS)
0090 5091 FE 80 CP 128
0091 5093 20 FA JR NZ,wrWait1
0092 5095
0093 5095 CD 7C 50 CALL setLBAaddr
0094 5098
0095 5098 3E 01 LD A,$01 ; 01 = Write block
0096 509A D3 89 OUT (SD_CONTROL),A
0097 509C
0098 509C 0E 04 LD c,4
0099 509E ;LD HL,hstbuf
0100 509E wr4secs:
0101 509E 06 80 LD b,128
0102 50A0 wrByte:
0103 50A0
0104 50A0 DB 89 wrWait2: IN A,(SD_STATUS)
0105 50A2 FE A0 CP 160 ; Write buffer empty
0106 50A4 20 FA JR NZ,wrWait2
0107 50A6
0108 50A6 ; UPDATE S0urceror, inserted wait cycle between IN and OUT
0109 50A6 ; to resolve unknown write issue in sd_controller.vhd in combination
0110 50A6 ; with MISTer virtual SD interface sys/sd_card.sv
0111 50A6 ; which results in hangs or write errors.
0112 50A6 C5 push bc
0113 50A7 06 32 ld b,50
0114 50A9 _again:
0115 50A9 10 FE djnz _again
0116 50AB C1 pop bc
0117 50AC ; END UPDATE
0118 50AC
0119 50AC 7E LD A,(HL)
0120 50AD D3 88 OUT (SD_DATA),A
0121 50AF 23 INC HL
0122 50B0 05 dec b
0123 50B1 20 ED JR NZ, wrByte
0124 50B3
0125 50B3 0D dec c
0126 50B4 20 E8 JR NZ,wr4secs
0127 50B6
0128 50B6 E1 POP HL
0129 50B7 C1 POP BC
0130 50B8 F1 POP AF
0131 50B9
0132 50B9 ;XOR a
0133 50B9 ;ld (erflag),a
0134 50B9 C9 RET
0135 50BA
0136 50BA
0137 50BA ;================================================================================================
0138 50BA ; Utilities
0139 50BA ;================================================================================================
0140 50BA
0141 50BA printInline:
0142 50BA E3 EX (SP),HL ; PUSH HL and put RET ADDress into HL
0143 50BB F5 PUSH AF
0144 50BC C5 PUSH BC
0145 50BD 7E nextILChar: LD A,(HL)
0146 50BE FE 00 CP 0
0147 50C0 28 04 JR Z,endOfPrint
0148 50C2 CF RST 08H
0149 50C3 23 INC HL
0150 50C4 18 F7 JR nextILChar
0151 50C6 23 endOfPrint: INC HL ; Get past "null" terminator
0152 50C7 C1 POP BC
0153 50C8 F1 POP AF
0154 50C9 E3 EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
0155 50CA C9 RET
0156 50CB
0157 50CB 00 lba0 .DB 00h
0158 50CC 00 lba1 .DB 00h
0159 50CD 00 lba2 .DB 00h
0160 50CE 00 lba3 .DB 00h
0161 50CF 00 00 dmaAddr .dw 0
0162 50D1
0163 50D1 .END
tasm: Number of errors = 0

4992
Z80 CPM and bootloader (basmon)/source/basMon.asm Normal file
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File diff suppressed because it is too large Load Diff

927
Z80 CPM and bootloader (basmon)/source/cbios128.asm Normal file
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@@ -0,0 +1,927 @@
;==================================================================================
; Contents of this file are copyright Grant Searle
; Blocking/unblocking routines are the published version by Digital Research
; (bugfixed, as found on the web)
;
; You have permission to use this for NON COMMERCIAL USE ONLY
; If you wish to use it elsewhere, please include an acknowledgement to myself.
;
; http://searle.hostei.com/grant/index.html
;
; eMail: home.micros01@btinternet.com
;
; If the above don't work, please perform an Internet search to see if I have
; updated the web page hosting service.
;
;==================================================================================
ccp .EQU 0D000h ; Base of CCP.
bdos .EQU ccp + 0806h ; Base of BDOS.
bios .EQU ccp + 1600h ; Base of BIOS.
; Set CP/M low memory datA, vector and buffer addresses.
iobyte .EQU 03h ; Intel standard I/O definition byte.
userdrv .EQU 04h ; Current user number and drive.
tpabuf .EQU 80h ; Default I/O buffer and command line storage.
SD_DATA .EQU 088H
SD_CONTROL .EQU 089H
SD_STATUS .EQU 089H
SD_LBA0 .EQU 08AH
SD_LBA1 .EQU 08BH
SD_LBA2 .EQU 08CH
RTS_HIGH .EQU 0D5H
RTS_LOW .EQU 095H
ACIA0_D .EQU $81
ACIA0_C .EQU $80
ACIA1_D .EQU $83
ACIA1_C .EQU $82
nmi .EQU 66H
blksiz .equ 4096 ;CP/M allocation size
hstsiz .equ 512 ;host disk sector size
hstspt .equ 32 ;host disk sectors/trk
hstblk .equ hstsiz/128 ;CP/M sects/host buff
cpmspt .equ hstblk * hstspt ;CP/M sectors/track
secmsk .equ hstblk-1 ;sector mask
;compute sector mask
;secshf .equ 2 ;log2(hstblk)
wrall .equ 0 ;write to allocated
wrdir .equ 1 ;write to directory
wrual .equ 2 ;write to unallocated
LF .EQU 0AH ;line feed
FF .EQU 0CH ;form feed
CR .EQU 0DH ;carriage RETurn
;================================================================================================
.ORG bios ; BIOS origin.
;================================================================================================
; BIOS jump table.
;================================================================================================
JP boot ; 0 Initialize.
wboote: JP wboot ; 1 Warm boot.
JP const ; 2 Console status.
JP conin ; 3 Console input.
JP conout ; 4 Console OUTput.
JP list ; 5 List OUTput.
JP punch ; 6 punch OUTput.
JP reader ; 7 Reader input.
JP home ; 8 Home disk.
JP seldsk ; 9 Select disk.
JP settrk ; 10 Select track.
JP setsec ; 11 Select sector.
JP setdma ; 12 Set DMA ADDress.
JP read ; 13 Read 128 bytes.
JP write ; 14 Write 128 bytes.
JP listst ; 15 List status.
JP sectran ; 16 Sector translate.
;================================================================================================
; Disk parameter headers for disk 0 to 15
;================================================================================================
dpbase:
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb0,0000h,alv00
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv01
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv02
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv03
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv04
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv05
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv06
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv07
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv08
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv09
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv10
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv11
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv12
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv13
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv14
.DW 0000h,0000h,0000h,0000h,dirbuf,dpb,0000h,alv15
; First drive has a reserved track for CP/M
dpb0:
.DW 128 ;SPT - sectors per track
.DB 5 ;BSH - block shift factor
.DB 31 ;BLM - block mask
.DB 1 ;EXM - Extent mask
.DW 2043 ; (2047-4) DSM - Storage size (blocks - 1)
.DW 511 ;DRM - Number of directory entries - 1
.DB 240 ;AL0 - 1 bit set per directory block
.DB 0 ;AL1 - "
.DW 0 ;CKS - DIR check vector size (DRM+1)/4 (0=fixed disk)
.DW 1 ;OFF - Reserved tracks
dpb:
.DW 128 ;SPT - sectors per track
.DB 5 ;BSH - block shift factor
.DB 31 ;BLM - block mask
.DB 1 ;EXM - Extent mask
.DW 2047 ;DSM - Storage size (blocks - 1)
.DW 511 ;DRM - Number of directory entries - 1
.DB 240 ;AL0 - 1 bit set per directory block
.DB 0 ;AL1 - "
.DW 0 ;CKS - DIR check vector size (DRM+1)/4 (0=fixed disk)
.DW 0 ;OFF - Reserved tracks
;================================================================================================
; Cold boot
;================================================================================================
boot:
DI ; Disable interrupts.
LD SP,biosstack ; Set default stack.
; Turn off ROM
LD A,$01
OUT ($38),A
LD A,RTS_LOW
OUT (ACIA0_C),A ; Initialise ACIA0
OUT (ACIA1_C),A ; Initialise ACIA1
CALL printInline
.DB FF
.TEXT "CP/M BIOS 2.0 by G. Searle 2013"
.DB CR,LF
.DB CR,LF
.TEXT "CP/M 2.2 "
.TEXT "(c)"
.TEXT " 1979 by Digital Research"
.DB CR,LF,0
; CALL sdPreamble??
XOR a ; Clear I/O & drive bytes.
LD (userdrv),A
JP gocpm
;================================================================================================
; Warm boot
;================================================================================================
wboot:
DI ; Disable interrupts.
LD SP,biosstack ; Set default stack.
LD B,11 ; Number of sectors to reload
LD A,0
LD (hstsec),A
OUT (SD_LBA2),A
OUT (SD_LBA1),A
LD HL,ccp
wbRdAllSecs:
wBrdWait1: IN A,(SD_STATUS)
CP 128
JR NZ,wBrdWait1
LD A,(hstsec)
OUT (SD_LBA0),A
LD A,$00 ; 00 = Read block
OUT (SD_CONTROL),A
PUSH BC
LD c,4
wBrd4secs:
LD b,128
wBrdByte:
wBrdWait2: IN A,(SD_STATUS)
CP 224 ; Read byte waiting
JR NZ,wBrdWait2
IN A,(SD_DATA)
LD (HL),A
INC HL
dec b
JR NZ, wBrdByte
dec c
JR NZ,wBrd4secs
LD A,(hstsec)
INC A
LD (hstsec),A
POP BC
DJNZ wbRdAllSecs
;================================================================================================
; Common code for cold and warm boot
;================================================================================================
gocpm:
xor a ;0 to accumulator
ld (hstact),a ;host buffer inactive
ld (unacnt),a ;clear unalloc count
LD HL,tpabuf ; Address of BIOS DMA buffer.
LD (dmaAddr),HL
LD A,0C3h ; Opcode for 'JP'.
LD (00h),A ; Load at start of RAM.
LD HL,wboote ; Address of jump for a warm boot.
LD (01h),HL
LD (05h),A ; Opcode for 'JP'.
LD HL,bdos ; Address of jump for the BDOS.
LD (06h),HL
LD A,(userdrv) ; Save new drive number (0).
LD c,A ; Pass drive number in C.
JP ccp ; Start CP/M by jumping to the CCP.
;================================================================================================
; Console I/O routines
;================================================================================================
;------------------------------------------------------------------------------------------------
const:
LD A,(iobyte)
AND 00001011b ; Mask off console and high bit of reader
CP 00001010b ; redirected to reader on UR1/2 (Serial A)
JR Z,constA
CP 00000010b ; redirected to reader on TTY/RDR (Serial B)
JR Z,constB
AND $03 ; remove the reader from the mask - only console bits then remain
CP $01
JR NZ,constB
constA:
IN A,(ACIA0_C) ; Status byte
AND $01
CP $0 ; Z flag set if no char
JR Z, dataAEmpty
LD A,0FFH
RET
dataAEmpty:
LD A,0
RET
constB:
IN A,(ACIA1_C) ; Status byte
AND $01
CP $0 ; Z flag set if no char
JR Z, dataBEmpty
LD A,0FFH
RET
dataBEmpty:
LD A,0
RET
;------------------------------------------------------------------------------------------------
reader:
PUSH AF
reader2: LD A,(iobyte)
AND $08
CP $08
JR NZ,coninB
JR coninA
;------------------------------------------------------------------------------------------------
conin:
PUSH AF
LD A,(iobyte)
AND $03
CP $02
JR Z,reader2 ; "BAT:" redirect
CP $01
JR NZ,coninB
coninA:
POP AF
waitForCharA:
IN A,(ACIA0_C) ; Status byte
AND $01
CP $0 ; Z flag set if no char
JR Z, waitForCharA
IN A,(ACIA0_D)
RET ; Char ready in A
coninB:
POP AF
waitForCharB:
IN A,(ACIA1_C) ; Status byte
AND $01
CP $0 ; Z flag set if no char
JR Z, waitForCharB
IN A,(ACIA1_D)
RET ; Char ready in A
;------------------------------------------------------------------------------------------------
list: PUSH AF ; Store character
list2: LD A,(iobyte)
AND $C0
CP $40
JR NZ,conoutB1
JR conoutA1
;------------------------------------------------------------------------------------------------
punch: PUSH AF ; Store character
LD A,(iobyte)
AND $20
CP $20
JR NZ,conoutB1
JR conoutA1
;------------------------------------------------------------------------------------------------
conout: PUSH AF
LD A,(iobyte)
AND $03
CP $02
JR Z,list2 ; "BAT:" redirect
CP $01
JR NZ,conoutB1
conoutA1: CALL CKACIA0 ; See if ACIA channel A is finished transmitting
JR Z,conoutA1 ; Loop until ACIA flag signals ready
LD A,C
OUT (ACIA0_D),A ; OUTput the character
POP AF
RET
conoutB1: CALL CKACIA1 ; See if ACIA channel B is finished transmitting
JR Z,conoutB1 ; Loop until ACIA flag signals ready
LD A,C
OUT (ACIA1_D),A ; OUTput the character
POP AF
RET
;------------------------------------------------------------------------------------------------
CKACIA0
IN A,(ACIA0_C) ; Status byte D1=TX Buff Empty, D0=RX char ready
RRCA ; Rotates RX status into Carry Flag,
BIT 0,A ; Set Zero flag if still transmitting character
RET
CKACIA1
IN A,(ACIA1_C) ; Status byte D1=TX Buff Empty, D0=RX char ready
RRCA ; Rotates RX status into Carry Flag,
BIT 0,A ; Set Zero flag if still transmitting character
RET
;------------------------------------------------------------------------------------------------
listst: LD A,$FF ; Return list status of 0xFF (ready).
RET
;================================================================================================
; Disk processing entry points
;================================================================================================
seldsk:
LD HL,$0000
LD A,C
CP 16 ; 16 for 128MB disk, 8 for 64MB disk
jr C,chgdsk ; if invalid drive will give BDOS error
LD A,(userdrv) ; so set the drive back to a:
CP C ; If the default disk is not the same as the
RET NZ ; selected drive then return,
XOR A ; else reset default back to a:
LD (userdrv),A ; otherwise will be stuck in a loop
LD (sekdsk),A
ret
chgdsk: LD (sekdsk),A
RLC a ;*2
RLC a ;*4
RLC a ;*8
RLC a ;*16
LD HL,dpbase
LD b,0
LD c,A
ADD HL,BC
RET
;------------------------------------------------------------------------------------------------
home:
ld a,(hstwrt) ;check for pending write
or a
jr nz,homed
ld (hstact),a ;clear host active flag
homed:
LD BC,0000h
;------------------------------------------------------------------------------------------------
settrk: LD (sektrk),BC ; Set track passed from BDOS in register BC.
RET
;------------------------------------------------------------------------------------------------
setsec: LD (seksec),BC ; Set sector passed from BDOS in register BC.
RET
;------------------------------------------------------------------------------------------------
setdma: LD (dmaAddr),BC ; Set DMA ADDress given by registers BC.
RET
;------------------------------------------------------------------------------------------------
sectran: PUSH BC
POP HL
RET
;------------------------------------------------------------------------------------------------
read:
;read the selected CP/M sector
xor a
ld (unacnt),a
ld a,1
ld (readop),a ;read operation
ld (rsflag),a ;must read data
ld a,wrual
ld (wrtype),a ;treat as unalloc
jp rwoper ;to perform the read
;------------------------------------------------------------------------------------------------
write:
;write the selected CP/M sector
xor a ;0 to accumulator
ld (readop),a ;not a read operation
ld a,c ;write type in c
ld (wrtype),a
cp wrual ;write unallocated?
jr nz,chkuna ;check for unalloc
;
; write to unallocated, set parameters
ld a,blksiz/128 ;next unalloc recs
ld (unacnt),a
ld a,(sekdsk) ;disk to seek
ld (unadsk),a ;unadsk = sekdsk
ld hl,(sektrk)
ld (unatrk),hl ;unatrk = sectrk
ld a,(seksec)
ld (unasec),a ;unasec = seksec
;
chkuna:
; check for write to unallocated sector
ld a,(unacnt) ;any unalloc remain?
or a
jr z,alloc ;skip if not
;
; more unallocated records remain
dec a ;unacnt = unacnt-1
ld (unacnt),a
ld a,(sekdsk) ;same disk?
ld hl,unadsk
cp (hl) ;sekdsk = unadsk?
jp nz,alloc ;skip if not
;
; disks are the same
ld hl,unatrk
call sektrkcmp ;sektrk = unatrk?
jp nz,alloc ;skip if not
;
; tracks are the same
ld a,(seksec) ;same sector?
ld hl,unasec
cp (hl) ;seksec = unasec?
jp nz,alloc ;skip if not
;
; match, move to next sector for future ref
inc (hl) ;unasec = unasec+1
ld a,(hl) ;end of track?
cp cpmspt ;count CP/M sectors
jr c,noovf ;skip if no overflow
;
; overflow to next track
ld (hl),0 ;unasec = 0
ld hl,(unatrk)
inc hl
ld (unatrk),hl ;unatrk = unatrk+1
;
noovf:
;match found, mark as unnecessary read
xor a ;0 to accumulator
ld (rsflag),a ;rsflag = 0
jr rwoper ;to perform the write
;
alloc:
;not an unallocated record, requires pre-read
xor a ;0 to accum
ld (unacnt),a ;unacnt = 0
inc a ;1 to accum
ld (rsflag),a ;rsflag = 1
;------------------------------------------------------------------------------------------------
rwoper:
;enter here to perform the read/write
xor a ;zero to accum
ld (erflag),a ;no errors (yet)
ld a,(seksec) ;compute host sector
or a ;carry = 0
rra ;shift right
or a ;carry = 0
rra ;shift right
ld (sekhst),a ;host sector to seek
;
; active host sector?
ld hl,hstact ;host active flag
ld a,(hl)
ld (hl),1 ;always becomes 1
or a ;was it already?
jr z,filhst ;fill host if not
;
; host buffer active, same as seek buffer?
ld a,(sekdsk)
ld hl,hstdsk ;same disk?
cp (hl) ;sekdsk = hstdsk?
jr nz,nomatch
;
; same disk, same track?
ld hl,hsttrk
call sektrkcmp ;sektrk = hsttrk?
jr nz,nomatch
;
; same disk, same track, same buffer?
ld a,(sekhst)
ld hl,hstsec ;sekhst = hstsec?
cp (hl)
jr z,match ;skip if match
;
nomatch:
;proper disk, but not correct sector
ld a,(hstwrt) ;host written?
or a
call nz,writehst ;clear host buff
;
filhst:
;may have to fill the host buffer
ld a,(sekdsk)
ld (hstdsk),a
ld hl,(sektrk)
ld (hsttrk),hl
ld a,(sekhst)
ld (hstsec),a
ld a,(rsflag) ;need to read?
or a
call nz,readhst ;yes, if 1
xor a ;0 to accum
ld (hstwrt),a ;no pending write
;
match:
;copy data to or from buffer
ld a,(seksec) ;mask buffer number
and secmsk ;least signif bits
ld l,a ;ready to shift
ld h,0 ;double count
add hl,hl
add hl,hl
add hl,hl
add hl,hl
add hl,hl
add hl,hl
add hl,hl
; hl has relative host buffer address
ld de,hstbuf
add hl,de ;hl = host address
ex de,hl ;now in DE
ld hl,(dmaAddr) ;get/put CP/M data
ld c,128 ;length of move
ld a,(readop) ;which way?
or a
jr nz,rwmove ;skip if read
;
; write operation, mark and switch direction
ld a,1
ld (hstwrt),a ;hstwrt = 1
ex de,hl ;source/dest swap
;
rwmove:
;C initially 128, DE is source, HL is dest
ld a,(de) ;source character
inc de
ld (hl),a ;to dest
inc hl
dec c ;loop 128 times
jr nz,rwmove
;
; data has been moved to/from host buffer
ld a,(wrtype) ;write type
cp wrdir ;to directory?
ld a,(erflag) ;in case of errors
ret nz ;no further processing
;
; clear host buffer for directory write
or a ;errors?
ret nz ;skip if so
xor a ;0 to accum
ld (hstwrt),a ;buffer written
call writehst
ld a,(erflag)
ret
;------------------------------------------------------------------------------------------------
;Utility subroutine for 16-bit compare
sektrkcmp:
;HL = .unatrk or .hsttrk, compare with sektrk
ex de,hl
ld hl,sektrk
ld a,(de) ;low byte compare
cp (HL) ;same?
ret nz ;return if not
; low bytes equal, test high 1s
inc de
inc hl
ld a,(de)
cp (hl) ;sets flags
ret
;================================================================================================
; Convert track/head/sector into LBA for physical access to the disk
;================================================================================================
setLBAaddr:
LD HL,(hsttrk)
RLC L
RLC L
RLC L
RLC L
RLC L
LD A,L
AND 0E0H
LD L,A
LD A,(hstsec)
ADD A,L
LD (lba0),A
LD HL,(hsttrk)
RRC L
RRC L
RRC L
LD A,L
AND 01FH
LD L,A
RLC H
RLC H
RLC H
RLC H
RLC H
LD A,H
AND 020H
LD H,A
LD A,(hstdsk)
RLC a
RLC a
RLC a
RLC a
RLC a
RLC a
AND 0C0H
ADD A,H
ADD A,L
LD (lba1),A
LD A,(hstdsk)
RRC A
RRC A
AND 03H
LD (lba2),A
LD a,00H
LD (lba3),A
; Transfer LBA to disk (LBA3 not used on SD card)
LD A,(lba2)
OUT (SD_LBA2),A
LD A,(lba1)
OUT (SD_LBA1),A
LD A,(lba0)
OUT (SD_LBA0),A
RET
;================================================================================================
; Read physical sector from host
;================================================================================================
readhst:
PUSH AF
PUSH BC
PUSH HL
rdWait1: IN A,(SD_STATUS)
CP 128
JR NZ,rdWait1
CALL setLBAaddr
LD A,$00 ; 00 = Read block
OUT (SD_CONTROL),A
LD c,4
LD HL,hstbuf
rd4secs:
LD b,128
rdByte:
rdWait2: IN A,(SD_STATUS)
CP 224 ; Read byte waiting
JR NZ,rdWait2
IN A,(SD_DATA)
LD (HL),A
INC HL
dec b
JR NZ, rdByte
dec c
JR NZ,rd4secs
POP HL
POP BC
POP AF
XOR a
ld (erflag),a
RET
;================================================================================================
; Write physical sector to host
;================================================================================================
writehst:
PUSH AF
PUSH BC
PUSH HL
wrWait1: IN A,(SD_STATUS)
CP 128
JR NZ,wrWait1
CALL setLBAaddr
LD A,$01 ; 01 = Write block
OUT (SD_CONTROL),A
LD c,4
LD HL,hstbuf
wr4secs:
LD b,128
wrByte:
wrWait2: IN A,(SD_STATUS)
CP 160 ; Write buffer empty
JR NZ,wrWait2
; UPDATE S0urceror, inserted wait cycle between IN and OUT
; to resolve unknown write issue in sd_controller.vhd in combination
; with MISTer virtual SD interface sys/sd_card.sv
; which results in hangs or write errors.
push bc
ld b,50
_again:
djnz _again
pop bc
; END UPDATE
LD A,(HL)
OUT (SD_DATA),A
INC HL
dec b
JR NZ, wrByte
dec c
JR NZ,wr4secs
POP HL
POP BC
POP AF
XOR a
ld (erflag),a
RET
;================================================================================================
; Utilities
;================================================================================================
printInline:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nextILChar: LD A,(HL)
CP 0
JR Z,endOfPrint
LD C,A
CALL conout ; Print to TTY
iNC HL
JR nextILChar
endOfPrint: INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
;================================================================================================
; Data storage
;================================================================================================
dirbuf: .ds 128 ;scratch directory area
alv00: .ds 257 ;allocation vector 0
alv01: .ds 257 ;allocation vector 1
alv02: .ds 257 ;allocation vector 2
alv03: .ds 257 ;allocation vector 3
alv04: .ds 257 ;allocation vector 4
alv05: .ds 257 ;allocation vector 5
alv06: .ds 257 ;allocation vector 6
alv07: .ds 257 ;allocation vector 7
alv08: .ds 257 ;allocation vector 8
alv09: .ds 257 ;allocation vector 9
alv10: .ds 257 ;allocation vector 10
alv11: .ds 257 ;allocation vector 11
alv12: .ds 257 ;allocation vector 12
alv13: .ds 257 ;allocation vector 13
alv14: .ds 257 ;allocation vector 14
alv15: .ds 257 ;allocation vector 15
lba0 .DB 00h
lba1 .DB 00h
lba2 .DB 00h
lba3 .DB 00h
.DS 020h ; Start of BIOS stack area.
biosstack: .EQU $
sekdsk: .ds 1 ;seek disk number
sektrk: .ds 2 ;seek track number
seksec: .ds 2 ;seek sector number
;
hstdsk: .ds 1 ;host disk number
hsttrk: .ds 2 ;host track number
hstsec: .ds 1 ;host sector number
;
sekhst: .ds 1 ;seek shr secshf
hstact: .ds 1 ;host active flag
hstwrt: .ds 1 ;host written flag
;
unacnt: .ds 1 ;unalloc rec cnt
unadsk: .ds 1 ;last unalloc disk
unatrk: .ds 2 ;last unalloc track
unasec: .ds 1 ;last unalloc sector
;
erflag: .ds 1 ;error reporting
rsflag: .ds 1 ;read sector flag
readop: .ds 1 ;1 if read operation
wrtype: .ds 1 ;write operation type
dmaAddr: .ds 2 ;last dma address
hstbuf: .ds 512 ;host buffer
hstBufEnd: .EQU $
biosEnd: .EQU $
; Disable the ROM, pop the active IO port from the stack (supplied by monitor),
; then start CP/M
popAndRun:
LD A,$01
OUT ($38),A
POP AF
CP $01
JR Z,consoleAtB
LD A,$01 ;(List is TTY:, Punch is TTY:, Reader is TTY:, Console is CRT:)
JR setIOByte
consoleAtB: LD A,$00 ;(List is TTY:, Punch is TTY:, Reader is TTY:, Console is TTY:)
setIOByte: LD (iobyte),A
JP bios
;=================================================================================
; Relocate TPA area from 4100 to 0100 then start CP/M
; Used to manually transfer a loaded program after CP/M was previously loaded
;=================================================================================
.org 0FFE8H
LD A,$01
OUT ($38),A
LD HL,04100H
LD DE,00100H
LD BC,08F00H
LDIR
JP bios
;=================================================================================
; Normal start CP/M vector
;=================================================================================
.ORG 0FFFEH
.dw popAndRun
.END

93
Z80 CPM and bootloader (basmon)/source/ch376s.asm Normal file
View File

@@ -0,0 +1,93 @@
LF .EQU 0AH ;line feed
FF .EQU 0CH ;form feed
CR .EQU 0DH ;carriage RETurn
DOT .EQU '.'
CH375_CMD_CHECK_EXIST .EQU 06H
CH375_CMD_RESET_ALL .EQU 05H
.ORG 4000H
CALL printInline
.TEXT "Check CH376s communication"
.DB CR,LF,0
CALL printInline
.TEXT "Send A"
.DB CR,LF,0
;ld a, CH375_CMD_RESET_ALL
;out (20h),a
;ld a, CH375_CMD_CHECK_EXIST
;out (20h),a
ld b, 10
ld a, 0AAH
_again:
out (20h),a
push bc
ld b, 50
_again2:
djnz _again2
pop bc
djnz _again
; receive result
;xor a
;out (20h),a
;in a, (20h)
;xor 255
CALL printInline
.TEXT "Received "
.DB 0
RST 08H ; print contents of A
CALL printInline
.DB CR,LF,0
ret
; LOOPBACK TEST
ld b, 39h
outer:
ld a, b
cp 2fh
ret z
; send out
out (20h),a
;inner:
; ld a, DOT
; rst 08h
; in a, (21h)
; bit 0,a
; jr z, inner
xor a
; read back
in a, (20h)
rst 08h ; should be 30h => 0..9
dec b
jr outer
ret
printInline:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nextILChar: LD A,(HL)
CP 0
JR Z,endOfPrint
RST 08H
INC HL
JR nextILChar
endOfPrint: INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
.END

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Z80 CPM and bootloader (basmon)/source/ch376s.bin Normal file
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3750
Z80 CPM and bootloader (basmon)/source/cpm22.asm Normal file
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287
Z80 CPM and bootloader (basmon)/source/download.asm Normal file
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;==================================================================================
; Contents of this file are copyright Grant Searle
; HEX routine from Joel Owens.
;
; You have permission to use this for NON COMMERCIAL USE ONLY
; If you wish to use it elsewhere, please include an acknowledgement to myself.
;
; http://searle.hostei.com/grant/index.html
;
; eMail: home.micros01@btinternet.com
;
; If the above don't work, please perform an Internet search to see if I have
; updated the web page hosting service.
;
;==================================================================================
TPA .EQU 100H
REBOOT .EQU 0H
BDOS .EQU 5H
CONIO .EQU 6
CONINP .EQU 1
CONOUT .EQU 2
PSTRING .EQU 9
MAKEF .EQU 22
CLOSEF .EQU 16
WRITES .EQU 21
DELF .EQU 19
SETUSR .EQU 32
CR .EQU 0DH
LF .EQU 0AH
FCB .EQU 05CH
BUFF .EQU 080H
.ORG TPA
LD A,0
LD (buffPos),A
LD (checkSum),A
LD (byteCount),A
LD (printCount),A
LD HL,BUFF
LD (buffPtr),HL
WAITLT: CALL GETCHR
CP 'U'
JP Z,SETUSER
CP ':'
JR NZ,WAITLT
LD C,DELF
LD DE,FCB
CALL BDOS
LD C,MAKEF
LD DE,FCB
CALL BDOS
GETHEX:
CALL GETCHR
CP '>'
JR Z,CLOSE
LD B,A
PUSH BC
CALL GETCHR
POP BC
LD C,A
CALL BCTOA
LD B,A
LD A,(checkSum)
ADD A,B
LD (checkSum),A
LD A,(byteCount)
INC A
LD (byteCount),A
LD A,B
LD HL,(buffPtr)
LD (HL),A
INC HL
LD (buffPtr),HL
LD A,(buffPos)
INC A
LD (buffPos),A
CP 80H
JR NZ,NOWRITE
LD C,WRITES
LD DE,FCB
CALL BDOS
LD A,'.'
CALL PUTCHR
; New line every 8K (64 dots)
LD A,(printCount)
INC A
CP 64
JR NZ,noCRLF
LD (printCount),A
LD A,CR
CALL PUTCHR
LD A,LF
CALL PUTCHR
LD A,0
noCRLF: LD (printCount),A
LD HL,BUFF
LD (buffPtr),HL
LD A,0
LD (buffPos),A
NOWRITE:
JR GETHEX
CLOSE:
LD A,(buffPos)
CP 0
JR Z,NOWRITE2
LD C,WRITES
LD DE,FCB
CALL BDOS
LD A,'.'
CALL PUTCHR
NOWRITE2:
LD C,CLOSEF
LD DE,FCB
CALL BDOS
; Byte count (lower 8 bits)
CALL GETCHR
LD B,A
PUSH BC
CALL GETCHR
POP BC
LD C,A
CALL BCTOA
LD B,A
LD A,(byteCount)
SUB B
CP 0
JR Z,byteCountOK
LD A,CR
CALL PUTCHR
LD A,LF
CALL PUTCHR
LD DE,countErrMess
LD C,PSTRING
CALL BDOS
; Sink remaining 2 bytes
CALL GETCHR
CALL GETCHR
JR FINISH
byteCountOK:
; Checksum
CALL GETCHR
LD B,A
PUSH BC
CALL GETCHR
POP BC
LD C,A
CALL BCTOA
LD B,A
LD A,(checkSum)
SUB B
CP 0
JR Z,checksumOK
LD A,CR
CALL PUTCHR
LD A,LF
CALL PUTCHR
LD DE,chkErrMess
LD C,PSTRING
CALL BDOS
JR FINISH
checksumOK:
LD A,CR
CALL PUTCHR
LD A,LF
CALL PUTCHR
LD DE,OKMess
LD C,PSTRING
CALL BDOS
FINISH:
LD C,SETUSR
LD E,0
CALL BDOS
JP REBOOT
SETUSER:
CALL GETCHR
CALL HEX2VAL
LD E,A
LD C,SETUSR
CALL BDOS
JP WAITLT
; Get a char into A
;GETCHR: LD C,CONINP
; CALL BDOS
; RET
; Wait for a char into A (no echo)
GETCHR:
LD E,$FF
LD C,CONIO
CALL BDOS
CP 0
JR Z,GETCHR
RET
; Write A to output
PUTCHR: LD C,CONOUT
LD E,A
CALL BDOS
RET
;------------------------------------------------------------------------------
; Convert ASCII characters in B C registers to a byte value in A
;------------------------------------------------------------------------------
BCTOA LD A,B ; Move the hi order byte to A
SUB $30 ; Take it down from Ascii
CP $0A ; Are we in the 0-9 range here?
JR C,BCTOA1 ; If so, get the next nybble
SUB $07 ; But if A-F, take it down some more
BCTOA1 RLCA ; Rotate the nybble from low to high
RLCA ; One bit at a time
RLCA ; Until we
RLCA ; Get there with it
LD B,A ; Save the converted high nybble
LD A,C ; Now get the low order byte
SUB $30 ; Convert it down from Ascii
CP $0A ; 0-9 at this point?
JR C,BCTOA2 ; Good enough then, but
SUB $07 ; Take off 7 more if it's A-F
BCTOA2 ADD A,B ; Add in the high order nybble
RET
; Change Hex in A to actual value in A
HEX2VAL SUB $30
CP $0A
RET C
SUB $07
RET
buffPos .DB 0H
buffPtr .DW 0000H
printCount .DB 0H
checkSum .DB 0H
byteCount .DB 0H
OKMess .BYTE "OK$"
chkErrMess .BYTE "======Checksum Error======$"
countErrMess .BYTE "======File Length Error======$"
.END

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Z80 CPM and bootloader (basmon)/source/form128.asm Normal file
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;==================================================================================
; Contents of this file are copyright Grant Searle
;
; You have permission to use this for NON COMMERCIAL USE ONLY
; If you wish to use it elsewhere, please include an acknowledgement to myself.
;
; http://searle.hostei.com/grant/index.html
;
; eMail: home.micros01@btinternet.com
;
; If the above don't work, please perform an Internet search to see if I have
; updated the web page hosting service.
;
;==================================================================================
numDrives .EQU 15 ; Not including A:
SD_DATA .EQU 088H
SD_CONTROL .EQU 089H
SD_STATUS .EQU 089H
SD_LBA0 .EQU 08AH
SD_LBA1 .EQU 08BH
SD_LBA2 .EQU 08CH
LF .EQU 0AH ;line feed
FF .EQU 0CH ;form feed
CR .EQU 0DH ;carriage RETurn
;====================================================================================
.ORG 5000H ; Format program origin.
CALL printInline
.TEXT "CP/M Formatter 2.0 by G. Searle 2013"
.DB CR,LF,0
LD A,'A'
LD (drvName),A
; There are 512 directory entries per disk, 4 DIR entries per sector
; So 128 x 128 byte sectors are to be initialised
; The drive uses 512 byte sectors, so 32 x 512 byte sectors per disk
; require initialisation
;Drive 0 (A:) is slightly different due to reserved track, so DIR sector starts at 32
LD A,(drvName)
RST 08H ; Print drive letter
INC A
LD (drvName),A
LD A,$20
LD (secNo),A
processSectorA:
LD A,(secNo)
OUT (SD_LBA0),A
LD A,0
OUT (SD_LBA1),A
LD A,0
OUT (SD_LBA2),A
LD a,$E0
call writehst
LD A,(secNo)
INC A
LD (secNo),A
CP $40
JR NZ, processSectorA
;Drive 1 onwards (B: etc) don't have reserved tracks, so sector starts at 0
LD DE,$0040 ; HL increment
LD HL,$0040 ; H = LBA2, L=LBA1, initialise for drive 1 (B:)
LD B,numDrives
processDirs:
LD A,(drvName)
RST 08H ; Print drive letter
INC A
LD (drvName),A
LD A,0
LD (secNo),A
processSector:
LD A,(secNo)
OUT (SD_LBA0),A
LD A,L
OUT (SD_LBA1),A
LD A,H
OUT (SD_LBA2),A
call writehst
LD A,(secNo)
INC A
LD (secNo),A
CP $20
JR NZ, processSector
ADD HL,DE
DEC B
JR NZ,processDirs
CALL printInline
.DB CR,LF
.TEXT "Formatting complete"
.DB CR,LF,0
RET
;================================================================================================
; Write physical sector to host
;================================================================================================
writehst:
PUSH AF
PUSH BC
PUSH HL
wrWait1: IN A,(SD_STATUS)
CP 128
JR NZ,wrWait1
;CALL setLBAaddr
LD A,$01 ; 01 = Write block
OUT (SD_CONTROL),A
LD c,4
wr4secs:
LD HL,dirData
LD b,128
wrByte:
wrWait2: IN A,(SD_STATUS)
CP 160 ; Write buffer empty
JR NZ,wrWait2
;LD A,'.'
;RST 08H
; UPDATE S0urceror, inserted wait cycle between IN and OUT
; to resolve unknown write issue in sd_controller.vhd in combination
; with MISTer virtual SD interface sys/sd_card.sv
; which results in hangs or write errors.
push bc
ld b,50
_again:
djnz _again
pop bc
; END UPDATE
LD A,(HL)
OUT (SD_DATA),A
INC HL
dec b
JR NZ, wrByte
dec c
JR NZ,wr4secs
POP HL
POP BC
POP AF
;XOR a
;ld (erflag),a
RET
;================================================================================================
; Utilities
;================================================================================================
printInline:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nextILChar: LD A,(HL)
CP 0
JR Z,endOfPrint
RST 08H
INC HL
JR nextILChar
endOfPrint: INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
secNo .db 0
drvName .db 0
; Directory data for 1 x 128 byte sector
dirData:
.DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.DB $E5,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$20,$00,$00,$00,$00
.DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.END

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Z80 CPM and bootloader (basmon)/source/putsys.asm Normal file
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;==================================================================================
; Contents of this file are copyright Grant Searle
;
; You have permission to use this for NON COMMERCIAL USE ONLY
; If you wish to use it elsewhere, please include an acknowledgement to myself.
;
; http://searle.hostei.com/grant/index.html
;
; eMail: home.micros01@btinternet.com
;
; If the above don't work, please perform an Internet search to see if I have
; updated the web page hosting service.
;
;==================================================================================
loadAddr .EQU 0D000h
numSecs .EQU 24 ; Number of 512 sectors to be loaded
SD_DATA .EQU 088H
SD_CONTROL .EQU 089H
SD_STATUS .EQU 089H
SD_LBA0 .EQU 08AH
SD_LBA1 .EQU 08BH
SD_LBA2 .EQU 08CH
LF .EQU 0AH ;line feed
FF .EQU 0CH ;form feed
CR .EQU 0DH ;carriage RETurn
;================================================================================================
.ORG 5000H ; Loader origin.
CALL printInline
.TEXT "CP/M System Transfer by G. Searle 2012-13"
.DB CR,LF,0
LD B,numSecs
LD A,0
LD (lba0),A
ld (lba1),A
ld (lba2),A
ld (lba3),A
LD HL,loadAddr
LD (dmaAddr),HL
processSectors:
call writehst
LD DE,0200H
LD HL,(dmaAddr)
ADD HL,DE
LD (dmaAddr),HL
LD A,(lba0)
INC A
LD (lba0),A
djnz processSectors
CALL printInline
.DB CR,LF
.TEXT "System transfer complete"
.DB CR,LF,0
RET
; =========================================================================
; Disk routines as used in CBIOS
; =========================================================================
setLBAaddr:
LD A,(lba2)
OUT (SD_LBA2),A
LD A,(lba1)
OUT (SD_LBA1),A
LD A,(lba0)
OUT (SD_LBA0),A
ret
;================================================================================================
; Write physical sector to host
;================================================================================================
writehst:
PUSH AF
PUSH BC
PUSH HL
wrWait1: IN A,(SD_STATUS)
CP 128
JR NZ,wrWait1
CALL setLBAaddr
LD A,$01 ; 01 = Write block
OUT (SD_CONTROL),A
LD c,4
;LD HL,hstbuf
wr4secs:
LD b,128
wrByte:
wrWait2: IN A,(SD_STATUS)
CP 160 ; Write buffer empty
JR NZ,wrWait2
; UPDATE S0urceror, inserted wait cycle between IN and OUT
; to resolve unknown write issue in sd_controller.vhd in combination
; with MISTer virtual SD interface sys/sd_card.sv
; which results in hangs or write errors.
push bc
ld b,50
_again:
djnz _again
pop bc
; END UPDATE
LD A,(HL)
OUT (SD_DATA),A
INC HL
dec b
JR NZ, wrByte
dec c
JR NZ,wr4secs
POP HL
POP BC
POP AF
;XOR a
;ld (erflag),a
RET
;================================================================================================
; Utilities
;================================================================================================
printInline:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nextILChar: LD A,(HL)
CP 0
JR Z,endOfPrint
RST 08H
INC HL
JR nextILChar
endOfPrint: INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
lba0 .DB 00h
lba1 .DB 00h
lba2 .DB 00h
lba3 .DB 00h
dmaAddr .dw 0
.END

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Z80 CPM and bootloader (basmon)/transientAppsPackage/CPM211FilesPkg.txt Normal file
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Z80 CPM and bootloader (basmon)/windowsApp/COMDLG32.OCX Normal file
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Z80 CPM and bootloader (basmon)/windowsApp/FilePackage.exe Normal file
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build_id.v Normal file
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`define BUILD_DATE "201227"

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c5_pin_model_dump.txt Normal file
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io_4iomodule_c5_index: 55gpio_index: 2
io_4iomodule_c5_index: 54gpio_index: 465
io_4iomodule_c5_index: 33gpio_index: 6
io_4iomodule_c5_index: 51gpio_index: 461
io_4iomodule_c5_index: 27gpio_index: 10
io_4iomodule_c5_index: 57gpio_index: 457
io_4iomodule_c5_index: 34gpio_index: 14
io_4iomodule_c5_index: 28gpio_index: 453
io_4iomodule_c5_index: 26gpio_index: 19
io_4iomodule_c5_index: 47gpio_index: 449
io_4iomodule_c5_index: 29gpio_index: 22
io_4iomodule_c5_index: 3gpio_index: 445
io_4iomodule_c5_index: 16gpio_index: 27
io_4iomodule_c5_index: 6gpio_index: 441
io_4iomodule_c5_index: 50gpio_index: 30
io_4iomodule_c5_index: 35gpio_index: 437
io_4iomodule_c5_index: 7gpio_index: 35
io_4iomodule_c5_index: 53gpio_index: 433
io_4iomodule_c5_index: 12gpio_index: 38
io_4iomodule_c5_index: 1gpio_index: 429
io_4iomodule_c5_index: 22gpio_index: 43
io_4iomodule_c5_index: 8gpio_index: 425
io_4iomodule_c5_index: 20gpio_index: 46
io_4iomodule_c5_index: 30gpio_index: 421
io_4iomodule_c5_index: 2gpio_index: 51
io_4iomodule_c5_index: 31gpio_index: 417
io_4iomodule_c5_index: 39gpio_index: 54
io_4iomodule_c5_index: 18gpio_index: 413
io_4iomodule_c5_index: 10gpio_index: 59
io_4iomodule_c5_index: 42gpio_index: 409
io_4iomodule_c5_index: 5gpio_index: 62
io_4iomodule_c5_index: 24gpio_index: 405
io_4iomodule_c5_index: 37gpio_index: 67
io_4iomodule_c5_index: 13gpio_index: 401
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_c5_index: 44gpio_index: 397
io_4iomodule_c5_index: 38gpio_index: 75
io_4iomodule_c5_index: 52gpio_index: 393
io_4iomodule_c5_index: 32gpio_index: 78
io_4iomodule_c5_index: 56gpio_index: 389
io_4iomodule_a_index: 13gpio_index: 385
io_4iomodule_c5_index: 4gpio_index: 83
io_4iomodule_c5_index: 23gpio_index: 86
io_4iomodule_a_index: 15gpio_index: 381
io_4iomodule_a_index: 8gpio_index: 377
io_4iomodule_c5_index: 46gpio_index: 91
io_4iomodule_a_index: 5gpio_index: 373
io_4iomodule_a_index: 11gpio_index: 369
io_4iomodule_c5_index: 41gpio_index: 94
io_4iomodule_a_index: 3gpio_index: 365
io_4iomodule_c5_index: 25gpio_index: 99
io_4iomodule_a_index: 7gpio_index: 361
io_4iomodule_c5_index: 9gpio_index: 102
io_4iomodule_a_index: 0gpio_index: 357
io_4iomodule_c5_index: 14gpio_index: 107
io_4iomodule_a_index: 12gpio_index: 353
io_4iomodule_c5_index: 45gpio_index: 110
io_4iomodule_c5_index: 17gpio_index: 115
io_4iomodule_a_index: 4gpio_index: 349
io_4iomodule_c5_index: 36gpio_index: 118
io_4iomodule_a_index: 10gpio_index: 345
io_4iomodule_a_index: 16gpio_index: 341
io_4iomodule_c5_index: 15gpio_index: 123
io_4iomodule_a_index: 14gpio_index: 337
io_4iomodule_c5_index: 43gpio_index: 126
io_4iomodule_c5_index: 19gpio_index: 131
io_4iomodule_a_index: 1gpio_index: 333
io_4iomodule_c5_index: 59gpio_index: 134
io_4iomodule_a_index: 2gpio_index: 329
io_4iomodule_a_index: 9gpio_index: 325
io_4iomodule_c5_index: 48gpio_index: 139
io_4iomodule_a_index: 6gpio_index: 321
io_4iomodule_a_index: 17gpio_index: 317
io_4iomodule_c5_index: 40gpio_index: 142
io_4iomodule_c5_index: 11gpio_index: 147
io_4iomodule_c5_index: 58gpio_index: 150
io_4iomodule_c5_index: 21gpio_index: 155
io_4iomodule_c5_index: 49gpio_index: 158
io_4iomodule_h_c5_index: 0gpio_index: 161
io_4iomodule_h_c5_index: 6gpio_index: 165
io_4iomodule_h_c5_index: 10gpio_index: 169
io_4iomodule_h_c5_index: 3gpio_index: 173
io_4iomodule_h_c5_index: 8gpio_index: 176
io_4iomodule_h_c5_index: 11gpio_index: 180
io_4iomodule_h_c5_index: 7gpio_index: 184
io_4iomodule_h_c5_index: 5gpio_index: 188
io_4iomodule_h_c5_index: 1gpio_index: 192
io_4iomodule_h_c5_index: 2gpio_index: 196
io_4iomodule_h_c5_index: 9gpio_index: 200
io_4iomodule_h_c5_index: 4gpio_index: 204
io_4iomodule_h_index: 15gpio_index: 208
io_4iomodule_h_index: 1gpio_index: 212
io_4iomodule_h_index: 3gpio_index: 216
io_4iomodule_h_index: 2gpio_index: 220
io_4iomodule_h_index: 11gpio_index: 224
io_4iomodule_vref_h_index: 1gpio_index: 228
io_4iomodule_h_index: 20gpio_index: 231
io_4iomodule_h_index: 8gpio_index: 235
io_4iomodule_h_index: 6gpio_index: 239
io_4iomodule_h_index: 10gpio_index: 243
io_4iomodule_h_index: 23gpio_index: 247
io_4iomodule_h_index: 7gpio_index: 251
io_4iomodule_h_index: 22gpio_index: 255
io_4iomodule_h_index: 5gpio_index: 259
io_4iomodule_h_index: 24gpio_index: 263
io_4iomodule_h_index: 0gpio_index: 267
io_4iomodule_h_index: 13gpio_index: 271
io_4iomodule_h_index: 21gpio_index: 275
io_4iomodule_h_index: 16gpio_index: 279
io_4iomodule_vref_h_index: 0gpio_index: 283
io_4iomodule_h_index: 12gpio_index: 286
io_4iomodule_h_index: 4gpio_index: 290
io_4iomodule_h_index: 19gpio_index: 294
io_4iomodule_h_index: 18gpio_index: 298
io_4iomodule_h_index: 17gpio_index: 302
io_4iomodule_h_index: 25gpio_index: 306
io_4iomodule_h_index: 14gpio_index: 310
io_4iomodule_h_index: 9gpio_index: 314

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<?xml version="1.0"?>
<instance entity-name="altera_pll" version="17.0" >
<generic name="debug_print_output" value="false" />
<generic name="debug_use_rbc_taf_method" value="false" />
<generic name="device_family" value="Cyclone V" />
<generic name="device" value="5CEBA2F17A7" />
<generic name="gui_device_speed_grade" value="2" />
<generic name="gui_pll_mode" value="Integer-N PLL" />
<generic name="gui_reference_clock_frequency" value="50.0" />
<generic name="gui_channel_spacing" value="0.0" />
<generic name="gui_operation_mode" value="direct" />
<generic name="gui_feedback_clock" value="Global Clock" />
<generic name="gui_fractional_cout" value="32" />
<generic name="gui_dsm_out_sel" value="1st_order" />
<generic name="gui_use_locked" value="true" />
<generic name="gui_en_adv_params" value="false" />
<generic name="gui_number_of_clocks" value="2" />
<generic name="gui_multiply_factor" value="1" />
<generic name="gui_frac_multiply_factor" value="1" />
<generic name="gui_divide_factor_n" value="1" />
<generic name="gui_cascade_counter0" value="false" />
<generic name="gui_output_clock_frequency0" value="112.0" />
<generic name="gui_divide_factor_c0" value="1" />
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
<generic name="gui_ps_units0" value="ps" />
<generic name="gui_phase_shift0" value="0" />
<generic name="gui_phase_shift_deg0" value="0.0" />
<generic name="gui_actual_phase_shift0" value="0" />
<generic name="gui_duty_cycle0" value="50" />
<generic name="gui_cascade_counter1" value="false" />
<generic name="gui_output_clock_frequency1" value="112.0" />
<generic name="gui_divide_factor_c1" value="1" />
<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
<generic name="gui_ps_units1" value="ps" />
<generic name="gui_phase_shift1" value="-4350" />
<generic name="gui_phase_shift_deg1" value="180.0" />
<generic name="gui_actual_phase_shift1" value="0" />
<generic name="gui_duty_cycle1" value="50" />
<generic name="gui_cascade_counter2" value="false" />
<generic name="gui_output_clock_frequency2" value="14.0" />
<generic name="gui_divide_factor_c2" value="1" />
<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
<generic name="gui_ps_units2" value="ps" />
<generic name="gui_phase_shift2" value="0" />
<generic name="gui_phase_shift_deg2" value="0.0" />
<generic name="gui_actual_phase_shift2" value="0" />
<generic name="gui_duty_cycle2" value="50" />
<generic name="gui_cascade_counter3" value="false" />
<generic name="gui_output_clock_frequency3" value="56.0" />
<generic name="gui_divide_factor_c3" value="1" />
<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
<generic name="gui_ps_units3" value="ps" />
<generic name="gui_phase_shift3" value="0" />
<generic name="gui_phase_shift_deg3" value="0.0" />
<generic name="gui_actual_phase_shift3" value="0" />
<generic name="gui_duty_cycle3" value="50" />
<generic name="gui_cascade_counter4" value="false" />
<generic name="gui_output_clock_frequency4" value="112.0" />
<generic name="gui_divide_factor_c4" value="1" />
<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
<generic name="gui_ps_units4" value="ps" />
<generic name="gui_phase_shift4" value="0" />
<generic name="gui_phase_shift_deg4" value="0.0" />
<generic name="gui_actual_phase_shift4" value="0" />
<generic name="gui_duty_cycle4" value="50" />
<generic name="gui_cascade_counter5" value="false" />
<generic name="gui_output_clock_frequency5" value="100.0" />
<generic name="gui_divide_factor_c5" value="1" />
<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
<generic name="gui_ps_units5" value="ps" />
<generic name="gui_phase_shift5" value="0" />
<generic name="gui_phase_shift_deg5" value="0.0" />
<generic name="gui_actual_phase_shift5" value="0" />
<generic name="gui_duty_cycle5" value="50" />
<generic name="gui_cascade_counter6" value="false" />
<generic name="gui_output_clock_frequency6" value="100.0" />
<generic name="gui_divide_factor_c6" value="1" />
<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
<generic name="gui_ps_units6" value="ps" />
<generic name="gui_phase_shift6" value="0" />
<generic name="gui_phase_shift_deg6" value="0.0" />
<generic name="gui_actual_phase_shift6" value="0" />
<generic name="gui_duty_cycle6" value="50" />
<generic name="gui_cascade_counter7" value="false" />
<generic name="gui_output_clock_frequency7" value="100.0" />
<generic name="gui_divide_factor_c7" value="1" />
<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
<generic name="gui_ps_units7" value="ps" />
<generic name="gui_phase_shift7" value="0" />
<generic name="gui_phase_shift_deg7" value="0.0" />
<generic name="gui_actual_phase_shift7" value="0" />
<generic name="gui_duty_cycle7" value="50" />
<generic name="gui_cascade_counter8" value="false" />
<generic name="gui_output_clock_frequency8" value="100.0" />
<generic name="gui_divide_factor_c8" value="1" />
<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
<generic name="gui_ps_units8" value="ps" />
<generic name="gui_phase_shift8" value="0" />
<generic name="gui_phase_shift_deg8" value="0.0" />
<generic name="gui_actual_phase_shift8" value="0" />
<generic name="gui_duty_cycle8" value="50" />
<generic name="gui_cascade_counter9" value="false" />
<generic name="gui_output_clock_frequency9" value="100.0" />
<generic name="gui_divide_factor_c9" value="1" />
<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
<generic name="gui_ps_units9" value="ps" />
<generic name="gui_phase_shift9" value="0" />
<generic name="gui_phase_shift_deg9" value="0.0" />
<generic name="gui_actual_phase_shift9" value="0" />
<generic name="gui_duty_cycle9" value="50" />
<generic name="gui_cascade_counter10" value="false" />
<generic name="gui_output_clock_frequency10" value="100.0" />
<generic name="gui_divide_factor_c10" value="1" />
<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
<generic name="gui_ps_units10" value="ps" />
<generic name="gui_phase_shift10" value="0" />
<generic name="gui_phase_shift_deg10" value="0.0" />
<generic name="gui_actual_phase_shift10" value="0" />
<generic name="gui_duty_cycle10" value="50" />
<generic name="gui_cascade_counter11" value="false" />
<generic name="gui_output_clock_frequency11" value="100.0" />
<generic name="gui_divide_factor_c11" value="1" />
<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
<generic name="gui_ps_units11" value="ps" />
<generic name="gui_phase_shift11" value="0" />
<generic name="gui_phase_shift_deg11" value="0.0" />
<generic name="gui_actual_phase_shift11" value="0" />
<generic name="gui_duty_cycle11" value="50" />
<generic name="gui_cascade_counter12" value="false" />
<generic name="gui_output_clock_frequency12" value="100.0" />
<generic name="gui_divide_factor_c12" value="1" />
<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
<generic name="gui_ps_units12" value="ps" />
<generic name="gui_phase_shift12" value="0" />
<generic name="gui_phase_shift_deg12" value="0.0" />
<generic name="gui_actual_phase_shift12" value="0" />
<generic name="gui_duty_cycle12" value="50" />
<generic name="gui_cascade_counter13" value="false" />
<generic name="gui_output_clock_frequency13" value="100.0" />
<generic name="gui_divide_factor_c13" value="1" />
<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
<generic name="gui_ps_units13" value="ps" />
<generic name="gui_phase_shift13" value="0" />
<generic name="gui_phase_shift_deg13" value="0.0" />
<generic name="gui_actual_phase_shift13" value="0" />
<generic name="gui_duty_cycle13" value="50" />
<generic name="gui_cascade_counter14" value="false" />
<generic name="gui_output_clock_frequency14" value="100.0" />
<generic name="gui_divide_factor_c14" value="1" />
<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
<generic name="gui_ps_units14" value="ps" />
<generic name="gui_phase_shift14" value="0" />
<generic name="gui_phase_shift_deg14" value="0.0" />
<generic name="gui_actual_phase_shift14" value="0" />
<generic name="gui_duty_cycle14" value="50" />
<generic name="gui_cascade_counter15" value="false" />
<generic name="gui_output_clock_frequency15" value="100.0" />
<generic name="gui_divide_factor_c15" value="1" />
<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
<generic name="gui_ps_units15" value="ps" />
<generic name="gui_phase_shift15" value="0" />
<generic name="gui_phase_shift_deg15" value="0.0" />
<generic name="gui_actual_phase_shift15" value="0" />
<generic name="gui_duty_cycle15" value="50" />
<generic name="gui_cascade_counter16" value="false" />
<generic name="gui_output_clock_frequency16" value="100.0" />
<generic name="gui_divide_factor_c16" value="1" />
<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
<generic name="gui_ps_units16" value="ps" />
<generic name="gui_phase_shift16" value="0" />
<generic name="gui_phase_shift_deg16" value="0.0" />
<generic name="gui_actual_phase_shift16" value="0" />
<generic name="gui_duty_cycle16" value="50" />
<generic name="gui_cascade_counter17" value="false" />
<generic name="gui_output_clock_frequency17" value="100.0" />
<generic name="gui_divide_factor_c17" value="1" />
<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
<generic name="gui_ps_units17" value="ps" />
<generic name="gui_phase_shift17" value="0" />
<generic name="gui_phase_shift_deg17" value="0.0" />
<generic name="gui_actual_phase_shift17" value="0" />
<generic name="gui_duty_cycle17" value="50" />
<generic name="gui_pll_auto_reset" value="On" />
<generic name="gui_pll_bandwidth_preset" value="Auto" />
<generic name="gui_en_reconf" value="false" />
<generic name="gui_en_dps_ports" value="false" />
<generic name="gui_en_phout_ports" value="false" />
<generic name="gui_phout_division" value="1" />
<generic name="gui_mif_generate" value="false" />
<generic name="gui_enable_mif_dps" value="false" />
<generic name="gui_dps_cntr" value="C0" />
<generic name="gui_dps_num" value="1" />
<generic name="gui_dps_dir" value="Positive" />
<generic name="gui_refclk_switch" value="false" />
<generic name="gui_refclk1_frequency" value="100.0" />
<generic name="gui_switchover_mode" value="Automatic Switchover" />
<generic name="gui_switchover_delay" value="0" />
<generic name="gui_active_clk" value="false" />
<generic name="gui_clk_bad" value="false" />
<generic name="gui_enable_cascade_out" value="false" />
<generic name="gui_cascade_outclk_index" value="0" />
<generic name="gui_enable_cascade_in" value="false" />
<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
</instance>

BIN
releases/MultiComp_20180624.rbf
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releases/MultiComp_20180629.rbf
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82
rtl/pll.bsf Normal file
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@@ -0,0 +1,82 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 144)
(text "pll" (rect 74 -1 81 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 48 112)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 112 72)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
(line (pt 160 112)(pt 112 112)(line_width 1))
)
(drawing
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
(line (pt 48 32)(pt 112 32)(line_width 1))
(line (pt 112 32)(pt 112 128)(line_width 1))
(line (pt 48 128)(pt 112 128)(line_width 1))
(line (pt 48 32)(pt 48 128)(line_width 1))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
(line (pt 50 92)(pt 50 116)(line_width 1))
(line (pt 111 52)(pt 111 76)(line_width 1))
(line (pt 110 52)(pt 110 76)(line_width 1))
(line (pt 111 92)(pt 111 116)(line_width 1))
(line (pt 110 92)(pt 110 116)(line_width 1))
(line (pt 0 0)(pt 160 0)(line_width 1))
(line (pt 160 0)(pt 160 144)(line_width 1))
(line (pt 0 144)(pt 160 144)(line_width 1))
(line (pt 0 0)(pt 0 144)(line_width 1))
)
)

9
rtl/pll.cmp Normal file
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@@ -0,0 +1,9 @@
component pll is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component pll;

13
rtl/pll.ppf Normal file
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@@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="pll"
megafunction_name="ALTERA_PLL"
intended_family="Cyclone V"
specifies="all_ports">
<global>
<pin name="refclk" direction="input" scope="external" />
<pin name="rst" direction="input" scope="external" />
<pin name="outclk_0" direction="output" scope="external" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

20
sys/pll.qip → rtl/pll.qip
View File

@@ -35,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTEyLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTEy::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -256,11 +256,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTEyLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTIgcHM=::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTYsNTYsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDUsNSw2LDEscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDEwMDAwLDExMjAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywzLDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwzMCwyMDAwLDMwMC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

6
rtl/pll.sip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll" -library "lib_pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_pll" -name SPD_FILE [file join $::quartus(sip_path) "pll.spd"]
set_global_assignment -library "lib_pll" -name MISC_FILE [file join $::quartus(sip_path) "pll_sim/pll.vo"]

6
rtl/pll.spd Normal file
View File

@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="pll_sim/pll.vo" type="VERILOG" />
<topLevel name="pll" />
<deviceFamily name="cyclonev" />
</simPackage>

10
sys/pll.v → rtl/pll.v
View File

@@ -2,14 +2,13 @@
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 598
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
@@ -17,7 +16,6 @@ module pll (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
@@ -28,7 +26,7 @@ endmodule
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Copyright (C) 1991-2020 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
@@ -63,12 +61,12 @@ endmodule
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="112.0" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="50.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />

0
sys/pll/pll_0002.qip → rtl/pll/pll_0002.qip
View File

13
sys/pll/pll_0002.v → rtl/pll/pll_0002.v
View File

@@ -10,9 +10,6 @@ module pll_0002(
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
@@ -21,12 +18,12 @@ module pll_0002(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("112.000000 MHz"),
.number_of_clocks(1),
.output_clock_frequency0("50.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("112.000000 MHz"),
.phase_shift1("-4352 ps"),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
@@ -80,7 +77,7 @@ module pll_0002(
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),

1
rtl/pll_sim.f Normal file
View File

@@ -0,0 +1 @@
pll_sim/pll.vo

157
sys/alsa.sv Normal file
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@@ -0,0 +1,157 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019,2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module alsa
#(
parameter CLK_RATE = 24576000
)
(
input reset,
input clk,
output reg [31:3] ram_address,
input [63:0] ram_data,
output reg ram_req = 0,
input ram_ready,
input spi_ss,
input spi_sck,
input spi_mosi,
output spi_miso,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg [60:0] buf_info;
reg [6:0] spicnt = 0;
always @(posedge spi_sck, posedge spi_ss) begin
reg [95:0] spi_data;
if(spi_ss) spicnt <= 0;
else begin
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
spicnt <= spicnt + 1'd1;
end
end
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
reg [31:0] spi_out = 0;
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
reg [31:3] buf_addr;
reg [18:3] buf_len;
reg [18:3] buf_wptr = 0;
always @(posedge clk) begin
reg [60:0] data1,data2;
data1 <= buf_info;
data2 <= data1;
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
end
reg [2:0] hurryup = 0;
reg [18:3] buf_rptr = 0;
always @(posedge clk) begin
reg [18:3] len = 0;
reg [1:0] ready = 0;
reg [63:0] readdata;
reg got_first = 0;
reg [7:0] ce_cnt = 0;
reg [1:0] state = 0;
if(reset) begin
ready <= 0;
ce_cnt <= 0;
state <= 0;
got_first <= 0;
len <= 0;
end
else begin
//ramp up
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
//ramp down
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
if(!len[18:10]) hurryup <= 0;
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
case(state)
0: if(!ce_sample) begin
if(ready) begin
if(ce_cnt) begin
{readdata[31:0],pcm_r,pcm_l} <= readdata;
ready <= ready - 1'd1;
ce_cnt <= ce_cnt - 1'd1;
end
end
else if(buf_rptr != buf_wptr) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else begin
ram_address <= buf_addr + buf_rptr;
ram_req <= ~ram_req;
buf_rptr <= buf_rptr + 1'd1;
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
state <= 1;
end
end
else begin
len <= 0;
ce_cnt <= 0;
hurryup <= 0;
end
end
1: if(ram_ready) begin
ready <= 2;
readdata <= ram_data;
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
state <= 0;
end
endcase
end
end
reg ce_sample;
always @(posedge clk) begin
reg [31:0] acc = 0;
ce_sample <= 0;
acc <= acc + 48000 + {hurryup,6'd0};
if(acc >= CLK_RATE) begin
acc <= acc - CLK_RATE;
ce_sample <= 1;
end
end
endmodule

296
sys/arcade_video.v Normal file
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@@ -0,0 +1,296 @@
//============================================================================
//
// Copyright (C) 2017-2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
// 24 : 8R 8G 8B
module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output CLK_VIDEO,
output CE_PIXEL,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output [1:0] VGA_SL,
input [2:0] fx,
input forced_scandoubler,
inout [21:0] gamma_bus
);
assign CLK_VIDEO = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(CLK_VIDEO, HSync, hs_fix);
sync_fix sync_h(CLK_VIDEO, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
reg CE,HS,VS,HBL,VBL;
always @(posedge CLK_VIDEO) begin
reg old_ce;
old_ce <= ce_pix;
CE <= 0;
if(~old_ce & ce_pix) begin
CE <= 1;
HS <= hs_fix;
if(~HS & hs_fix) VS <= vs_fix;
RGB_fix <= RGB_in;
HBL <= HBlank;
if(HBL & ~HBlank) VBL <= VBlank;
end
end
wire [7:0] R,G,B;
generate
if(DW == 6) begin
assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else if(DW == 12) begin
assign R = {RGB_fix[11:8],RGB_fix[11:8]};
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else begin // 24
assign R = RGB_fix[23:16];
assign G = RGB_fix[15:8];
assign B = RGB_fix[7:0];
end
endgenerate
assign VGA_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
(
.clk_vid(CLK_VIDEO),
.ce_pix(CE),
.ce_pix_out(CE_PIXEL),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R((DW!=24) ? R[7:4] : R),
.G((DW!=24) ? G[7:4] : G),
.B((DW!=24) ? B[7:4] : B),
.HSync (HS),
.VSync (VS),
.HBlank(HBL),
.VBlank(VBL),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
);
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module screen_rotate
(
input CLK_VIDEO,
input CE_PIXEL,
input [7:0] VGA_R,
input [7:0] VGA_G,
input [7:0] VGA_B,
input VGA_HS,
input VGA_VS,
input VGA_DE,
input rotate_ccw,
input no_rotate,
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
output DDRAM_RD
);
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
assign DDRAM_CLK = CLK_VIDEO;
assign DDRAM_BURSTCNT = 1;
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F;
assign DDRAM_DIN = {ram_data,ram_data};
assign DDRAM_WE = ram_wr;
assign DDRAM_RD = 0;
assign FB_EN = ~no_rotate;
assign FB_FORMAT = 5'b00110;
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
assign FB_WIDTH = vsz;
assign FB_HEIGHT = hsz;
assign FB_STRIDE = stride;
function [1:0] buf_next;
input [1:0] a,b;
begin
buf_next = 1;
if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2;
if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0;
end
endfunction
reg [1:0] i_fb,o_fb;
always @(posedge CLK_VIDEO) begin
reg old_vbl,old_vs;
old_vbl <= FB_VBL;
old_vs <= VGA_VS;
if(FB_LL) begin
if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]};
if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]};
end
else begin
if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb);
if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb);
end
end
reg [11:0] hsz = 320, vsz = 240;
reg [11:0] bwidth;
reg [22:0] bufsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] hcnt = 0, vcnt = 0;
reg old_vs, old_de;
if(CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
hcnt <= hcnt + 1'd1;
if(~old_de & VGA_DE) begin
hcnt <= 1;
vcnt <= vcnt + 1'd1;
end
if(old_de & ~VGA_DE) hsz <= hcnt;
if(~old_vs & VGA_VS) begin
vsz <= vcnt;
bwidth <= vcnt + 2'd3;
vcnt <= 0;
end
if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
end
end
wire [13:0] stride = {bwidth[11:2], 4'd0};
reg [22:0] ram_addr, next_addr;
reg [31:0] ram_data;
reg ram_wr;
always @(posedge CLK_VIDEO) begin
reg [13:0] hcnt = 0;
reg old_vs, old_de;
ram_wr <= 0;
if(CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
if(~old_vs & VGA_VS) begin
next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
end
if(VGA_DE) begin
ram_wr <= 1;
ram_data <= {VGA_B,VGA_G,VGA_R};
ram_addr <= next_addr;
next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
end
if(old_de & ~VGA_DE) begin
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
end
end
end
endmodule

2560
sys/ascal.vhd Normal file
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File diff suppressed because it is too large Load Diff

296
sys/audio_out.v Normal file
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@@ -0,0 +1,296 @@
module audio_out
#(
parameter CLK_RATE = 24576000
)
(
input reset,
input clk,
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [31:0] flt_rate,
input [39:0] cx,
input [7:0] cx0,
input [7:0] cx1,
input [7:0] cx2,
input [23:0] cy0,
input [23:0] cy1,
input [23:0] cy2,
input [4:0] att,
input [1:0] mix,
input is_signed,
input [15:0] core_l,
input [15:0] core_r,
input [15:0] alsa_l,
input [15:0] alsa_r,
// I2S
output i2s_bclk,
output i2s_lrclk,
output i2s_data,
// SPDIF
output spdif,
// Sigma-Delta DAC
output dac_l,
output dac_r
);
localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce = 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce = 1;
end
end
reg i2s_ce;
always @(posedge clk) begin
reg div;
i2s_ce <= 0;
if(mclk_ce) begin
div <= ~div;
i2s_ce <= div;
end
end
i2s i2s
(
.reset(reset),
.clk(clk),
.ce(i2s_ce),
.sclk(i2s_bclk),
.lrclk(i2s_lrclk),
.sdata(i2s_data),
.left_chan(al),
.right_chan(ar)
);
spdif toslink
(
.rst_i(reset),
.clk_i(clk),
.bit_out_en_i(mclk_ce),
.sample_i({ar,al}),
.spdif_o(spdif)
);
sigma_delta_dac #(15) sd_l
(
.CLK(clk),
.RESET(reset),
.DACin({~al[15], al[14:0]}),
.DACout(dac_l)
);
sigma_delta_dac #(15) sd_r
(
.CLK(clk),
.RESET(reset),
.DACin({~ar[15], ar[14:0]}),
.DACout(dac_r)
);
reg sample_ce;
always @(posedge clk) begin
reg [8:0] div = 0;
reg [1:0] add = 0;
div <= div + add;
if(!div) begin
div <= 2'd1 << sample_rate;
add <= 2'd1 << sample_rate;
end
sample_ce <= !div;
end
reg flt_ce;
always @(posedge clk) begin
reg [31:0] cnt = 0;
flt_ce = 0;
cnt = cnt + {flt_rate[30:0],1'b0};
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
flt_ce = 1;
end
end
reg [15:0] cl,cr;
always @(posedge clk) begin
reg [15:0] cl1,cl2;
reg [15:0] cr1,cr2;
cl1 <= core_l; cl2 <= cl1;
if(cl2 == cl1) cl <= cl2;
cr1 <= core_r; cr2 <= cr1;
if(cr2 == cr1) cr <= cr2;
end
reg a_en1 = 0, a_en2 = 0;
always @(posedge clk, posedge reset) begin
reg [1:0] dly1 = 0;
reg [14:0] dly2 = 0;
if(reset) begin
dly1 <= 0;
dly2 <= 0;
a_en1 <= 0;
a_en2 <= 0;
end
else begin
if(flt_ce) begin
if(~&dly1) dly1 <= dly1 + 1'd1;
else a_en1 <= 1;
end
if(sample_ce) begin
if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1;
else a_en2 <= 1;
end
end
end
wire [15:0] acl, acr;
IIR_filter #(.use_params(0)) IIR_filter
(
.clk(clk),
.reset(reset),
.ce(flt_ce & a_en1),
.sample_ce(sample_ce),
.cx(cx),
.cx0(cx0),
.cx1(cx1),
.cx2(cx2),
.cy0(cy0),
.cy1(cy1),
.cy2(cy2),
.input_l({~is_signed ^ cl[15], cl[14:0]}),
.input_r({~is_signed ^ cr[15], cr[14:0]}),
.output_l(acl),
.output_r(acr)
);
wire [15:0] adl;
DC_blocker dcb_l
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acl),
.dout(adl)
);
wire [15:0] adr;
DC_blocker dcb_r
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acr),
.dout(adr)
);
wire [15:0] al, audio_l_pre;
aud_mix_top audmix_l
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adl),
.pre_in(audio_r_pre),
.linux_audio(alsa_l),
.pre_out(audio_l_pre),
.out(al)
);
wire [15:0] ar, audio_r_pre;
aud_mix_top audmix_r
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adr),
.pre_in(audio_l_pre),
.linux_audio(alsa_r),
.pre_out(audio_r_pre),
.out(ar)
);
endmodule
module aud_mix_top
(
input clk,
input ce,
input [4:0] att,
input [1:0] mix,
input [15:0] core_audio,
input [15:0] linux_audio,
input [15:0] pre_in,
output reg [15:0] pre_out = 0,
output reg [15:0] out = 0
);
reg signed [16:0] a1, a2, a3, a4;
always @(posedge clk) if (ce) begin
a1 <= {core_audio[15],core_audio};
a2 <= a1 + {linux_audio[15],linux_audio};
pre_out <= a2[16:1];
case(mix)
0: a3 <= a2;
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
endcase
if(att[4]) a4 <= 0;
else a4 <= a3 >>> att[3:0];
//clamping
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
end
endmodule

28
sys/build_id.tcl
View File

@@ -1,25 +1,29 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set outputFile [open $outputFileName "w"]
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file

108
sys/ddr_svc.sv Normal file
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@@ -0,0 +1,108 @@
//
// Copyright (c) 2020 Alexey Melnikov
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// 16-bit version
module ddr_svc
(
input clk,
input ram_waitrequest,
output [7:0] ram_burstcnt,
output [28:0] ram_addr,
input [63:0] ram_readdata,
input ram_read_ready,
output reg ram_read,
output [63:0] ram_writedata,
output [7:0] ram_byteenable,
output reg ram_write,
output [7:0] ram_bcnt,
input [31:3] ch0_addr,
input [7:0] ch0_burst,
output [63:0] ch0_data,
input ch0_req,
output ch0_ready,
input [31:3] ch1_addr,
input [7:0] ch1_burst,
output [63:0] ch1_data,
input ch1_req,
output ch1_ready
);
assign ram_burstcnt = ram_burst;
assign ram_byteenable = 8'hFF;
assign ram_addr = ram_address;
assign ram_writedata = 0;
assign ch0_data = ram_q[0];
assign ch1_data = ram_q[1];
assign ch0_ready = ready[0];
assign ch1_ready = ready[1];
reg [7:0] ram_burst;
reg [63:0] ram_q[2];
reg [31:3] ram_address;
reg [1:0] ack = 0;
reg [1:0] ready;
reg state = 0;
reg ch = 0;
always @(posedge clk) begin
ready <= 0;
if(!ram_waitrequest) begin
ram_read <= 0;
ram_write <= 0;
case(state)
0: if(ch0_req != ack[0]) begin
ack[0] <= ch0_req;
ram_address <= ch0_addr;
ram_burst <= ch0_burst;
ram_read <= 1;
ch <= 0;
ram_bcnt <= 8'hFF;
state <= 1;
end
else if(ch1_req != ack[1]) begin
ack[1] <= ch1_req;
ram_address <= ch1_addr;
ram_burst <= ch1_burst;
ram_read <= 1;
ch <= 1;
ram_bcnt <= 8'hFF;
state <= 1;
end
1: begin
if(ram_read_ready) begin
ram_bcnt <= ram_bcnt + 1'd1;
ram_q[ch] <= ram_readdata;
ready[ch] <= 1;
if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
end
end
endcase
end
end
endmodule

122
sys/gamma_corr.sv Normal file
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@@ -0,0 +1,122 @@
module gamma_corr
(
input clk_sys,
input clk_vid,
input ce_pix,
input gamma_en,
input gamma_wr,
input [9:0] gamma_wr_addr,
input [7:0] gamma_value,
input HSync,
input VSync,
input HBlank,
input VBlank,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
reg [9:0] gamma_index;
reg [7:0] gamma;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb;
reg [1:0] ctr = 0;
if(ce_pix) begin
{R_in,G_in,B_in} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
ctr <= 1;
gamma_index <= {2'b00,RGB_in[23:16]};
end
if (|ctr) ctr <= ctr + 1'd1;
case(ctr)
1: begin gamma_index <= {2'b01,G_in}; end
2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
3: begin G_gamma <= gamma; end
endcase
end
endmodule
module gamma_fast
(
input clk_vid,
input ce_pix,
inout [21:0] gamma_bus,
input HSync,
input VSync,
input HBlank,
input VBlank,
input DE,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg DE_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256];
assign gamma_bus[21] = 1;
wire clk_sys = gamma_bus[20];
wire gamma_en = gamma_bus[19];
wire gamma_wr = gamma_bus[18];
wire [9:0] gamma_wr_addr = gamma_bus[17:8];
wire [7:0] gamma_value = gamma_bus[7:0];
always @(posedge clk_sys) if (gamma_wr) begin
case(gamma_wr_addr[9:8])
0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value;
1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value;
2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value;
endcase
end
reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb,de;
if(ce_pix) begin
{gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
de <= DE;
RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]}
: {gamma_index_r,gamma_index_g,gamma_index_b};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
DE_out <= de;
end
end
endmodule

65
sys/hdmi_config.sv
View File

@@ -2,11 +2,15 @@
module hdmi_config
(
// Host Side
input iCLK,
input iRST_N,
input iCLK,
input iRST_N,
input dvi_mode,
input audio_96k,
input [1:0] limited,
input ypbpr,
output reg done,
// I2C Side
output I2C_SCL,
@@ -24,13 +28,17 @@ i2c #(50_000_000, 20_000) i2c_av
(
.CLK(iCLK),
.I2C_SCL(I2C_SCL), // I2C CLOCK
.I2C_SDA(I2C_SDA), // I2C DATA
.I2C_SCL(I2C_SCL), // I2C CLOCK
.I2C_SDA(I2C_SDA), // I2C DATA
.I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
.START(mI2C_GO), // START transfer
.END(mI2C_END), // END transfer
.ACK(mI2C_ACK) // ACK
.I2C_ADDR('h39), // 0x39 is the Slave Address of the ADV7513 chip!
.I2C_WLEN(1),
.I2C_WDATA1(init_data[LUT_INDEX][15:8]), // SUB_ADDR
.I2C_WDATA2(init_data[LUT_INDEX][7:0]), // DATA
.START(mI2C_GO), // START transfer
.READ(0),
.END(mI2C_END), // END transfer
.ACK(mI2C_ACK) // ACK
);
////////////////////// Config Control ////////////////////////////
@@ -41,6 +49,7 @@ always@(posedge iCLK or negedge iRST_N) begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
done <= 0;
end else begin
if(init_data[LUT_INDEX] != 16'hFFFF) begin
case(mSetup_ST)
@@ -58,13 +67,14 @@ always@(posedge iCLK or negedge iRST_N) begin
end
endcase
end
else done <= 1;
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
wire [15:0] init_data[58] =
wire [15:0] init_data[82] =
'{
16'h9803, // ADI required Write.
@@ -101,10 +111,32 @@ wire [15:0] init_data[58] =
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
{8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
// CSC Equation 3 [4:0] b00110.
{8'h18, ypbpr ? 8'h88 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
{8'h19, ypbpr ? 8'h2E : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
{8'h1A, ypbpr ? 8'h18 : 8'h00}, // CSC Channel A.
{8'h1B, ypbpr ? 8'h93 : 8'h00},
{8'h1C, ypbpr ? 8'h1F : 8'h00},
{8'h1D, ypbpr ? 8'h3F : 8'h00},
{8'h1E, ypbpr ? 8'h08 : 8'h01},
{8'h1F, 8'h00},
{8'h20, ypbpr ? 8'h03 : 8'h00}, // CSC Channel B.
{8'h21, ypbpr ? 8'h67 : 8'h00},
{8'h22, ypbpr ? 8'h0B : limited[0] ? 8'h0D : 8'h0E},
{8'h23, ypbpr ? 8'h71 : limited[0] ? 8'hBC : 8'hFE},
{8'h24, ypbpr ? 8'h01 : 8'h00},
{8'h25, ypbpr ? 8'h28 : 8'h00},
{8'h26, ypbpr ? 8'h00 : 8'h01},
{8'h27, 8'h00},
{8'h28, ypbpr ? 8'h1E : 8'h00}, // CSC Channel C.
{8'h29, ypbpr ? 8'h21 : 8'h00},
{8'h2A, ypbpr ? 8'h19 : 8'h00},
{8'h2B, ypbpr ? 8'hB2 : 8'h00},
{8'h2C, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
{8'h2D, ypbpr ? 8'h2D : limited[0] ? 8'hBC : 8'hFE},
{8'h2E, ypbpr ? 8'h08 : 8'h01},
{8'h2F, 8'h00},
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
@@ -122,6 +154,11 @@ wire [15:0] init_data[58] =
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
{8'h57, 1'b0, // [7] IT Content. 0 - No. 1 - Yes (type set in register h59).
3'b000, // [6:4] Color space (ignored for RGB)
(ypbpr | limited) ? 2'b01 : 2'b10, // [3:2] RGB Quantization range
2'b00}, // [1:0] Non-Uniform Scaled: 00 - None. 01 - Horiz. 10 - Vert. 11 - Both.
16'h7301,
{8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
@@ -142,9 +179,9 @@ wire [15:0] init_data[58] =
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
{8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [4]=0 Current frame is unencrypted
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!

395
sys/hdmi_lite.sv
View File

@@ -1,395 +0,0 @@
//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

1203
sys/hps_io.v
View File

File diff suppressed because it is too large Load Diff

421
sys/hq2x.sv
View File

@@ -1,91 +1,84 @@
//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
// Copyright (c) 2017,2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <= 1024 ? 9 : \
N <= 2048 ?10 : 11 )
// altera message_off 10030
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
input clk,
input ce_in,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input ce_out,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
(* romstyle = "MLAB" *) reg [5:0] hqTable[256];
initial begin
hqTable = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
end
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
wire [5:0] hqrule = hqTable[nextpatt];
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
reg [1:0] cyc;
wire curbuf = y[0];
reg curbuf;
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [23:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [23:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
wire [DWIDTH:0] Curr21tmp;
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
@@ -109,9 +102,11 @@ hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.rdaddr(offs),
.rdbuf0(prevbuf),
.rdbuf1(curbuf),
.q0(Curr20tmp),
.q1(Curr21tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
@@ -119,66 +114,82 @@ hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
reg [AWIDTH+1:0] read_x;
reg [AWIDTH+1:0] wrout_addr;
reg wrout_en;
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
wire [DWIDTH1*4-1:0] outpixel_x4;
reg [DWIDTH1*2-1:0] outpixel_x2;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
(
.clk(clk),
.clock(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
.q(outpixel_x4),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wraddress(wrout_addr),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
if(ce_out) begin
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
end
end
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
reg [3:0] wrdata_finished;
reg [AWIDTH+1:0] waddr;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
if(ce_in) begin
pattern <= new_pattern;
// blend_result has been delayed by 4 cycles
case(cyc)
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
endcase
wrdata_finished <= wrdata_finished << 1;
if(wrdata_finished[3]) begin
wrout_en <= 1;
wrout_addr <= waddr;
end
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
if (cyc == 1) begin
Prev2 <= Curr20;
Curr2 <= Curr21;
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
if(cyc==3) begin
offs <= offs + 1'd1;
waddr <= {offs, curbuf};
wrdata_finished[0] <= 1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
pattern <= new_pattern;
if(cyc==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
@@ -190,19 +201,20 @@ always @(posedge clk) begin
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
cyc <= cyc + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
cyc <= 0;
curbuf <= ~curbuf;
prevbuf <= curbuf;
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
curbuf <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
@@ -216,8 +228,8 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input rdbuf0, rdbuf1,
output[DWIDTH:0] q0,q1,
input [AWIDTH:0] wraddr,
input wrbuf,
@@ -225,51 +237,27 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output logic [DWIDTH:0] q
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output reg [DWIDTH:0] q
);
logic [DWIDTH:0] ram[0:NUMWORDS-1];
reg [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
@@ -284,15 +272,14 @@ module DiffCheck
(
input [23:0] rgb1,
input [23:0] rgb2,
output result
output result
);
wire [7:0] r = rgb1[7:1] - rgb2[7:1];
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
wire [8:0] t = $signed(r) + $signed(b);
wire [8:0] gx = {g[7], g};
wire [9:0] y = $signed(t) + $signed(gx);
wire [9:0] y = $signed(t) + $signed({g[7], g});
wire [8:0] u = $signed(r) - $signed(b);
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
@@ -300,48 +287,19 @@ module DiffCheck
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
wire u_inside = (u < 9'h10 || u >= 9'h1f0);
wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [10:0] Amul = mul8x3(A, Op[7:5]);
wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
wire [10:0] At = Amul;
wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [11:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[11:4];
endmodule
module Blend
(
input clk,
input clk_en,
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
@@ -351,66 +309,63 @@ module Blend
output [23:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4
localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4
localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
reg [23:0] a,b,d,e,h,f;
reg [3:0] bl_rule;
reg [1:0] df_rule;
always @(posedge clk) if (clk_en) begin
{bl_rule,df_rule} <= rule;
a <= A; b <= B; d <= D; e <= E; f <= F; h <= H;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [23:0] Input1 = E;
wire [23:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire is_diff;
DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff);
reg [23:0] i10,i20,i30;
reg [6:0] op0;
always @(posedge clk) if (clk_en) begin
i10 <= e;
case({!is_diff, bl_rule})
1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0};
2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0};
3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0};
4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b};
5,21: {op0, i20, i30} <= {BLEND2, a, b};
6,22: {op0, i20, i30} <= {BLEND2, a, d};
25,29: {op0, i20, i30} <= {BLEND5, d, b};
26: {op0, i20, i30} <= {BLEND6, d, b};
28: {op0, i20, i30} <= {BLEND4, d, b};
30: {op0, i20, i30} <= {BLEND3, b, d};
31: {op0, i20, i30} <= {BLEND3, d, b};
default: {op0, i20, i30} <= {BLEND1, e, 24'd0};
endcase
end
reg [23:0] i1,i2,i3;
reg [6:0] op;
always @(posedge clk) if (clk_en) begin
op <= op0; i1 <= i10; i2 <= i20; i3 <= i30;
end
function [34:0] mul24x3;
input [23:0] op1;
input [2:0] op2;
begin
mul24x3 = 0;
if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]};
if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0};
if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00};
end
endfunction
wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]});
always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]};
wire [23:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]);
InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]);
InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
endmodule

65
sys/i2c.v
View File

@@ -4,7 +4,12 @@ module i2c
input CLK,
input START,
input [23:0] I2C_DATA,
input READ,
input [6:0] I2C_ADDR,
input I2C_WLEN, // 0 - one byte, 1 - two bytes
input [7:0] I2C_WDATA1,
input [7:0] I2C_WDATA2,
output [7:0] I2C_RDATA,
output reg END = 1,
output reg ACK = 0,
@@ -18,51 +23,73 @@ module i2c
parameter CLK_Freq = 50_000_000; // 50 MHz
parameter I2C_Freq = 400_000; // 400 KHz
reg I2C_CLOCK;
always@(negedge CLK) begin
integer mI2C_CLK_DIV = 0;
if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
end else begin
mI2C_CLK_DIV <= 0;
I2C_CLOCK <= ~I2C_CLOCK;
localparam I2C_FreqX2 = I2C_Freq*2;
reg I2C_CLOCK;
reg [31:0] cnt;
wire [31:0] cnt_next = cnt + I2C_FreqX2;
always @(posedge CLK) begin
cnt <= cnt_next;
if(cnt_next >= CLK_Freq) begin
cnt <= cnt_next - CLK_Freq;
I2C_CLOCK <= ~I2C_CLOCK;
end
end
assign I2C_SCL = SCLK | I2C_CLOCK;
assign I2C_SDA = SDO ? 1'bz : 1'b0;
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
reg SCLK = 1, SDO = 1;
reg SCLK = 1;
reg [3:0] SDO = 4'b1111;
reg [0:7] rdata;
assign I2C_RDATA = rdata;
always @(posedge CLK) begin
reg old_clk;
reg old_st;
reg rd,len;
reg [5:0] SD_COUNTER = 'b111111;
reg [0:31] SD;
old_clk <= I2C_CLOCK;
old_st <= START;
// delay to make sure SDA changed while SCL is stabilized at low
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
SDO[3:1] <= SDO[2:0];
if(~old_st && START) begin
SCLK <= 1;
SDO <= 1;
SDO <= 4'b1111;
ACK <= 0;
END <= 0;
SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
rd <= READ;
len <= I2C_WLEN;
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
SD_COUNTER <= 0;
end else begin
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
SD_COUNTER <= SD_COUNTER + 6'd1;
case(SD_COUNTER)
01: SCLK <= 0;
10,19,28: ACK <= ACK | I2C_SDA;
29: SCLK <= 1;
32: END <= 1;
01: SCLK <= 0;
10: ACK <= ACK | I2C_SDA;
19: if(~rd) begin
ACK <= ACK | I2C_SDA;
if(~len) SD_COUNTER <= 29;
end
20: if(rd) SCLK <= 1;
23: if(rd) END <= 1;
28: if(~rd) ACK <= ACK | I2C_SDA;
29: if(~rd) SCLK <= 1;
32: if(~rd) END <= 1;
endcase
end
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
end
end
end

128
sys/i2s.v
View File

@@ -1,14 +1,12 @@
module i2s
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_DW = 16,
parameter AUDIO_RATE = 96000
parameter AUDIO_DW = 16
)
(
input reset,
input clk_sys,
input half_rate,
input clk,
input ce,
output reg sclk,
output reg lrclk,
@@ -18,119 +16,39 @@ module i2s
input [AUDIO_DW-1:0] right_chan
);
localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
reg lpf_ce;
wire [AUDIO_DW-1:0] al, ar;
lpf_i2s lpf_l
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(left_chan),
.ODATA(al)
);
lpf_i2s lpf_r
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(right_chan),
.ODATA(ar)
);
always @(posedge clk_sys) begin
reg [31:0] count_q;
reg [31:0] error_q;
always @(posedge clk) begin
reg [7:0] bit_cnt;
reg skip = 0;
reg msclk;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
reg msclk;
reg ce;
lpf_ce <= 0;
if (reset) begin
count_q <= 0;
error_q <= 0;
ce <= 0;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
else begin
sclk <= msclk;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) begin
msclk <= ~msclk;
if(msclk) begin
skip <= ~skip;
if(skip) lpf_ce <= 1;
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= al;
right <= ar;
end
if(ce) begin
msclk <= ~msclk;
if(msclk) begin
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= left_chan;
right <= right_chan;
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
endmodule
module lpf_i2s
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

213
sys/iir_filter.v Normal file
View File

@@ -0,0 +1,213 @@
// 3-tap IIR filter for 2 channels.
// Copyright (C) 2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0)
//
module IIR_filter
#(
parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables.
parameter stereo = 1, // 0 for mono (input_l)
parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9)
parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7
parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7
parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7
parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9)
parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9)
parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9)
)
(
input clk,
input reset,
input ce, // must be double of calculated rate for stereo!
input sample_ce, // desired output sample rate
input [39:0] cx,
input [7:0] cx0,
input [7:0] cx1,
input [7:0] cx2,
input [23:0] cy0,
input [23:0] cy1,
input [23:0] cy2,
input [15:0] input_l, input_r, // signed samples
output [15:0] output_l, output_r // signed samples
);
localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000;
localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000;
localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000;
localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000;
wire [39:0] vcoeff = use_params ? pcoeff_x : cx;
wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0;
wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1;
wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2;
wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff);
wire [39:0] x = inp_mul[59:20];
wire [39:0] y = x + tap0;
wire [39:0] tap0;
iir_filter_tap iir_tap_0
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x0[7:0] : cx0),
.cy(vcoeff_y0),
.x(x),
.y(y),
.z(tap1),
.tap(tap0)
);
wire [39:0] tap1;
iir_filter_tap iir_tap_1
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x1[7:0] : cx1),
.cy(vcoeff_y1),
.x(x),
.y(y),
.z(tap2),
.tap(tap1)
);
wire [39:0] tap2;
iir_filter_tap iir_tap_2
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x2[7:0] : cx2),
.cy(vcoeff_y2),
.x(x),
.y(y),
.z(0),
.tap(tap2)
);
wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20];
reg ch = 0;
reg [15:0] out_l, out_r, out_m;
reg [15:0] inp, inp_m;
always @(posedge clk) if (ce) begin
if(!stereo) begin
ch <= 0;
inp <= input_l;
out_l <= y_clamp;
out_r <= y_clamp;
end
else begin
ch <= ~ch;
if(ch) begin
out_m <= y_clamp;
inp <= inp_m;
end
else begin
out_l <= out_m;
out_r <= y_clamp;
inp <= input_l;
inp_m <= input_r;
end
end
end
reg [31:0] out;
always @(posedge clk) if (sample_ce) out <= {out_l, out_r};
assign {output_l, output_r} = out;
endmodule
module iir_filter_tap
(
input clk,
input reset,
input ce,
input ch,
input [7:0] cx,
input [23:0] cy,
input [39:0] x,
input [39:0] y,
input [39:0] z,
output [39:0] tap
);
wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy);
function [39:0] x_mul;
input [39:0] x;
begin
x_mul = 0;
if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]};
if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]};
if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]};
if(cx[7]) x_mul = ~x_mul; //cheap NEG
end
endfunction
(* ramstyle = "logic" *) reg [39:0] intreg[2];
always @(posedge clk, posedge reset) begin
if(reset) {intreg[0],intreg[1]} <= 80'd0;
else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z;
end
assign tap = intreg[ch];
endmodule
// simplified IIR 1-tap.
module DC_blocker
(
input clk,
input ce, // 48/96 KHz
input mute,
input sample_rate,
input [15:0] din,
output [15:0] dout
);
wire [39:0] x = {din[15], din, 23'd0};
wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]});
wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]});
wire [39:0] y0 = x0 - x1 + y1;
reg [39:0] x1, y;
always @(posedge clk) if(ce) begin
x1 <= x0;
y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0;
end
assign dout = mute ? 16'd0 : y[38:23];
endmodule

60
sys/ip/avalon_combiner.v
View File

@@ -1,60 +0,0 @@
// avalon_combiner.v
`timescale 1 ps / 1 ps
module avalon_combiner
(
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [6:0] mixer_address, // ctl_mixer.address
output wire [3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0] mixer_writedata, // .writedata
input wire mixer_waitrequest, // .waitrequest
output wire [6:0] scaler_address, // ctl_scaler.address
output wire [3:0] scaler_byteenable, // .byteenable
input wire scaler_waitrequest, // .waitrequest
output wire scaler_write, // .write
output wire [31:0] scaler_writedata, // .writedata
output wire [7:0] video_address, // ctl_video.address
output wire [3:0] video_byteenable, // .byteenable
input wire video_waitrequest, // .waitrequest
output wire video_write, // .write
output wire [31:0] video_writedata, // .writedata
output wire clock, // control.clock
output wire reset, // .reset
input wire [8:0] address, // .address
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire waitrequest // .waitrequest
);
assign clock = clk;
assign reset = rst;
assign mixer_address = address[6:0];
assign scaler_address = address[6:0];
assign video_address = address[7:0];
assign mixer_byteenable = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable = 4'b1111;
wire en_scaler = (address[8:7] == 0);
wire en_mixer = (address[8:7] == 1);
wire en_video = address[8];
assign mixer_write = en_mixer & write;
assign scaler_write = en_scaler & write;
assign video_write = en_video & write;
assign mixer_writedata = writedata;
assign scaler_writedata = writedata;
assign video_writedata = writedata;
assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
endmodule

204
sys/ip/avalon_combiner_hw.tcl
View File

@@ -1,204 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Wed Dec 13 01:40:49 CST 2017
# DO NOT MODIFY
#
# avalon_combiner "avalon_combiner" v17.0
# sorgelig 2017.12.13.01:40:49
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module avalon_combiner
#
set_module_property DESCRIPTION ""
set_module_property NAME avalon_combiner
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR sorgelig
set_module_property DISPLAY_NAME avalon_combiner
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rst reset Input 1
#
# connection point ctl_mixer
#
add_interface ctl_mixer avalon start
set_interface_property ctl_mixer addressUnits WORDS
set_interface_property ctl_mixer associatedClock clock
set_interface_property ctl_mixer associatedReset reset
set_interface_property ctl_mixer bitsPerSymbol 8
set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
set_interface_property ctl_mixer burstcountUnits WORDS
set_interface_property ctl_mixer doStreamReads false
set_interface_property ctl_mixer doStreamWrites false
set_interface_property ctl_mixer holdTime 0
set_interface_property ctl_mixer linewrapBursts false
set_interface_property ctl_mixer maximumPendingReadTransactions 0
set_interface_property ctl_mixer maximumPendingWriteTransactions 0
set_interface_property ctl_mixer readLatency 0
set_interface_property ctl_mixer readWaitTime 1
set_interface_property ctl_mixer setupTime 0
set_interface_property ctl_mixer timingUnits Cycles
set_interface_property ctl_mixer writeWaitTime 0
set_interface_property ctl_mixer ENABLED true
set_interface_property ctl_mixer EXPORT_OF ""
set_interface_property ctl_mixer PORT_NAME_MAP ""
set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
add_interface_port ctl_mixer mixer_address address Output 7
add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
add_interface_port ctl_mixer mixer_write write Output 1
add_interface_port ctl_mixer mixer_writedata writedata Output 32
add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
#
# connection point ctl_scaler
#
add_interface ctl_scaler avalon start
set_interface_property ctl_scaler addressUnits WORDS
set_interface_property ctl_scaler associatedClock clock
set_interface_property ctl_scaler associatedReset reset
set_interface_property ctl_scaler bitsPerSymbol 8
set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
set_interface_property ctl_scaler burstcountUnits WORDS
set_interface_property ctl_scaler doStreamReads false
set_interface_property ctl_scaler doStreamWrites false
set_interface_property ctl_scaler holdTime 0
set_interface_property ctl_scaler linewrapBursts false
set_interface_property ctl_scaler maximumPendingReadTransactions 0
set_interface_property ctl_scaler maximumPendingWriteTransactions 0
set_interface_property ctl_scaler readLatency 0
set_interface_property ctl_scaler readWaitTime 1
set_interface_property ctl_scaler setupTime 0
set_interface_property ctl_scaler timingUnits Cycles
set_interface_property ctl_scaler writeWaitTime 0
set_interface_property ctl_scaler ENABLED true
set_interface_property ctl_scaler EXPORT_OF ""
set_interface_property ctl_scaler PORT_NAME_MAP ""
set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
add_interface_port ctl_scaler scaler_address address Output 7
add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
add_interface_port ctl_scaler scaler_write write Output 1
add_interface_port ctl_scaler scaler_writedata writedata Output 32
#
# connection point ctl_video
#
add_interface ctl_video avalon start
set_interface_property ctl_video addressUnits WORDS
set_interface_property ctl_video associatedClock clock
set_interface_property ctl_video associatedReset reset
set_interface_property ctl_video bitsPerSymbol 8
set_interface_property ctl_video burstOnBurstBoundariesOnly false
set_interface_property ctl_video burstcountUnits WORDS
set_interface_property ctl_video doStreamReads false
set_interface_property ctl_video doStreamWrites false
set_interface_property ctl_video holdTime 0
set_interface_property ctl_video linewrapBursts false
set_interface_property ctl_video maximumPendingReadTransactions 0
set_interface_property ctl_video maximumPendingWriteTransactions 0
set_interface_property ctl_video readLatency 0
set_interface_property ctl_video readWaitTime 1
set_interface_property ctl_video setupTime 0
set_interface_property ctl_video timingUnits Cycles
set_interface_property ctl_video writeWaitTime 0
set_interface_property ctl_video ENABLED true
set_interface_property ctl_video EXPORT_OF ""
set_interface_property ctl_video PORT_NAME_MAP ""
set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
set_interface_property ctl_video SVD_ADDRESS_GROUP ""
add_interface_port ctl_video video_address address Output 8
add_interface_port ctl_video video_byteenable byteenable Output 4
add_interface_port ctl_video video_waitrequest waitrequest Input 1
add_interface_port ctl_video video_write write Output 1
add_interface_port ctl_video video_writedata writedata Output 32
#
# connection point control
#
add_interface control conduit end
set_interface_property control associatedClock clock
set_interface_property control associatedReset reset
set_interface_property control ENABLED true
set_interface_property control EXPORT_OF ""
set_interface_property control PORT_NAME_MAP ""
set_interface_property control CMSIS_SVD_VARIABLES ""
set_interface_property control SVD_ADDRESS_GROUP ""
add_interface_port control address address Input 9
add_interface_port control write write Input 1
add_interface_port control writedata writedata Input 32
add_interface_port control waitrequest waitrequest Output 1
add_interface_port control clock clock Output 1
add_interface_port control reset reset Output 1

3706
sys/ip/de10_hps_hw.tcl
View File

File diff suppressed because it is too large Load Diff

52
sys/ip/in_split.v
View File

@@ -1,52 +0,0 @@
// in_split.v
`timescale 1 ps / 1 ps
module in_split (
input wire clk, // input.clk
input wire ce, // .ce
input wire de, // .de
input wire h_sync, // .h_sync
input wire v_sync, // .v_sync
input wire f, // .f
input wire [23:0] data, // .data
output wire vid_clk, // Output.vid_clk
output reg vid_datavalid, // .vid_datavalid
output reg [1:0] vid_de, // .vid_de
output reg [1:0] vid_f, // .vid_f
output reg [1:0] vid_h_sync, // .vid_h_sync
output reg [1:0] vid_v_sync, // .vid_v_sync
output reg [47:0] vid_data, // .vid_data
output wire vid_locked, // .vid_locked
output wire [7:0] vid_color_encoding, // .vid_color_encoding
output wire [7:0] vid_bit_width, // .vid_bit_width
input wire clipping, // .clipping
input wire overflow, // .overflow
input wire sof, // .sof
input wire sof_locked, // .sof_locked
input wire refclk_div, // .refclk_div
input wire padding // .padding
);
assign vid_bit_width = 0;
assign vid_color_encoding = 0;
assign vid_locked = 1;
assign vid_clk = clk;
always @(posedge clk) begin
reg odd = 0;
vid_datavalid <= 0;
if(ce) begin
vid_de[odd] <= de;
vid_f[odd] <= f;
vid_h_sync[odd] <= h_sync;
vid_v_sync[odd] <= v_sync;
if(odd) vid_data[47:24] <= data;
else vid_data[23:0] <= data;
odd <= ~odd;
vid_datavalid <= odd;
end
end
endmodule

104
sys/ip/in_split_hw.tcl
View File

@@ -1,104 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 18:50:29 CST 2018
# DO NOT MODIFY
#
# in_split "Input Splitter" v17.0
# Sorgelig 2018.01.25.18:50:29
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module in_split
#
set_module_property DESCRIPTION ""
set_module_property NAME in_split
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Input Splitter"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input clk clk Input 1
add_interface_port input ce ce Input 1
add_interface_port input de de Input 1
add_interface_port input h_sync h_sync Input 1
add_interface_port input v_sync v_sync Input 1
add_interface_port input f f Input 1
add_interface_port input data data Input 24
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output vid_clk vid_clk Output 1
add_interface_port Output vid_datavalid vid_datavalid Output 1
add_interface_port Output vid_de vid_de Output 2
add_interface_port Output vid_f vid_f Output 2
add_interface_port Output vid_h_sync vid_h_sync Output 2
add_interface_port Output vid_v_sync vid_v_sync Output 2
add_interface_port Output vid_data vid_data Output 48
add_interface_port Output vid_locked vid_locked Output 1
add_interface_port Output vid_color_encoding vid_color_encoding Output 8
add_interface_port Output vid_bit_width vid_bit_width Output 8
add_interface_port Output clipping clipping Input 1
add_interface_port Output overflow overflow Input 1
add_interface_port Output sof sof Input 1
add_interface_port Output sof_locked sof_locked Input 1
add_interface_port Output refclk_div refclk_div Input 1
add_interface_port Output padding padding Input 1

44
sys/ip/out_mix.v
View File

@@ -1,44 +0,0 @@
// out_mix.v
`timescale 1 ps / 1 ps
module out_mix (
input wire clk, // Output.clk
output reg de, // .de
output reg h_sync, // .h_sync
output reg v_sync, // .v_sync
output reg [23:0] data, // .data
output reg vid_clk, // input.vid_clk
input wire [1:0] vid_datavalid, // .vid_datavalid
input wire [1:0] vid_h_sync, // .vid_h_sync
input wire [1:0] vid_v_sync, // .vid_v_sync
input wire [47:0] vid_data, // .vid_data
input wire underflow, // .underflow
input wire vid_mode_change, // .vid_mode_change
input wire [1:0] vid_std, // .vid_std
input wire [1:0] vid_f, // .vid_f
input wire [1:0] vid_h, // .vid_h
input wire [1:0] vid_v // .vid_v
);
reg r_de;
reg r_h_sync;
reg r_v_sync;
reg [23:0] r_data;
always @(posedge clk) begin
vid_clk <= ~vid_clk;
if(~vid_clk) begin
{r_de,de} <= vid_datavalid;
{r_h_sync, h_sync} <= vid_h_sync;
{r_v_sync, v_sync} <= vid_v_sync;
{r_data, data} <= vid_data;
end else begin
de <= r_de;
h_sync <= r_h_sync;
v_sync <= r_v_sync;
data <= r_data;
end
end
endmodule

97
sys/ip/out_mix_hw.tcl
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@@ -1,97 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 06:51:26 CST 2018
# DO NOT MODIFY
#
# out_mix "Output Mixer" v1.0
# Sorgelig 2018.01.25.06:51:26
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module out_mix
#
set_module_property DESCRIPTION ""
set_module_property NAME out_mix
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Output Mixer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output clk clk Input 1
add_interface_port Output de de Output 1
add_interface_port Output h_sync h_sync Output 1
add_interface_port Output v_sync v_sync Output 1
add_interface_port Output data data Output 24
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input vid_clk vid_clk Output 1
add_interface_port input vid_datavalid vid_datavalid Input 2
add_interface_port input vid_h_sync vid_h_sync Input 2
add_interface_port input vid_v_sync vid_v_sync Input 2
add_interface_port input vid_data vid_data Input 48
add_interface_port input underflow underflow Input 1
add_interface_port input vid_mode_change vid_mode_change Input 1
add_interface_port input vid_std vid_std Input 2
add_interface_port input vid_f vid_f Input 2
add_interface_port input vid_h vid_h Input 2
add_interface_port input vid_v vid_v Input 2

50
sys/ip/reset_source.v
View File

@@ -1,50 +0,0 @@
// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire reset_vip, // .reset_vip
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
wire reset_m = sys_reset | reset_hps | reset_req;
assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

152
sys/ip/reset_source_hw.tcl
View File

@@ -1,152 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Tue Feb 20 07:55:55 CST 2018
# DO NOT MODIFY
#
# reset_source "reset_source" v17.0
# Sorgelig 2018.02.20.07:55:55
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module reset_source
#
set_module_property DESCRIPTION ""
set_module_property NAME reset_source
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME reset_source
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_hps
#
add_interface reset_hps reset end
set_interface_property reset_hps associatedClock ""
set_interface_property reset_hps synchronousEdges NONE
set_interface_property reset_hps ENABLED true
set_interface_property reset_hps EXPORT_OF ""
set_interface_property reset_hps PORT_NAME_MAP ""
set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
set_interface_property reset_hps SVD_ADDRESS_GROUP ""
add_interface_port reset_hps reset_hps reset Input 1
#
# connection point reset_sys
#
add_interface reset_sys reset start
set_interface_property reset_sys associatedClock ""
set_interface_property reset_sys associatedDirectReset ""
set_interface_property reset_sys associatedResetSinks ""
set_interface_property reset_sys synchronousEdges NONE
set_interface_property reset_sys ENABLED true
set_interface_property reset_sys EXPORT_OF ""
set_interface_property reset_sys PORT_NAME_MAP ""
set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
set_interface_property reset_sys SVD_ADDRESS_GROUP ""
add_interface_port reset_sys reset_sys reset Output 1
#
# connection point reset_ctl
#
add_interface reset_ctl conduit end
set_interface_property reset_ctl associatedClock ""
set_interface_property reset_ctl associatedReset ""
set_interface_property reset_ctl ENABLED true
set_interface_property reset_ctl EXPORT_OF ""
set_interface_property reset_ctl PORT_NAME_MAP ""
set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
add_interface_port reset_ctl cold_req cold_req Input 1
add_interface_port reset_ctl reset reset Output 1
add_interface_port reset_ctl reset_req reset_req Input 1
add_interface_port reset_ctl warm_req warm_req Input 1
add_interface_port reset_ctl reset_vip reset_vip Input 1
#
# connection point reset_warm
#
add_interface reset_warm reset start
set_interface_property reset_warm associatedClock ""
set_interface_property reset_warm associatedDirectReset ""
set_interface_property reset_warm associatedResetSinks ""
set_interface_property reset_warm synchronousEdges NONE
set_interface_property reset_warm ENABLED true
set_interface_property reset_warm EXPORT_OF ""
set_interface_property reset_warm PORT_NAME_MAP ""
set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
set_interface_property reset_warm SVD_ADDRESS_GROUP ""
add_interface_port reset_warm reset_warm reset Output 1
#
# connection point reset_cold
#
add_interface reset_cold reset start
set_interface_property reset_cold associatedClock ""
set_interface_property reset_cold associatedDirectReset ""
set_interface_property reset_cold associatedResetSinks ""
set_interface_property reset_cold synchronousEdges NONE
set_interface_property reset_cold ENABLED true
set_interface_property reset_cold EXPORT_OF ""
set_interface_property reset_cold PORT_NAME_MAP ""
set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
set_interface_property reset_cold SVD_ADDRESS_GROUP ""
add_interface_port reset_cold reset_cold reset Output 1

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