V1.1 Add 6502 Basic and 6802 Basic

Add 6502 Basic and 6802 Basic accessible by the OSD MiSTer menu.

Microcomputer6502Basic.vhd

@@ -0,0 +1,296 @@
+-- This file is copyright by Grant Searle 2014
+-- You are free to use this file in your own projects but must never charge for it nor use it without
+-- acknowledgement.
+-- Please ask permission from Grant Searle before republishing elsewhere.
+-- If you use this file or any part of it, please add an acknowledgement to myself and
+-- a link back to my main web site http://searle.hostei.com/grant/    
+-- and to the "multicomp" page at http://searle.hostei.com/grant/Multicomp/index.html
+--
+-- Please check on the above web pages to see if there are any updates before using this file.
+-- If for some reason the page is no longer available, please search for "Grant Searle"
+-- on the internet to see if I have moved to another web hosting service.
+--
+-- Grant Searle
+-- eMail address available on my main web page link above.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use  IEEE.STD_LOGIC_ARITH.all;
+use  IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity Microcomputer6502Basic is
+	port(
+		N_RESET	   : in std_logic;
+		clk			: in std_logic;
+
+		sramData		: inout std_logic_vector(7 downto 0);
+		sramAddress	: out std_logic_vector(15 downto 0);
+		n_sRamWE		: out std_logic;
+		n_sRamCS		: out std_logic;
+		n_sRamOE		: out std_logic;
+		n_sRamLB		: out std_logic;
+		n_sRamUB		: out std_logic;
+		
+		rxd1			: in std_logic;
+		txd1			: out std_logic;
+		rts1			: out std_logic;
+
+		rxd2			: in std_logic;
+		txd2			: out std_logic;
+		rts2			: out std_logic;
+		
+		videoSync	: out std_logic;
+		video			: out std_logic;
+
+		R       		: out std_logic_vector(1 downto 0);
+		G       		: out std_logic_vector(1 downto 0);
+		B       		: out std_logic_vector(1 downto 0);
+		HS		  		: out std_logic;
+		VS 			: out std_logic;
+		hBlank		: out std_logic;
+		vBlank		: out std_logic;
+		cepix  		: out std_logic;
+
+		ps2Clk		: in std_logic;
+		ps2Data		: in std_logic;
+
+		sdCS			: out std_logic;
+		sdMOSI		: out std_logic;
+		sdMISO		: in std_logic;
+		sdSCLK		: out std_logic;
+		driveLED		: out std_logic :='1'	
+	);
+end Microcomputer6502Basic;
+
+architecture struct of Microcomputer6502Basic is
+
+	signal n_WR							: std_logic;
+	signal n_RD							: std_logic;
+	signal cpuAddress					: std_logic_vector(15 downto 0);
+	signal cpuDataOut					: std_logic_vector(7 downto 0);
+	signal cpuDataIn					: std_logic_vector(7 downto 0);
+
+	signal basRomData					: std_logic_vector(7 downto 0);
+	signal internalRam1DataOut		: std_logic_vector(7 downto 0);
+	signal internalRam2DataOut		: std_logic_vector(7 downto 0);
+	signal interface1DataOut		: std_logic_vector(7 downto 0);
+	signal interface2DataOut		: std_logic_vector(7 downto 0);
+	signal sdCardDataOut				: std_logic_vector(7 downto 0);
+
+	signal n_memWR						: std_logic :='1';
+	signal n_memRD 					: std_logic :='1';
+
+	signal n_ioWR						: std_logic :='1';
+	signal n_ioRD 						: std_logic :='1';
+	
+	signal n_MREQ						: std_logic :='1';
+	signal n_IORQ						: std_logic :='1';	
+
+	signal n_int1						: std_logic :='1';	
+	signal n_int2						: std_logic :='1';	
+	
+	signal n_externalRamCS			: std_logic :='1';
+	signal n_internalRam1CS			: std_logic :='1';
+	signal n_internalRam2CS			: std_logic :='1';
+	signal n_basRomCS					: std_logic :='1';
+	signal n_interface1CS			: std_logic :='1';
+	signal n_interface2CS			: std_logic :='1';
+	signal n_sdCardCS					: std_logic :='1';
+
+	signal serialClkCount			: std_logic_vector(15 downto 0);
+	signal cpuClkCount				: std_logic_vector(5 downto 0); 
+	signal sdClkCount					: std_logic_vector(5 downto 0); 	
+	signal cpuClock					: std_logic;
+	signal serialClock				: std_logic;
+	signal sdClock						: std_logic;
+
+begin
+
+-- ____________________________________________________________________________________
+-- CPU CHOICE GOES HERE
+
+cpu1 : entity work.T65
+port map(
+	Enable => '1',
+	Mode => "00",
+	Res_n => N_RESET,
+	Clk => cpuClock,
+	Rdy => '1',
+	Abort_n => '1',
+	IRQ_n => '1',
+	NMI_n => '1',
+	SO_n => '1',
+	R_W_n => n_WR,
+	A(15 downto 0) => cpuAddress,
+	DI => cpuDataIn,
+	DO => cpuDataOut
+);
+
+-- ____________________________________________________________________________________
+-- ROM GOES HERE	
+
+rom1 : entity work.M6502_BASIC_ROM -- 8KB BASIC
+port map(
+	address => cpuAddress(12 downto 0),
+	clock => clk,
+	q => basRomData
+);
+
+-- ____________________________________________________________________________________
+-- RAM GOES HERE
+
+ram1: entity work.InternalRam64K
+port map
+(
+	address => cpuAddress(15 downto 0),
+	clock => clk,
+	data => cpuDataOut,
+	wren => not(n_memWR or n_internalRam1CS),
+	q => internalRam1DataOut
+);
+
+-- ____________________________________________________________________________________
+-- INPUT/OUTPUT DEVICES GO HERE	
+
+io1 : entity work.SBCTextDisplayRGB
+port map (
+	n_reset => N_RESET,
+	clk => clk,
+
+	-- RGB video signals
+	hSync => HS,
+	vSync => VS,
+   videoR0 => R(1),
+   videoR1 => R(0),
+   videoG0 => G(1),
+   videoG1 => G(0),
+   videoB0 => B(1),
+   videoB1 => B(0),
+	hBlank => hBlank,
+	vBlank => vBlank,
+	cepix => cepix,
+
+	-- Monochrome video signals (when using TV timings only)
+	sync => videoSync,
+	video => video,
+
+	n_wr => n_interface1CS or cpuClock or n_WR,
+	n_rd => n_interface1CS or cpuClock or (not n_WR),
+	n_int => n_int1,
+	regSel => cpuAddress(0),
+	dataIn => cpuDataOut,
+	dataOut => interface1DataOut,
+	ps2Clk => ps2Clk,
+	ps2Data => ps2Data
+);
+
+io2 : entity work.bufferedUART
+port map(
+	clk => clk,
+	n_wr => n_interface1CS or cpuClock or n_WR,
+	n_rd => n_interface1CS or cpuClock or (not n_WR),
+	n_int => n_int1,
+	regSel => cpuAddress(0),
+	dataIn => cpuDataOut,
+	dataOut => interface2DataOut,
+	rxClock => serialClock,
+	txClock => serialClock,
+	rxd => rxd1,
+	txd => txd1,
+	n_cts => '0',
+	n_dcd => '0',
+	n_rts => rts1
+);
+
+sd1 : entity work.sd_controller
+port map(
+	sdCS => sdCS,
+	sdMOSI => sdMOSI,
+	sdMISO => sdMISO,
+	sdSCLK => sdSCLK,
+	n_wr => n_sdCardCS or cpuClock or n_WR,
+	n_rd => n_sdCardCS or cpuClock or (not n_WR),
+	n_reset => n_reset,
+	dataIn => cpuDataOut,
+	dataOut => sdCardDataOut,
+	regAddr => cpuAddress(2 downto 0),
+	driveLED => driveLED,
+	clk => sdClock -- twice the spi clk
+);
+
+-- ____________________________________________________________________________________
+-- MEMORY READ/WRITE LOGIC GOES HERE
+
+n_memRD <= not(cpuClock) nand n_WR;
+n_memWR <= not(cpuClock) nand (not n_WR);
+
+-- ____________________________________________________________________________________
+-- CHIP SELECTS GO HERE
+
+
+n_basRomCS <= '0' when cpuAddress(15 downto 13) = "111" else '1'; --8K at top of memory
+n_interface1CS <= '0' when cpuAddress(15 downto 1) = "111111111101000" else '1'; -- 2 bytes FFD0-FFD1
+n_interface2CS <= '0' when cpuAddress(15 downto 1) = "111111111101001" else '1'; -- 2 bytes FFD2-FFD3
+n_sdCardCS <= '0' when cpuAddress(15 downto 3) = "1111111111011" else '1'; -- 8 bytes FFD8-FFDF
+n_internalRam1CS <= not n_basRomCS; -- Full Internal RAM - 64 K
+
+-- ____________________________________________________________________________________
+-- BUS ISOLATION GOES HERE
+
+cpuDataIn <=
+interface1DataOut when n_interface1CS = '0' else
+interface2DataOut when n_interface2CS = '0' else
+sdCardDataOut when n_sdCardCS = '0' else
+basRomData when n_basRomCS = '0' else
+internalRam1DataOut when n_internalRam1CS= '0' else
+sramData when n_externalRamCS= '0' else
+x"FF";
+
+-- ____________________________________________________________________________________
+-- SYSTEM CLOCKS GO HERE
+
+
+-- SUB-CIRCUIT CLOCK SIGNALS
+
+serialClock <= serialClkCount(15);
+process (clk)
+begin
+	if rising_edge(clk) then
+
+		if cpuClkCount < 4 then -- 4 = 10MHz, 3 = 12.5MHz, 2=16.6MHz, 1=25MHz
+			cpuClkCount <= cpuClkCount + 1;
+		else
+			cpuClkCount <= (others=>'0');
+		end if;
+		if cpuClkCount < 2 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
+			cpuClock <= '0';
+		else
+			cpuClock <= '1';
+		end if; 
+
+		if sdClkCount < 49 then -- 1MHz
+			sdClkCount <= sdClkCount + 1;
+		else
+			sdClkCount <= (others=>'0');
+		end if;
+
+		if sdClkCount < 25 then
+			sdClock <= '0';
+		else
+			sdClock <= '1';
+		end if;
+
+		-- Serial clock DDS
+		-- 50MHz master input clock:
+		-- Baud Increment
+		-- 115200 2416
+		-- 38400 805
+		-- 19200 403
+		-- 9600 201
+		-- 4800 101
+		-- 2400 50
+		serialClkCount <= serialClkCount + 2416;
+	end if;
+end process;
+
+end;

Microcomputer6809Basic.vhd

@@ -0,0 +1,294 @@
+-- This file is copyright by Grant Searle 2014
+-- You are free to use this file in your own projects but must never charge for it nor use it without
+-- acknowledgement.
+-- Please ask permission from Grant Searle before republishing elsewhere.
+-- If you use this file or any part of it, please add an acknowledgement to myself and
+-- a link back to my main web site http://searle.hostei.com/grant/    
+-- and to the "multicomp" page at http://searle.hostei.com/grant/Multicomp/index.html
+--
+-- Please check on the above web pages to see if there are any updates before using this file.
+-- If for some reason the page is no longer available, please search for "Grant Searle"
+-- on the internet to see if I have moved to another web hosting service.
+--
+-- Grant Searle
+-- eMail address available on my main web page link above.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use  IEEE.STD_LOGIC_ARITH.all;
+use  IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity Microcomputer6809Basic is
+	port(
+		N_RESET	   : in std_logic;
+		clk			: in std_logic;
+
+		sramData		: inout std_logic_vector(7 downto 0);
+		sramAddress	: out std_logic_vector(15 downto 0);
+		n_sRamWE		: out std_logic;
+		n_sRamCS		: out std_logic;
+		n_sRamOE		: out std_logic;
+		n_sRamLB		: out std_logic;
+		n_sRamUB		: out std_logic;
+		
+		rxd1			: in std_logic;
+		txd1			: out std_logic;
+		rts1			: out std_logic;
+
+		rxd2			: in std_logic;
+		txd2			: out std_logic;
+		rts2			: out std_logic;
+		
+		videoSync	: out std_logic;
+		video			: out std_logic;
+
+		R       		: out std_logic_vector(1 downto 0);
+		G       		: out std_logic_vector(1 downto 0);
+		B       		: out std_logic_vector(1 downto 0);
+		HS		  		: out std_logic;
+		VS 			: out std_logic;
+		hBlank		: out std_logic;
+		vBlank		: out std_logic;
+		cepix  		: out std_logic;
+
+		ps2Clk		: in std_logic;
+		ps2Data		: in std_logic;
+
+		sdCS			: out std_logic;
+		sdMOSI		: out std_logic;
+		sdMISO		: in std_logic;
+		sdSCLK		: out std_logic;
+		driveLED		: out std_logic :='1'	
+	);
+end Microcomputer6809Basic;
+
+architecture struct of Microcomputer6809Basic is
+
+	signal n_WR							: std_logic;
+	signal n_RD							: std_logic;
+	signal cpuAddress					: std_logic_vector(15 downto 0);
+	signal cpuDataOut					: std_logic_vector(7 downto 0);
+	signal cpuDataIn					: std_logic_vector(7 downto 0);
+
+	signal basRomData					: std_logic_vector(7 downto 0);
+	signal internalRam1DataOut		: std_logic_vector(7 downto 0);
+	signal internalRam2DataOut		: std_logic_vector(7 downto 0);
+	signal interface1DataOut		: std_logic_vector(7 downto 0);
+	signal interface2DataOut		: std_logic_vector(7 downto 0);
+	signal sdCardDataOut				: std_logic_vector(7 downto 0);
+
+	signal n_memWR						: std_logic :='1';
+	signal n_memRD 					: std_logic :='1';
+
+	signal n_ioWR						: std_logic :='1';
+	signal n_ioRD 						: std_logic :='1';
+	
+	signal n_MREQ						: std_logic :='1';
+	signal n_IORQ						: std_logic :='1';	
+
+	signal n_int1						: std_logic :='1';	
+	signal n_int2						: std_logic :='1';	
+	
+	signal n_externalRamCS			: std_logic :='1';
+	signal n_internalRam1CS			: std_logic :='1';
+	signal n_internalRam2CS			: std_logic :='1';
+	signal n_basRomCS					: std_logic :='1';
+	signal n_interface1CS			: std_logic :='1';
+	signal n_interface2CS			: std_logic :='1';
+	signal n_sdCardCS					: std_logic :='1';
+
+	signal serialClkCount			: std_logic_vector(15 downto 0);
+	signal cpuClkCount				: std_logic_vector(5 downto 0); 
+	signal sdClkCount					: std_logic_vector(5 downto 0); 	
+	signal cpuClock					: std_logic;
+	signal serialClock				: std_logic;
+	signal sdClock						: std_logic;
+
+begin
+
+-- ____________________________________________________________________________________
+-- CPU CHOICE GOES HERE
+
+cpu1 : entity work.cpu09
+port map(
+	clk => not(cpuClock),
+	rst => not N_RESET,
+	rw => n_WR,
+	addr => cpuAddress,
+	data_in => cpuDataIn,
+	data_out => cpuDataOut,
+	halt => '0',
+	hold => '0',
+	irq => '0',
+	firq => '0',
+	nmi => '0'
+); 
+
+-- ____________________________________________________________________________________
+-- ROM GOES HERE	
+
+rom1 : entity work.M6809_EXT_BASIC_ROM -- 8KB BASIC
+port map(
+	address => cpuAddress(12 downto 0),
+	clock => clk,
+	q => basRomData
+);
+
+-- ____________________________________________________________________________________
+-- RAM GOES HERE
+
+ram1: entity work.InternalRam64K
+port map
+(
+	address => cpuAddress(15 downto 0),
+	clock => clk,
+	data => cpuDataOut,
+	wren => not(n_memWR or n_internalRam1CS),
+	q => internalRam1DataOut
+);
+
+-- ____________________________________________________________________________________
+-- INPUT/OUTPUT DEVICES GO HERE	
+
+io1 : entity work.SBCTextDisplayRGB
+port map (
+	n_reset => N_RESET,
+	clk => clk,
+
+	-- RGB video signals
+	hSync => HS,
+	vSync => VS,
+   videoR0 => R(1),
+   videoR1 => R(0),
+   videoG0 => G(1),
+   videoG1 => G(0),
+   videoB0 => B(1),
+   videoB1 => B(0),
+	hBlank => hBlank,
+	vBlank => vBlank,
+	cepix => cepix,
+
+	-- Monochrome video signals (when using TV timings only)
+	sync => videoSync,
+	video => video,
+
+	n_wr => n_interface1CS or cpuClock or n_WR,
+	n_rd => n_interface1CS or cpuClock or (not n_WR),
+	n_int => n_int1,
+	regSel => cpuAddress(0),
+	dataIn => cpuDataOut,
+	dataOut => interface1DataOut,
+	ps2Clk => ps2Clk,
+	ps2Data => ps2Data
+);
+
+io2 : entity work.bufferedUART
+port map(
+	clk => clk,
+	n_wr => n_interface1CS or cpuClock or n_WR,
+	n_rd => n_interface1CS or cpuClock or (not n_WR),
+	n_int => n_int1,
+	regSel => cpuAddress(0),
+	dataIn => cpuDataOut,
+	dataOut => interface2DataOut,
+	rxClock => serialClock,
+	txClock => serialClock,
+	rxd => rxd1,
+	txd => txd1,
+	n_cts => '0',
+	n_dcd => '0',
+	n_rts => rts1
+);
+
+sd1 : entity work.sd_controller
+port map(
+	sdCS => sdCS,
+	sdMOSI => sdMOSI,
+	sdMISO => sdMISO,
+	sdSCLK => sdSCLK,
+	n_wr => n_sdCardCS or cpuClock or n_WR,
+	n_rd => n_sdCardCS or cpuClock or (not n_WR),
+	n_reset => n_reset,
+	dataIn => cpuDataOut,
+	dataOut => sdCardDataOut,
+	regAddr => cpuAddress(2 downto 0),
+	driveLED => driveLED,
+	clk => sdClock -- twice the spi clk
+);
+
+-- ____________________________________________________________________________________
+-- MEMORY READ/WRITE LOGIC GOES HERE
+
+n_memRD <= not(cpuClock) nand n_WR;
+n_memWR <= not(cpuClock) nand (not n_WR);
+
+-- ____________________________________________________________________________________
+-- CHIP SELECTS GO HERE
+
+
+n_basRomCS <= '0' when cpuAddress(15 downto 13) = "111" else '1'; --8K at top of memory
+n_interface1CS <= '0' when cpuAddress(15 downto 1) = "111111111101000" else '1'; -- 2 bytes FFD0-FFD1
+n_interface2CS <= '0' when cpuAddress(15 downto 1) = "111111111101001" else '1'; -- 2 bytes FFD2-FFD3
+n_sdCardCS <= '0' when cpuAddress(15 downto 3) = "1111111111011" else '1'; -- 8 bytes FFD8-FFDF
+n_internalRam1CS <= not n_basRomCS; -- Full Internal RAM - 64 K
+
+-- ____________________________________________________________________________________
+-- BUS ISOLATION GOES HERE
+
+cpuDataIn <=
+interface1DataOut when n_interface1CS = '0' else
+interface2DataOut when n_interface2CS = '0' else
+sdCardDataOut when n_sdCardCS = '0' else
+basRomData when n_basRomCS = '0' else
+internalRam1DataOut when n_internalRam1CS= '0' else
+sramData when n_externalRamCS= '0' else
+x"FF";
+
+-- ____________________________________________________________________________________
+-- SYSTEM CLOCKS GO HERE
+
+
+-- SUB-CIRCUIT CLOCK SIGNALS
+
+serialClock <= serialClkCount(15);
+process (clk)
+begin
+	if rising_edge(clk) then
+
+		if cpuClkCount < 4 then -- 4 = 10MHz, 3 = 12.5MHz, 2=16.6MHz, 1=25MHz
+			cpuClkCount <= cpuClkCount + 1;
+		else
+			cpuClkCount <= (others=>'0');
+		end if;
+		if cpuClkCount < 2 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
+			cpuClock <= '0';
+		else
+			cpuClock <= '1';
+		end if; 
+
+		if sdClkCount < 49 then -- 1MHz
+			sdClkCount <= sdClkCount + 1;
+		else
+			sdClkCount <= (others=>'0');
+		end if;
+
+		if sdClkCount < 25 then
+			sdClock <= '0';
+		else
+			sdClock <= '1';
+		end if;
+
+		-- Serial clock DDS
+		-- 50MHz master input clock:
+		-- Baud Increment
+		-- 115200 2416
+		-- 38400 805
+		-- 19200 403
+		-- 9600 201
+		-- 4800 101
+		-- 2400 50
+		serialClkCount <= serialClkCount + 2416;
+	end if;
+end process;
+
+end;

MultiComp-lite.qsf

@@ -357,7 +357,6 @@ set_global_assignment -name CDF_FILE jtag.cdf
 set_global_assignment -name QIP_FILE sys/sys.qip
 set_global_assignment -name SYSTEMVERILOG_FILE MultiComp.sv
 set_global_assignment -name VHDL_FILE Components/M6809/cpu09l.vhd
-set_global_assignment -name VHDL_FILE Components/TERMINAL/SBCTextDisplayRGB.vhd
 set_global_assignment -name VHDL_FILE Components/M6800/cpu68.vhd
 set_global_assignment -name VHDL_FILE Components/Z80/T80s.vhd
 set_global_assignment -name VHDL_FILE Components/Z80/T80_Reg.vhd
@@ -365,22 +364,23 @@ set_global_assignment -name VHDL_FILE Components/Z80/T80_Pack.vhd
 set_global_assignment -name VHDL_FILE Components/Z80/T80_MCode.vhd
 set_global_assignment -name VHDL_FILE Components/Z80/T80_ALU.vhd
 set_global_assignment -name VHDL_FILE Components/Z80/T80.vhd
-set_global_assignment -name VHDL_FILE Components/TERMINAL/CGABoldRom.vhd
-set_global_assignment -name VHDL_FILE Components/UART/bufferedUART.vhd
 set_global_assignment -name VHDL_FILE Components/M6502/T65_Pack.vhd
 set_global_assignment -name VHDL_FILE Components/M6502/T65_MCode.vhd
 set_global_assignment -name VHDL_FILE Components/M6502/T65_ALU.vhd
 set_global_assignment -name VHDL_FILE Components/M6502/T65.vhd
+set_global_assignment -name VHDL_FILE Components/UART/bufferedUART.vhd
 set_global_assignment -name VHDL_FILE Components/SDCARD/sd_controller.vhd
 set_global_assignment -name QIP_FILE Components/INTERNALRAM/InternalRam64K.qip
-set_global_assignment -name QIP_FILE ROMS/6502/M6502_BASIC_ROM.qip
-set_global_assignment -name QIP_FILE ROMS/Z80/Z80_BASIC_ROM.qip
+set_global_assignment -name VHDL_FILE Components/TERMINAL/SBCTextDisplayRGB.vhd
+set_global_assignment -name VHDL_FILE Components/TERMINAL/CGABoldRom.vhd
 set_global_assignment -name QIP_FILE Components/TERMINAL/DisplayRam1K.qip
-set_global_assignment -name CDF_FILE output_files/m6502.cdf
 set_global_assignment -name QIP_FILE Components/TERMINAL/DisplayRam2K.qip
 set_global_assignment -name QIP_FILE Components/TERMINAL/CGABoldRomReduced.qip
+set_global_assignment -name QIP_FILE ROMS/Z80/Z80_BASIC_ROM.qip
+set_global_assignment -name QIP_FILE ROMS/6502/M6502_BASIC_ROM.qip
 set_global_assignment -name QIP_FILE ROMS/6809/M6809_EXT_BASIC_ROM.qip
 set_global_assignment -name QIP_FILE ROMS/Z80/Z80_CPM_BASIC_ROM.qip
 set_global_assignment -name VHDL_FILE MicrocomputerZ80CPM.vhd
-set_global_assignment -name VHDL_FILE MicrocomputerZ80Basic.vhd
+set_global_assignment -name VHDL_FILE Microcomputer6502Basic.vhd
+set_global_assignment -name VHDL_FILE Microcomputer6809Basic.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

MultiComp.qsf

@@ -381,5 +381,6 @@ set_global_assignment -name QIP_FILE Components/TERMINAL/CGABoldRomReduced.qip
 set_global_assignment -name QIP_FILE ROMS/6809/M6809_EXT_BASIC_ROM.qip
 set_global_assignment -name QIP_FILE ROMS/Z80/Z80_CPM_BASIC_ROM.qip
 set_global_assignment -name VHDL_FILE MicrocomputerZ80CPM.vhd
-set_global_assignment -name VHDL_FILE MicrocomputerZ80Basic.vhd
+set_global_assignment -name VHDL_FILE Microcomputer6502Basic.vhd
+set_global_assignment -name VHDL_FILE Microcomputer6809Basic.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

MultiComp.sv

@@ -110,6 +110,8 @@ assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DD
 
 assign LED_USER  = 0;
 assign LED_DISK  = ~driveLED;
+
+
 assign LED_POWER = 0;
 
 assign VIDEO_ARX = 4;
@@ -119,10 +121,10 @@ assign VIDEO_ARY = 3;
 `include "build_id.v"
 localparam CONF_STR = {
 	"MultiComp;;",
-	//"-;",
-	//"O79,CPU/ROM,Z80-CP/M,Z80-Basic,6502-Basic,6809-Basic;",
 	"-;",
-	"V,v1.0.",`BUILD_DATE
+	"O78,CPU-ROM,Z80-CP/M,6502-Basic,6809-Basic;",
+	"-;",
+	"V,v1.1.",`BUILD_DATE
 };
 
 
@@ -168,33 +170,103 @@ wire reset = RESET | status[0] | buttons[1];
 
 assign CLK_VIDEO = CLK_50M;
 
+typedef enum {cpuZ80CPM='b00, cpu6502Basic='b01, cpu6809Basic='b10} cpu_type_enum;
+wire [1:0] cpu_type = status[8:7];
+
 wire hblank, vblank;
 wire hs, vs;
 wire [1:0] r,g,b;
 wire driveLED;
-//wire [2:0] cpu_rom_type = status[9:7];
+
+wire [2:0] _hblank, _vblank;
+wire [2:0] _hs, _vs;
+wire [1:0] _r[2:0], _g[2:0], _b[2:0];
+wire [2:0] _CE_PIXEL;
+wire [2:0] _SD_CS;
+wire [2:0] _SD_MOSI;
+wire [2:0] _SD_SCK;
+wire [2:0] _driveLED;
+
+always_comb 
+begin
+	hblank 		<= _hblank[cpu_type];
+	vblank 		<= _vblank[cpu_type];
+	hs 		 	<= _hs[cpu_type];
+	vs				<= _vs[cpu_type];
+	r 				<= _r[cpu_type][1:0];
+	g 				<= _g[cpu_type][1:0];
+	b				<= _b[cpu_type][1:0];
+	CE_PIXEL		<= _CE_PIXEL[cpu_type];
+	SD_CS			<= _SD_CS[cpu_type];
+	SD_MOSI		<= _SD_MOSI[cpu_type];
+	SD_SCK		<= _SD_SCK[cpu_type];
+	driveLED 	<= _driveLED[cpu_type];
+end
 
 MicrocomputerZ80CPM MicrocomputerZ80CPM
 (
-	.N_RESET(~reset),
-	.clk(CLK_50M),
-	.R(r),
-	.G(g),
-	.B(b),
-	.HS(hs),
-	.VS(vs),
-	.hBlank(hblank),
-	.vBlank(vblank),
-	.cepix(CE_PIXEL),
+	.N_RESET(~reset & cpu_type == cpuZ80CPM),
+	.clk(cpu_type == cpuZ80CPM ? CLK_50M : 0),
+	.R(_r[0][1:0]),
+	.G(_g[0][1:0]),
+	.B(_b[0][1:0]),
+	.HS(_hs[0]),
+	.VS(_vs[0]),
+	.hBlank(_hblank[0]),
+	.vBlank(_vblank[0]),
+	.cepix(_CE_PIXEL[0]),
 	.ps2Clk(PS2_CLK),
 	.ps2Data(PS2_DAT),
-	.sdCS(SD_CS),
-	.sdMOSI(SD_MOSI),
+	.sdCS(_SD_CS[0]),
+	.sdMOSI(_SD_MOSI[0]),
 	.sdMISO(SD_MISO),
-	.sdSCLK(SD_SCK),
-	.driveLED(driveLED)
+	.sdSCLK(_SD_SCK[0]),
+	.driveLED(_driveLED[0])
 );
- 
+
+Microcomputer6502Basic Microcomputer6502Basic
+(
+	.N_RESET(~reset & cpu_type == cpu6502Basic),
+	.clk(cpu_type == cpu6502Basic ? CLK_50M : 0),
+	.R(_r[1][1:0]),
+	.G(_g[1][1:0]),
+	.B(_b[1][1:0]),
+	.HS(_hs[1]),
+	.VS(_vs[1]),
+	.hBlank(_hblank[1]),
+	.vBlank(_vblank[1]),
+	.cepix(_CE_PIXEL[1]),
+	.ps2Clk(PS2_CLK),
+	.ps2Data(PS2_DAT),
+	.sdCS(_SD_CS[1]),
+	.sdMOSI(_SD_MOSI[1]),
+	.sdMISO(SD_MISO),
+	.sdSCLK(_SD_SCK[1]),
+	.driveLED(_driveLED[1])
+);
+
+//Reset is not working (even on the original Grant's 6809)
+Microcomputer6809Basic Microcomputer6809Basic
+(
+	.N_RESET(~reset & cpu_type == cpu6809Basic),
+	.clk(cpu_type == cpu6809Basic ? CLK_50M : 0),
+	.R(_r[2][1:0]),
+	.G(_g[2][1:0]),
+	.B(_b[2][1:0]),
+	.HS(_hs[2]),
+	.VS(_vs[2]),
+	.hBlank(_hblank[2]),
+	.vBlank(_vblank[2]),
+	.cepix(_CE_PIXEL[2]),
+	.ps2Clk(PS2_CLK),
+	.ps2Data(PS2_DAT),
+	.sdCS(_SD_CS[2]),
+	.sdMOSI(_SD_MOSI[2]),
+	.sdMISO(SD_MISO),
+	.sdSCLK(_SD_SCK[2]),
+	.driveLED(_driveLED[2])
+);
+
 video_cleaner video_cleaner
 (
 	.clk_vid(CLK_VIDEO),

README.md

@@ -1,8 +1,10 @@
 MISTer MultiComp 
 ================
 
-Port of Grant Searle's MultiComp to the MiSTer
+Port of Grant Searle's MultiComp to the MiSTer. 
+The MiSTer OSD while allow the access to three machines:
 
+## Z80 CP/M - SD card needed in I/O Board: 
 For convenience you can use the Multicomp FPGA - CP/M Demo Disk from Obsolescence Guaranteed:
 http://obsolescence.wixsite.com/obsolescence/multicomp-fpga-cpm-demo-disk
 
@@ -12,6 +14,19 @@ https://github.com/MiSTer-devel/Main_MiSTer/wiki/IO-Board
 Using CP/M - from Grant Searle website:
 http://searle.hostei.com/grant/Multicomp/cpm/fpgaCPM.html#UsingTheMachine
 
+## 6502 Basic - No SD card support (No CSAVE/CLOAD):
+END, FOR, NEXT, DATA, INPUT, DIM, READ, LET, GOTO, RUN, IF, RESTORE, GOSUB, RETURN, REM, STOP, ON, NULL, WAIT, DEF, POKE, PRINT,
+CONT, LIST, CLEAR, NEW, TAB(, TO, FN, SPC(, THEN, NOT, STEP, SGN, INT, ABS, USR, FRE, POS, SQR, RND, LOG, EXP, COS, SIN, TAN, ATN,
+PEEK, LEN, STR$, VAL, ASC, CHR$, LEFT$, RIGHT$, MID$, +, -, *, /, ^, AND, OR, >, +, <
+
+## 6809 Basic - No SD card support(No CSAVE/CLOAD):
+FOR, GO, REM, ELSE, IF, DATA, PRINT, ON GOSUB, ON GOTO, INPUT, LINE INPUT, END, NEXT, DIM, READ, RUN, RESTORE, RETURN, STOP, POKE,
+CONT, LIST, CLEAR, NEW, EXEC, TAB, TO, SUB, THEN, NOT, STEP, +, -, *, /, ^, AND, OR, >, =, <, DEL, DEF, LET, RENUM, FN, &, &H, TRON,
+TROFF, EDIT, SGN, INT, ABS, USR, RND, SIN, PEEK, LEN, STR$, VAL, ASC, CHR$, LEFT$, RIGHT$, MID$, INKEY$, MEM, ATN, COS, TAN, EXP, FIX,
+LOG, SQR, HEX$, VARPTR, INSTR, STRING$, MID$ (MODIFICATION), POS
+
+http://searle.hostei.com/grant/Multicomp/#BASICKeywords
+
 ## License
 
 __Software and VHDL project download link__
@@ -21,7 +36,7 @@ copyright owners of ROM contents are respectfully acknowledged.  Use of the
 contents of any file within your own projects is permitted freely, but any
 publishing of material containing whole or part of any file distributed
 here, or derived from the work that I have done here will contain an
-acknowledgement back to myself, Grant Searle, and a link back to this page.
+acknowledgment back to myself, Grant Searle, and a link back to this page.
 Any file published or distributed that contains all or part of any file
 arom this page must be made available free of charge.
 
@@ -32,4 +47,4 @@ Grant Searle
 [Grant's MULTICOMP pick and mix computer](http://searle.hostei.com/grant/Multicomp/index.html)
 
 ## Note
-For now only the Z80 CP/M version of the MulitiComp is working. Other CPU/OS will be implemented in the future.
+The 6809 Basic is not resetting  properly. This issue is present in the original Grant Searle's MultiComp project

clean.bat

@@ -31,7 +31,6 @@ del /s *.bsf
 del /s *.f
 del /s *.sopcinfo
 del /s *.xml
-del *.cdf
 del *.rpt
 del /s new_rtl_netlist
 del /s old_rtl_netlist

jtag.cdf

@@ -0,0 +1,13 @@
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
+	P ActionCode(Cfg)
+		Device PartName(5CSEBA6U23I7) Path("output_files/") File("MultiComp.sof") MfrSpec(OpMask(1));
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;