remove the broken delay in sd_controller

This commit is contained in:
Fred VanEijk
2024-12-08 09:58:13 -05:00
parent 1efd36aa14
commit 5032cb28ce
3 changed files with 3 additions and 5 deletions

View File

@@ -101,7 +101,7 @@ use ieee.std_logic_unsigned.all;
entity sd_controller is
generic (
constant CLKEDGE_DIVIDER : integer := 200 -- 50MHz / 200 gives edges at 250kHz ie output
constant CLKEDGE_DIVIDER : integer := 100 -- 50MHz / 100 gives edges at 500kHz ie output
-- or sdSCLK of 250kHz to be used during init phase
);
port (
@@ -302,9 +302,7 @@ begin
state <= cmd0;
else
bit_counter := bit_counter - 1;
if clkCount = (CLKEDGE_DIVIDER - 1) then -- Only toggle clock at divided rate
sclk_sig <= not sclk_sig;
end if;
sclk_sig <= not sclk_sig;
end if;
when cmd0 =>

View File

@@ -1 +1 @@
`define BUILD_DATE "241207"
`define BUILD_DATE "241208"

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