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https://github.com/MiSTer-devel/MultiComp_MiSTer.git
synced 2026-04-19 03:04:38 +00:00
remove the broken delay in sd_controller
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@@ -101,7 +101,7 @@ use ieee.std_logic_unsigned.all;
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entity sd_controller is
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generic (
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constant CLKEDGE_DIVIDER : integer := 200 -- 50MHz / 200 gives edges at 250kHz ie output
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constant CLKEDGE_DIVIDER : integer := 100 -- 50MHz / 100 gives edges at 500kHz ie output
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-- or sdSCLK of 250kHz to be used during init phase
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);
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port (
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@@ -302,9 +302,7 @@ begin
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state <= cmd0;
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else
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bit_counter := bit_counter - 1;
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if clkCount = (CLKEDGE_DIVIDER - 1) then -- Only toggle clock at divided rate
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sclk_sig <= not sclk_sig;
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end if;
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sclk_sig <= not sclk_sig;
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end if;
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when cmd0 =>
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@@ -1 +1 @@
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`define BUILD_DATE "241207"
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`define BUILD_DATE "241208"
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BIN
releases/MultiComp_20241208.rbf
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BIN
releases/MultiComp_20241208.rbf
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