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fixed serial via uart

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Mario Smit
2020-11-21 21:28:30 +01:00
parent 5df985e5c1
commit 4da3af2feb
7 changed files with 100 additions and 30 deletions
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6
Microcomputer6809Basic.vhd
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@@ -185,9 +185,9 @@ port map (
io2 : entity work.bufferedUART
port map(
clk => clk,
n_wr => n_interface1CS or cpuClock or n_WR,
n_rd => n_interface1CS or cpuClock or (not n_WR),
n_int => n_int1,
n_wr => n_interface2CS or cpuClock or n_WR,
n_rd => n_interface2CS or cpuClock or (not n_WR),
n_int => n_int2,
regSel => cpuAddress(0),
dataIn => cpuDataOut,
dataOut => interface2DataOut,