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Rewrite to use latest version of open source scaler and standard sys framework.

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This commit is contained in:
sorgelig
2019-05-24 00:11:49 +08:00
parent be8bc67273
commit d5bfe923c3
34 changed files with 5009 additions and 2152 deletions
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2
ddram.sv
View File

@@ -101,7 +101,7 @@ begin
old_we <= we;
busy <= 0;
if(~old_we && we)
if(~old_we && we && addr[28:26])
begin
ram_cache[{addr[2:0], 3'b000} +:8] <= din;
ram_address <= addr;

5
files.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name QIP_FILE sdram.qip
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name VERILOG_FILE lfsr.v
set_global_assignment -name SYSTEMVERILOG_FILE cos.sv
set_global_assignment -name SYSTEMVERILOG_FILE menu.sv

12
menu.qpf
View File

@@ -1,12 +1,2 @@
#
# please keep this file read-only!
# Quartus changes this file everytime revision is switched,
# and it will be marked as changed with every commit.
#
QUARTUS_VERSION = "16.1"
DATE = "23:13:02 April 27, 2017"
# Revisions
QUARTUS_VERSION = "17.0"
PROJECT_REVISION = "menu"

367
menu.qsf
View File

@@ -1,48 +1,25 @@
# -------------------------------------------------------------------------- #
# --------------------------------------------------------------------------
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
# MiSTer project
#
# -------------------------------------------------------------------------- #
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
# --------------------------------------------------------------------------
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
@@ -50,318 +27,28 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# USER PORT
#============================================================
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name VERILOG_FILE lfsr.v
set_global_assignment -name SYSTEMVERILOG_FILE cos.sv
set_global_assignment -name SYSTEMVERILOG_FILE menu.sv
source sys/sys.tcl
source files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

69
menu.srf
View File

@@ -1,59 +1,28 @@
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(536): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 127 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Design contains combinational loop of 127 nodes. Estimating the delays through the loop." { } { } 0 332081 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cyclonev_pll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

47
menu.sv
View File

@@ -1,7 +1,7 @@
//============================================================================
//
// Menu for MiSTer.
// Copyright (C) 2017,2018 Sorgelig
// Copyright (C) 2017-2019 Sorgelig
//
//
// This program is free software; you can redistribute it and/or modify it
@@ -27,10 +27,9 @@ module emu
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
output RESET_OUT,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
inout [45:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
@@ -43,13 +42,14 @@ module emu
output [7:0] VIDEO_ARX,
output [7:0] VIDEO_ARY,
input PAL,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output LED_USER, // 1 - ON, 0 - OFF.
@@ -61,9 +61,11 @@ module emu
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
input TAPE_IN,
//ADC
inout [3:0] ADC_BUS,
// SD-SPI
output SD_SCK,
@@ -72,9 +74,6 @@ module emu
output SD_CS,
input SD_CD,
output [2:0] PATTERN,
output reg DIM,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
@@ -100,23 +99,37 @@ module emu
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..5 - USR1..USR4
// Set USER_OUT to 1 to read from USER_IN.
input [5:0] USER_IN,
output [5:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign DDRAM_CLK = clk_sys;
assign CE_PIXEL = ce_pix;
assign VIDEO_ARX = 16;
assign VIDEO_ARY = 9;
assign VGA_SL = 0;
assign VGA_F1 = 0;
assign VIDEO_ARX = 0;
assign VIDEO_ARY = 0;
assign AUDIO_S = 0;
assign AUDIO_L = 0;
@@ -157,9 +170,7 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.ps2_key(ps2_key)
);
assign RESET_OUT = buttons[1];
assign PATTERN = status[3:1];
/*
always @(posedge CLK_50M) begin
integer sec, to;
reg old_stb;
@@ -175,7 +186,7 @@ always @(posedge CLK_50M) begin
old_stb <= ps2_key[10];
if((old_stb ^ ps2_key[10]) || status[0] || buttons[1]) to <= 0;
end
*/
//////////////////// CLOCKS ///////////////////
wire locked, clk_sys;
@@ -235,6 +246,8 @@ end
///////////////////// VIDEO ///////////////////
wire PAL = status[4];
reg [9:0] hc;
reg [9:0] vc;
reg [9:0] vvc;

2
menu_Q13.qpf Normal file
View File

@@ -0,0 +1,2 @@
QUARTUS_VERSION = "13.1"
PROJECT_REVISION = "menu_Q13"

45
menu_Q13.qsf Normal file
View File

@@ -0,0 +1,45 @@
# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name SEED 1
source sys/sys.tcl
set_global_assignment -name QIP_FILE files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

26
menu_Q13.srf Normal file
View File

@@ -0,0 +1,26 @@
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL information at MC6845.v(280): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(601): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Dummy RLC values generated in IBIS model files for device 5CSEBA6 with package UFBGA and pin count 672" { } { } 0 205009 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(10): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(9): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(29): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Timing characteristics of device 5CSEBA6U23I7 are preliminary" { } { } 0 334000 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|rom_map_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

2
sdram.qip Normal file
View File

@@ -0,0 +1,2 @@
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ]

13
sdram.sdc Normal file
View File

@@ -0,0 +1,13 @@
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

2399
sys/ascal.vhd Normal file
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File diff suppressed because it is too large Load Diff

157
sys/audio_out.v Normal file
View File

@@ -0,0 +1,157 @@
module audio_out
#(
parameter CLK_RATE = 50000000
)
(
input reset,
input clk,
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [15:0] left_in,
input [15:0] right_in,
// I2S
output i2s_bclk,
output i2s_lrclk,
output i2s_data,
// SPDIF
output spdif,
// Sigma-Delta DAC
output dac_l,
output dac_r
);
localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce <= 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce <= 1;
end
end
reg i2s_ce;
always @(posedge clk) begin
reg div;
i2s_ce <= 0;
if(mclk_ce) begin
div <= ~div;
i2s_ce <= div;
end
end
reg lpf_ce;
always @(posedge clk) begin
integer div;
lpf_ce <= 0;
if(mclk_ce) begin
div <= div + 1;
if(div == FILTER_DIV) begin
div <= 0;
lpf_ce <= 1;
end
end
end
i2s i2s
(
.reset(reset),
.clk(clk),
.ce(i2s_ce),
.sclk(i2s_bclk),
.lrclk(i2s_lrclk),
.sdata(i2s_data),
.left_chan(al),
.right_chan(ar)
);
spdif toslink
(
.rst_i(reset),
.clk_i(clk),
.bit_out_en_i(mclk_ce),
.sample_i({ar,al}),
.spdif_o(spdif)
);
sigma_delta_dac #(15) sd_l
(
.CLK(clk),
.RESET(reset),
.DACin({~al[15], al[14:0]}),
.DACout(dac_l)
);
sigma_delta_dac #(15) sd_r
(
.CLK(clk),
.RESET(reset),
.DACin({~ar[15], ar[14:0]}),
.DACout(dac_r)
);
wire [15:0] al, ar;
lpf_aud lpf_l
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(left_in),
.ODATA(al)
);
lpf_aud lpf_r
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(right_in),
.ODATA(ar)
);
endmodule
module lpf_aud
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

61
sys/hps_io.v
View File

@@ -33,17 +33,17 @@
module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
(
input clk_sys,
inout [44:0] HPS_BUS,
inout [45:0] HPS_BUS,
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
output reg [15:0] joystick_0,
output reg [15:0] joystick_1,
output reg [15:0] joystick_2,
output reg [15:0] joystick_3,
output reg [15:0] joystick_4,
output reg [15:0] joystick_5,
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [31:0] joystick_5,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
@@ -57,6 +57,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
output reg [31:0] status,
input [31:0] status_in,
input status_set,
input [15:0] status_menumask,
//toggle to force notify of video mode change
input new_vmode,
@@ -173,15 +174,18 @@ wire de = HPS_BUS[40];
wire hs = HPS_BUS[39];
wire vs = HPS_BUS[38];
wire vs_hdmi = HPS_BUS[44];
wire f1 = HPS_BUS[45];
reg [31:0] vid_hcnt = 0;
reg [31:0] vid_vcnt = 0;
reg [7:0] vid_nres = 0;
reg [1:0] vid_int = 0;
integer hcnt;
always @(posedge clk_vid) begin
integer vcnt;
reg old_vs= 0, old_de = 0, old_vmode = 0;
reg [3:0] resto = 0;
reg calch = 0;
if(ce_pix) begin
@@ -193,15 +197,22 @@ always @(posedge clk_vid) begin
if(old_de & ~de) calch <= 0;
if(old_vs & ~vs) begin
if(hcnt && vcnt) begin
old_vmode <= new_vmode;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
vid_int <= {vid_int[0],f1};
if(~f1) begin
if(hcnt && vcnt) begin
old_vmode <= new_vmode;
//report new resolution after timeout
if(resto) resto <= resto + 1'd1;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
if(&resto) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
vcnt <= 0;
hcnt <= 0;
calch <= 1;
end
vcnt <= 0;
hcnt <= 0;
calch <= 1;
end
end
end
@@ -321,6 +332,7 @@ always@(posedge clk_sys) begin
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
'h2F: io_dout <= 1;
endcase
sd_buff_addr <= 0;
@@ -330,13 +342,13 @@ always@(posedge clk_sys) begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h02: joystick_0 <= io_din;
'h03: joystick_1 <= io_din;
'h10: joystick_2 <= io_din;
'h11: joystick_3 <= io_din;
'h12: joystick_4 <= io_din;
'h13: joystick_5 <= io_din;
'h01: cfg <= io_din[7:0];
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
// store incoming ps2 mouse bytes
'h04: begin
@@ -432,7 +444,7 @@ always@(posedge clk_sys) begin
//Video res.
'h23: case(byte_cnt)
1: io_dout <= vid_nres;
1: io_dout <= {|vid_int, vid_nres};
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
@@ -458,6 +470,9 @@ always@(posedge clk_sys) begin
1: io_dout <= status_req[15:0];
2: io_dout <= status_req[31:16];
endcase
//menu mask
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
endcase
end
end

22
sys/hq2x.sv
View File

@@ -15,12 +15,15 @@
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input ce_in,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input ce_out,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel
@@ -129,6 +132,14 @@ hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_ou
.wren(wrout_en)
);
always @(posedge clk) begin
if(ce_out) begin
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
end
end
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs;
@@ -139,10 +150,7 @@ always @(posedge clk) begin
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(ce_in) begin
if(~&offs) begin
if (cyc == 1) begin
@@ -168,6 +176,7 @@ always @(posedge clk) begin
end
end
pattern <= new_pattern;
if(cyc==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
@@ -194,9 +203,6 @@ always @(posedge clk) begin
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
end

190
sys/i2s.v
View File

@@ -1,136 +1,54 @@
module i2s
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_DW = 16,
parameter AUDIO_RATE = 96000
)
(
input reset,
input clk_sys,
input half_rate,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
reg lpf_ce;
wire [AUDIO_DW-1:0] al, ar;
lpf_i2s lpf_l
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(left_chan),
.ODATA(al)
);
lpf_i2s lpf_r
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(right_chan),
.ODATA(ar)
);
always @(posedge clk_sys) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg [7:0] bit_cnt;
reg skip = 0;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
reg msclk;
reg ce;
lpf_ce <= 0;
if (reset) begin
count_q <= 0;
error_q <= 0;
ce <= 0;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
sclk <= msclk;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) begin
msclk <= ~msclk;
if(msclk) begin
skip <= ~skip;
if(skip) lpf_ce <= 1;
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= al;
right <= ar;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
end
endmodule
module lpf_i2s
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule
module i2s
#(
parameter AUDIO_DW = 16
)
(
input reset,
input clk,
input ce,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
always @(posedge clk) begin
reg [7:0] bit_cnt;
reg msclk;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
if (reset) begin
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else begin
sclk <= msclk;
if(ce) begin
msclk <= ~msclk;
if(msclk) begin
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= left_chan;
right <= right_chan;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
endmodule

162
sys/ltc2308.sv Normal file
View File

@@ -0,0 +1,162 @@
//============================================================================
//
// LTC2308 controller
// Copyright (C) 2019 Sorgelig
//
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
// NUM_CH 1..8
// Sampling rate = ADC_RATE/NUM_CH
// ADC_RATE max is ~500KHz
// CLK_RATE max is ~80MHz
module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000)
(
input reset,
input clk,
inout [3:0] ADC_BUS,
output reg dout_sync, // toggle with every ADC round
output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned)
);
localparam TCONV = CLK_RATE/625000;
reg sck;
wire sdo = cfg[5];
assign ADC_BUS[3] = sck;
wire sdi = ADC_BUS[2];
assign ADC_BUS[1] = sdo;
assign ADC_BUS[0] = convst;
reg convst;
reg [5:0] cfg;
reg [31:0] sum;
wire [31:0] next_sum = sum + ADC_RATE;
reg [2:0] pin;
wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1);
always @(posedge clk) begin
reg [7:0] tconv;
reg [3:0] bitcnt;
reg [10:0] adcin;
convst <= 0;
if(reset) begin
sum <= 0;
tconv <= 0;
bitcnt <= 0;
sck <= 0;
cfg <= 0;
dout <= 0;
pin <= NUM_CH[2:0]-1'd1;
end
else begin
sum <= next_sum;
if(next_sum >= CLK_RATE) begin
sum <= next_sum - CLK_RATE;
tconv <= TCONV[7:0];
convst <= 1;
bitcnt <= 12;
cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0};
if(!next_pin) dout_sync <= ~dout_sync;
end
if(tconv) tconv <= tconv - 1'd1;
else if(bitcnt) begin
sck <= ~sck;
if(sck) cfg <= cfg<<1;
else begin
adcin <= {adcin[9:0],sdi};
bitcnt <= bitcnt - 1'd1;
if(bitcnt == 1) begin
dout[pin*12 +:12] <= {adcin,sdi};
pin <= next_pin;
end
end
end
else sck <= 0;
end
end
endmodule
module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
(
input reset,
input clk,
inout [3:0] ADC_BUS,
output reg dout,
output active
);
wire [11:0] adc_data;
wire adc_sync;
ltc2308 #(1, ADC_RATE, CLK_RATE) adc
(
.reset(reset),
.clk(clk),
.ADC_BUS(ADC_BUS),
.dout(adc_data),
.dout_sync(adc_sync)
);
always @(posedge clk) begin
reg [13:0] data1,data2,data3,data4, sum;
reg adc_sync_d;
adc_sync_d<=adc_sync;
if(adc_sync_d ^ adc_sync) begin
data1 <= data2;
data2 <= data3;
data3 <= data4;
data4 <= adc_data;
sum <= data1+data2+data3+data4;
if(sum[13:2]<HIST_LOW) dout <= 0;
if(sum[13:2]>HIST_HIGH) dout <= 1;
end
end
assign active = |act;
reg [1:0] act;
always @(posedge clk) begin
reg [31:0] onesec;
reg old_dout;
onesec <= onesec + 1;
if(onesec>CLK_RATE) begin
onesec <= 0;
if(act) act <= act - 1'd1;
end
old_dout <= dout;
if(old_dout ^ dout) act <= 2;
end
endmodule

5
sys/osd.v
View File

@@ -13,7 +13,8 @@ module osd
input [23:0] din,
output [23:0] dout,
input de_in,
output reg de_out
output reg de_out,
output osd_status
);
parameter OSD_COLOR = 3'd4;
@@ -23,6 +24,8 @@ parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
assign osd_status = 1;
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096+1024];

182
sys/pattern_vg.v
View File

@@ -1,182 +0,0 @@
module pattern_vg
#(
parameter B=8, // number of bits per channel
X_BITS=13,
Y_BITS=13
)
(
input reset, clk_in,
input [X_BITS-1:0] x,
input [Y_BITS-1:0] y,
input vs_in, hs_in, de_in,
output reg vs_out, hs_out, de_out,
output reg [B-1:0] r, g, b,
input [X_BITS-1:0] width,
input [Y_BITS-1:0] height,
input [2:0] pattern
);
reg [Y_BITS-1:0] ramp_y;
reg [X_BITS-1:0] ramp_x;
reg [X_BITS+9:0] cosx;
wire [63:0] rnd;
reg [5:0] rnd_reg;
wire [5:0] rnd_c = {rnd[0],rnd[1],rnd[2],rnd[2],rnd[2],rnd[2]};
wire [7:0] cos_out;
reg [5:0] cos_g;
lfsr random(rnd);
cos cos(cosx[9:0], cos_out);
wire [7:0] noise = (cos_g >= rnd_reg) ? {cos_g - rnd_reg, 2'b00} : 8'd0;
reg [9:0] vvc = 0;
always @(posedge clk_in) cosx <= vvc + ({y,10'd0}/height);
always @(posedge clk_in) begin
reg [X_BITS-1:0] acc_x,step_x,add_x;
reg [Y_BITS-1:0] acc_y,step_y,add_y;
reg old_hs;
if(vs_in) begin
add_x <= pattern[1] ? 10'd14 : 10'd255;
add_y <= pattern[1] ? 10'd255 : 10'd14;
end
ramp_x <= step_x;
ramp_y <= step_y;
acc_x = acc_x + add_x;
if(acc_x >= width) begin
acc_x = acc_x - width;
step_x <= step_x + 1'd1;
end
if(!x) begin
acc_x = 0;
step_x <= 0;
ramp_x <= 0;
end
old_hs <= hs_in;
if(old_hs & ~hs_in) begin
acc_y = acc_y + add_y;
if(acc_y >= height) begin
acc_y = acc_y - height;
step_y <= step_y + 1'd1;
end
if(!y) begin
acc_y = 0;
step_y <= 0;
ramp_y <= 0;
end
end
end
wire [X_BITS-1:0] inv_ramp_x = 8'd13 - ramp_x;
wire [Y_BITS-1:0] inv_ramp_y = 8'd13 - ramp_y;
always @(posedge clk_in) begin
if(!x && !y && de_in) vvc <= vvc + 9'd6;
if(!x) cos_g <= {1'b1, cos_out[7:3]};
if(x[1:0] == 0) rnd_reg <= rnd_c;
vs_out <= vs_in;
hs_out <= hs_in;
de_out <= de_in;
case(pattern)
// TV noise
0: if(&x[1:0]) begin
r <= noise;
g <= noise;
b <= noise;
end
// black
1: begin
r <= 0;
g <= 0;
b <= 0;
end
// border
2: if (de_in && ((y == 12'b0) || (x == 12'b0) || (x == width - 1) || (y == height - 1)))
begin
r <= 8'hFF;
g <= 8'hFF;
b <= 8'hFF;
end
else
if (de_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == width - 1 - 20) || (y == height - 1 - 20)))
begin
r <= 8'h80;
g <= 8'h80;
b <= 8'h80;
end
else
begin
r <= 0;
g <= 0;
b <= 0;
end
// stripes
3: if ((de_in) && y[2])
begin
r <= 8'h80;
g <= 8'h80;
b <= 8'h80;
end
else
begin
r <= 8'hC0;
g <= 8'hC0;
b <= 8'hC0;
end
4: begin
if(~ramp_y[0]) begin
r <= ramp_y[1] ? 8'h00 : ramp_x[7:0];
g <= ramp_y[2] ? 8'h00 : ramp_x[7:0];
b <= ramp_y[3] ? 8'h00 : ramp_x[7:0];
end
else begin
r <= inv_ramp_y[1] ? 8'h00 : ~ramp_x[7:0];
g <= inv_ramp_y[2] ? 8'h00 : ~ramp_x[7:0];
b <= inv_ramp_y[3] ? 8'h00 : ~ramp_x[7:0];
end
end
5: begin
r <= ramp_y[1] ? 8'h00 : ~ramp_x[7:0];
g <= ramp_y[2] ? 8'h00 : ~ramp_x[7:0];
b <= ramp_y[3] ? 8'h00 : ~ramp_x[7:0];
end
6: begin
if(~ramp_x[0]) begin
r <= ramp_x[1] ? 8'h00 : ramp_y[7:0];
g <= ramp_x[2] ? 8'h00 : ramp_y[7:0];
b <= ramp_x[3] ? 8'h00 : ramp_y[7:0];
end
else begin
r <= inv_ramp_x[1] ? 8'h00 : ~ramp_y[7:0];
g <= inv_ramp_x[2] ? 8'h00 : ~ramp_y[7:0];
b <= inv_ramp_x[3] ? 8'h00 : ~ramp_y[7:0];
end
end
7: begin
r <= ramp_x[1] ? 8'h00 : ~ramp_y[7:0];
g <= ramp_x[2] ? 8'h00 : ~ramp_y[7:0];
b <= ramp_x[3] ? 8'h00 : ~ramp_y[7:0];
end
endcase
end
endmodule

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

433
sys/pll_hdmi_adj.vhd Normal file
View File

@@ -0,0 +1,433 @@
--------------------------------------------------------------------------------
-- HDMI PLL Adjust
--------------------------------------------------------------------------------
-- Changes the HDMI PLL frequency according to the scaler suggestions.
--------------------------------------------
-- LLTUNE :
-- 0 : Input Display Enable
-- 1 : Input Vsync
-- 2 : Input Interlaced mode
-- 3 : Input Interlaced field
-- 4 : Output Image frame
-- 5 :
-- 6 : Input clock
-- 7 : Output clock
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY pll_hdmi_adj IS
PORT (
-- Scaler
llena : IN std_logic; -- 0=Disabled 1=Enabled
lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler
locked : OUT std_logic;
-- Signals from reconfig commands
i_waitrequest : OUT std_logic;
i_write : IN std_logic;
i_address : IN unsigned(5 DOWNTO 0);
i_writedata : IN unsigned(31 DOWNTO 0);
-- Outputs to PLL_HDMI_CFG
o_waitrequest : IN std_logic;
o_write : OUT std_logic;
o_address : OUT unsigned(5 DOWNTO 0);
o_writedata : OUT unsigned(31 DOWNTO 0);
------------------------------------
clk : IN std_logic;
reset_na : IN std_logic
);
BEGIN
END ENTITY pll_hdmi_adj;
--##############################################################################
ARCHITECTURE rtl OF pll_hdmi_adj IS
SIGNAL i_clk,i_de,i_de2,i_vss,i_vss2,i_vss_delay,i_ce : std_logic;
SIGNAL i_linecpt,i_line : natural RANGE 0 TO 2**12-1;
SIGNAL i_delay : natural RANGE 0 TO 2**14-1;
SIGNAL pwrite : std_logic;
SIGNAL paddress : unsigned(5 DOWNTO 0);
SIGNAL pdata : unsigned(31 DOWNTO 0);
TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
SIGNAL state : enum_state;
SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
SIGNAL mul : unsigned(15 DOWNTO 0);
SIGNAL sign,sign_pre : std_logic;
SIGNAL expand : boolean;
SIGNAL up,modo,phm,dir : std_logic;
SIGNAL cpt : natural RANGE 0 TO 3;
SIGNAL col : natural RANGE 0 TO 15;
SIGNAL icpt,ocpt,o2cpt,ssh,ofsize,ifsize : natural RANGE 0 TO 2**24-1;
SIGNAL ivss,ivss2,itog : std_logic;
SIGNAL ovss,ovss2,otog : std_logic;
SIGNAL sync,pulse,los,lop : std_logic;
SIGNAL osize,offset,osizep,offsetp : signed(23 DOWNTO 0);
SIGNAL logcpt : natural RANGE 0 TO 31;
SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
BEGIN
----------------------------------------------------------------------------
-- 4 lines delay to input
i_vss<=lltune(0);
i_de <=lltune(1);
i_ce <=lltune(5);
i_clk<=lltune(6);
Delay:PROCESS(i_clk) IS
BEGIN
IF rising_edge(i_clk) THEN
IF i_ce='1' THEN
-- Measure input line time.
i_de2<=i_de;
IF i_de='1' AND i_de2='0' THEN
i_linecpt<=0;
IF i_vss='1' THEN
i_line<=i_linecpt;
END IF;
ELSE
i_linecpt<=i_linecpt+1;
END IF;
-- Delay 4 lines
i_vss2<=i_vss;
IF i_vss/=i_vss2 THEN
i_delay<=0;
ELSIF i_delay=i_line * 4 THEN
i_vss_delay<=i_vss;
ELSE
i_delay<=i_delay+1;
END IF;
END IF;
END IF;
END PROCESS Delay;
----------------------------------------------------------------------------
-- Sample image sizes
Sampler:PROCESS(clk,reset_na) IS
BEGIN
IF reset_na='0' THEN
--pragma synthesis_off
otog<='0';
itog<='0';
ivss<='0';
ivss2<='0';
ovss<='0';
ovss2<='0';
--pragma synthesis_on
ELSIF rising_edge(clk) THEN
-- Clock domain crossing
ivss<=i_vss_delay; -- <ASYNC>
ivss2<=ivss;
ovss<=lltune(4); -- <ASYNC>
ovss2<=ovss;
otog<=otog XOR (ovss AND NOT ovss2);
-- Measure output frame time
IF ovss='1' AND ovss2='0' AND otog='1' THEN
ocpt<=0;
osizep<=to_signed(ocpt,24);
ELSE
ocpt<=ocpt+1;
END IF;
IF ovss='0' AND ovss2='1' AND otog='0' THEN
o2cpt<=0;
ELSE
o2cpt<=o2cpt+1;
END IF;
-- Measure output image time
IF ovss='0' AND ovss2='1' AND otog='0' THEN
ofsize<=ocpt;
END IF;
itog<=itog XOR (ivss AND NOT ivss2);
-- Measure input frame time
IF ivss='1' AND ivss2='0' AND itog='1' THEN
icpt<=0;
osize<=osizep;
udiff<=integer(to_integer(osizep)) - integer(icpt);
sync<='1';
ELSE
icpt<=icpt+1;
sync<='0';
END IF;
-- Measure input image time
IF ivss='0' AND ivss2='1' AND itog='0' THEN
ifsize<=icpt;
END IF;
expand<=(ofsize>=ifsize);
-- IN | ######### | EXPAND = 1
-- OUT | ############# |
-- IN | ######### | EXPAND = 0
-- OUT | ###### |
IF expand THEN
IF ivss='1' AND ivss2='0' AND itog='1' THEN
offset<=to_signed(ocpt,24);
END IF;
ELSE
IF ivss='0' AND ivss2='1' AND itog='0' THEN
offset<=to_signed(o2cpt,24);
END IF;
END IF;
--------------------------------------------
pulse<='0';
IF sync='1' THEN
logcpt<=0;
ssh<=to_integer(osize);
los<='0';
lop<='0';
ELSIF logcpt<24 THEN
-- Frequency difference
IF udiff>0 AND ssh<udiff AND los='0' THEN
tune_freq<='0' & to_unsigned(logcpt,5);
los<='1';
ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
tune_freq<='1' & to_unsigned(logcpt,5);
los<='1';
END IF;
-- Phase difference
IF offset<osize/2 AND ssh<offset AND lop='0' THEN
tune_phase<='0' & to_unsigned(logcpt,5);
lop<='1';
ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
tune_phase<='1' & to_unsigned(logcpt,5);
lop<='1';
END IF;
ssh<=ssh/2;
logcpt<=logcpt+1;
ELSIF logcpt=24 THEN
pulse<='1';
ssh<=ssh/2;
logcpt<=logcpt+1;
END IF;
END IF;
END PROCESS Sampler;
----------------------------------------------------------------------------
-- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
-- 000100 : M counter
-- 000111 : M counter Fractional Value K
Comb:PROCESS(i_write,i_address,
i_writedata,pwrite,paddress,pdata) IS
BEGIN
IF i_write='1' THEN
o_write <=i_write;
o_address <=i_address;
o_writedata <=i_writedata;
ELSE
o_write <=pwrite;
o_address <=paddress;
o_writedata<=pdata;
END IF;
END PROCESS Comb;
i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
----------------------------------------------------------------------------
Schmurtz:PROCESS(clk,reset_na) IS
VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
VARIABLE diff_v : unsigned(40 DOWNTO 0);
VARIABLE mulco : unsigned(15 DOWNTO 0);
VARIABLE up_v,sign_v : std_logic;
BEGIN
IF reset_na='0' THEN
modo<='0';
state<=sIDLE;
ELSIF rising_edge(clk) THEN
------------------------------------------------------
-- Snoop accesses to PLL reconfiguration
IF i_address="000100" AND i_write='1' THEN
mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mul<=i_writedata(15 DOWNTO 0);
modo<='1';
END IF;
IF i_address="000111" AND i_write='1' THEN
mfrac (31 DOWNTO 0)<=i_writedata;
mfrac_ref(31 DOWNTO 0)<=i_writedata;
mfrac_mem(31 DOWNTO 0)<=i_writedata;
modo<='1';
END IF;
------------------------------------------------------
-- Tuning
off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
--IF off_v<8 THEN off_v:=8; END IF;
--IF ofp_v<7 THEN ofp_v:=7; END IF;
IF off_v<4 THEN off_v:=4; END IF;
IF ofp_v<4 THEN ofp_v:=4; END IF;
IF off_v>=18 AND ofp_v>=18 THEN
locked<=llena;
ELSE
locked<='0';
END IF;
up_v:='0';
IF pulse='1' THEN
cpt<=(cpt+1) MOD 4;
IF llena='0' THEN
-- Recover original freq when disabling low lag mode
cpt<=0;
col<=0;
IF modo='1' THEN
mfrac<=mfrac_mem;
mfrac_ref<=mfrac_mem;
up<='1';
modo<='0';
END IF;
ELSIF phm='0' AND cpt=0 THEN
-- Frequency adjust
sign_v:=tune_freq(5);
IF col<10 THEN col<=col+1; END IF;
IF off_v>=16 AND col>=10 THEN
phm<='1';
col<=0;
ELSE
off_v:=off_v+1;
IF off_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
up<='1';
END IF;
ELSIF cpt=0 THEN
-- Phase adjust
sign_v:=NOT tune_phase(5);
col<=col+1;
IF col>=10 THEN
phm<='0';
up_v:='1';
off_v:=31;
col<=0;
ELSE
off_v:=ofp_v + 1;
IF ofp_v>7 THEN
off_v:=off_v + 1;
END IF;
IF ofp_v>14 THEN
off_v:=off_v + 2;
END IF;
IF ofp_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
END IF;
up<='1';
END IF;
END IF;
diff_v:=shift_right(mfrac_ref,off_v);
IF sign_v='0' THEN
diff_v:=mfrac_ref + diff_v;
ELSE
diff_v:=mfrac_ref - diff_v;
END IF;
IF up_v='1' THEN
mfrac<=diff_v;
END IF;
IF up_v='1' AND phm='0' THEN
mfrac_ref<=diff_v;
END IF;
------------------------------------------------------
-- Update PLL registers
mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
CASE state IS
WHEN sIDLE =>
pwrite<='0';
IF up='1' THEN
up<='0';
IF mulco/=mul THEN
state<=sW1;
ELSE
state<=sW3;
END IF;
END IF;
WHEN sW1 => -- Change M multiplier
mul<=mulco;
pdata<=x"0000" & mulco;
paddress<="000100";
pwrite<='1';
state<=sW2;
WHEN sW2 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW3;
pwrite<='0';
END IF;
WHEN sW3 => -- Change M fractional value
pdata<=mfrac(31 DOWNTO 0);
paddress<="000111";
pwrite<='1';
state<=sW4;
WHEN sW4 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW5;
pwrite<='0';
END IF;
WHEN sW5 =>
pdata<=x"0000_0001";
paddress<="000010";
pwrite<='1';
state<=sW6;
WHEN sW6 =>
IF pwrite='1' AND o_waitrequest='0' THEN
pwrite<='0';
state<=sIDLE;
END IF;
END CASE;
END IF;
END PROCESS Schmurtz;
----------------------------------------------------------------------------
END ARCHITECTURE rtl;

13
sys/pll_hdmi_q13.qip Normal file
View File

@@ -0,0 +1,13 @@
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

7
sys/pll_q13.qip Normal file
View File

@@ -0,0 +1,7 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]

3
sys/pll_q17.qip Normal file
View File

@@ -0,0 +1,3 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]

102
sys/scandoubler.v
View File

@@ -49,38 +49,27 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
//Compensate picture shift after HQ2x
assign vb_out = vbo[3];
assign hb_out = hbo[6];
reg [7:0] pix_len = 0;
reg [7:0] pix_cnt = 0;
wire [7:0] pl = pix_len + 1'b1;
wire [7:0] pc = pix_cnt + 1'b1;
reg ce_x4, ce_x2, ce_x1;
reg [7:0] pix_in_cnt = 0;
wire [7:0] pc_in = pix_in_cnt + 1'b1;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
reg ce_x4i, ce_x1i;
always @(negedge clk_sys) begin
reg old_ce, valid, hs;
reg [2:0] ce_cnt;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
if(~&pix_len) pix_len <= pl;
if(~&pix_cnt) pix_cnt <= pc;
if(~&pix_in_cnt) pix_in_cnt <= pc_in;
ce_x4 <= 0;
ce_x2 <= 0;
ce_x1 <= 0;
ce_x4i <= 0;
ce_x1i <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
if( pc == pixsz2) ce_x2 <= 1;
if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1;
old_ce <= ce_pix;
if(~old_ce & ce_pix) begin
@@ -93,41 +82,72 @@ always @(negedge clk_sys) begin
valid <= 1;
end
if(hb_in | vb_in) valid <= 0;
hs <= hs_in;
if((~hs & hs_in) || (pc_in >= pixsz)) begin
ce_x4i <= 1;
ce_x1i <= 1;
pix_in_cnt <= 0;
end
hs <= hs_out;
if((~hs & hs_out) || (pc >= pixsz)) begin
ce_x2 <= 1;
ce_x4 <= 1;
ce_x1 <= 1;
pix_cnt <= 0;
if(hb_in | vb_in) valid <= 0;
end
reg req_line_reset;
reg [DWIDTH:0] r_d, g_d, b_d;
always @(posedge clk_sys) begin
if(ce_x1i) begin
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
end
end
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4),
.ce_in(ce_x4i),
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vb_in),
.reset_line(req_line_reset),
.ce_out(ce_x4o),
.read_y(sd_line),
.hblank(hbo[0]&hbo[8]),
.outpixel({b_out,g_out,r_out})
);
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
reg [7:0] pix_out_cnt = 0;
wire [7:0] pc_out = pix_out_cnt + 1'b1;
reg ce_x4o, ce_x2o;
always @(negedge clk_sys) begin
reg hs;
if(~&pix_out_cnt) pix_out_cnt <= pc_out;
ce_x4o <= 0;
ce_x2o <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1;
if( pc_out == pixsz2) ce_x2o <= 1;
hs <= hs_out;
if((~hs & hs_out) || (pc_out >= pixsz)) begin
ce_x2o <= 1;
ce_x4o <= 1;
pix_out_cnt <= 0;
end
end
reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
reg req_line_reset;
always @(posedge clk_sys) begin
reg [31:0] hcnt;
@@ -137,7 +157,7 @@ always @(posedge clk_sys) begin
reg hs, hb;
if(ce_x4) begin
if(ce_x4o) begin
hbo[8:1] <= hbo[7:0];
end
@@ -164,13 +184,6 @@ always @(posedge clk_sys) begin
hs <= hs_in;
hb <= hb_in;
if(ce_x1) begin
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
end
hcnt <= hcnt + 1'd1;
if(hb && !hb_in) begin
hde_start <= hcnt[31:1];
@@ -192,4 +205,11 @@ always @(posedge clk_sys) begin
if(!hs && hs_in) hs_start <= hcnt[31:1];
end
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4o : ce_x2o;
//Compensate picture shift after HQ2x
assign vb_out = vbo[3];
assign hb_out = hbo[6];
endmodule

1076
sys/sd_card.v
View File

File diff suppressed because it is too large Load Diff

145
sys/spdif.v
View File

@@ -31,125 +31,6 @@
// altera message_off 10240
module spdif
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_RATE = 48000,
// Generated params
parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128),
parameter ERROR_BASE = 10000,
parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input half_rate,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [15:0] audio_r,
input [15:0] audio_l,
output sample_req_o
);
reg lpf_ce;
always @(posedge clk_i) begin
reg [2:0] div;
if(bit_clk_q) div <= div + 1'd1;
lpf_ce <= !div;
end
wire [15:0] al, ar;
lpf_spdif lpf_l
(
.CLK(clk_i),
.CE(lpf_ce),
.IDATA(audio_l),
.ODATA(al)
);
lpf_spdif lpf_r
(
.CLK(clk_i),
.CE(lpf_ce),
.IDATA(audio_r),
.ODATA(ar)
);
reg bit_clk_q;
// Clock pulse generator
always @ (posedge rst_i or posedge clk_i) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg ce;
if (rst_i) begin
count_q <= 0;
error_q <= 0;
bit_clk_q <= 1;
ce <= 0;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
bit_clk_q <= 0;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) bit_clk_q <= 1;
end
end
end
//-----------------------------------------------------------------
// Core SPDIF
//-----------------------------------------------------------------
wire [31:0] sample_i = {ar, al};
spdif_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.bit_out_en_i(bit_clk_q),
.spdif_o(spdif_o),
.sample_i(sample_i),
.sample_req_o(sample_req_o)
);
endmodule
module spdif_core
(
input clk_i,
input rst_i,
@@ -417,29 +298,3 @@ else
assign spdif_o = spdif_out_q;
endmodule
module lpf_spdif
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

80
sys/sync_vg.v
View File

@@ -1,80 +0,0 @@
module sync_vg
#(
parameter X_BITS=12, Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire [Y_BITS-1:0] v_total,
input wire [Y_BITS-1:0] v_fp,
input wire [Y_BITS-1:0] v_bp,
input wire [Y_BITS-1:0] v_sync,
input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync,
output reg vs_out,
output reg hs_out,
output reg hde_out,
output reg vde_out,
output reg [X_BITS-1:0] x_out,
output reg [Y_BITS-1:0] y_out
);
reg [X_BITS-1:0] htotal,hbp,hfp,hsync;
reg [Y_BITS-1:0] vtotal,vbp,vfp,vsync;
always @(posedge clk) begin
vtotal <= v_total - 1'd1;
vsync <= v_sync - 1'd1;
vbp <= vsync + v_bp;
vfp <= vtotal - v_fp;
htotal <= h_total - 1'd1;
hsync <= h_sync - 1'd1;
hbp <= hsync + h_bp;
hfp <= htotal - h_fp;
end
reg [X_BITS-1:0] hcount;
reg [Y_BITS-1:0] vcount;
always @(posedge clk) begin
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
h_count <= h_count + 1'd1;
if (h_count == htotal) begin
h_count <= 0;
v_count <= v_count + 1'd1;
if (v_count == vtotal) v_count <= 0;
end
hcount <= h_count;
vcount <= v_count;
end
reg [X_BITS-1:0] x;
reg [Y_BITS-1:0] y;
reg hs,hde;
reg vs,vde;
always @(posedge clk) begin
if(hcount == htotal) hs <= 1;
if(hcount == hsync) hs <= 0;
if(hcount == hbp) hde <= 1;
if(hde) x <= hcount - hbp;
if(hcount == hfp) {hde,x} <= 0;
if(vcount == vtotal) vs <= 1;
if(vcount == vsync) vs <= 0;
if(vcount == vbp) vde <= 1;
if(vde) y <= vcount - vbp;
if(vcount == vfp) {vde,y} <= 0;
end
always @(posedge clk) {vs_out,hs_out,hde_out,vde_out,x_out,y_out} <= {vs,hs,hde,vde,x,y};
endmodule

12
sys/sys.qip
View File

@@ -1,8 +1,8 @@
set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
@@ -10,16 +10,14 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) v
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sync_vg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pattern_vg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

308
sys/sys.tcl Normal file
View File

@@ -0,0 +1,308 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# USER PORT
#============================================================
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip

18
sys/sys_top.sdc
View File

@@ -1,4 +1,4 @@
# Specify root clocks
# Specify root clocks
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
@@ -7,23 +7,12 @@ create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_
derive_pll_clocks
# Specify PLL-generated clock(s)
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
# Decouple different clock groups (to simplify routing)
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
@@ -31,7 +20,8 @@ set_clock_groups -asynchronous \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK 1.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *

676
sys/sys_top.v
View File

@@ -1,6 +1,6 @@
//============================================================================
//
// MiSTer hardware abstraction module (Menu core only)
// MiSTer hardware abstraction module
// (c)2017-2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
@@ -83,6 +83,12 @@ module sys_top
output SDIO_CLK,
input SDIO_CD,
////////// ADC //////////////
output ADC_SCK,
input ADC_SDO,
output ADC_SDI,
output ADC_CONVST,
////////// MB KEY ///////////
input [1:0] KEY,
@@ -99,6 +105,7 @@ module sys_top
assign SDIO_DAT[2:1] = 2'bZZ;
////////////////////////// LEDs ///////////////////////////////////////
reg [7:0] led_overtake = 0;
@@ -107,13 +114,14 @@ reg [7:0] led_state = 0;
wire led_p = led_power[1] ? ~led_power[0] : 1'b0;
wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
wire led_u = ~led_user;
wire led_locked;
assign LED_POWER = led_p ? 1'bZ : 1'b0;
assign LED_HDD = led_d ? 1'bZ : 1'b0;
assign LED_USER = led_u ? 1'bZ : 1'b0;
//LEDs on main board
assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
////////////////////////// Buttons ///////////////////////////////////
@@ -164,7 +172,7 @@ reg rack;
wire io_strobe = ~rack & io_clk;
always @(posedge clk_sys) begin
if(~io_wait | io_strobe) begin
if(~(io_wait | vs_wait) | io_strobe) begin
rack <= io_clk;
io_ack <= rack;
end
@@ -191,33 +199,45 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
reg [15:0] cfg;
reg cfg_got = 0;
reg cfg_set = 0;
//wire [2:0] hdmi_res = cfg[10:8];
wire hdmi_limited = cfg[8];
wire dvi_mode = cfg[7];
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
wire vga_scaler = cfg[2];
reg cfg_got = 0;
reg cfg_set = 0;
wire hdmi_limited = cfg[8];
wire dvi_mode = cfg[7];
wire audio_96k = cfg[6];
wire ypbpr_en = cfg[5];
wire csync = cfg[3];
wire vga_scaler= cfg[2];
reg cfg_custom_t = 0;
reg [5:0] cfg_custom_p1;
reg [31:0] cfg_custom_p2;
reg [4:0] vol_att = 0;
reg pal = 0;
reg [6:0] coef_addr;
reg [8:0] coef_data;
reg coef_wr = 0;
wire [7:0] ARX, ARY;
reg [11:0] VSET = 0;
reg [2:0] scaler_flt;
reg lowlat = 0;
reg vs_wait = 0;
always@(posedge clk_sys) begin
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
reg [7:0] cnt = 0;
reg vs_d0,vs_d1,vs_d2;
old_strobe <= io_strobe;
coef_wr <= 0;
if(~io_uio) begin
has_cmd <= 0;
cmd <= 0;
end
else
if(~old_strobe & io_strobe) begin
@@ -225,6 +245,7 @@ always@(posedge clk_sys) begin
has_cmd <= 1;
cmd <= io_din[7:0];
cnt <= 0;
if(io_din[7:0] == 'h30) vs_wait <= 1;
end
else begin
if(cmd == 1) begin
@@ -235,15 +256,15 @@ always@(posedge clk_sys) begin
cfg_set <= 0;
cnt <= cnt + 1'd1;
if(cnt<8) begin
case(cnt)
0: if(WIDTH != io_din[11:0]) begin WIDTH <= io_din[11:0]; end
1: if(HFP != io_din[11:0]) begin HFP <= io_din[11:0]; end
2: if(HS != io_din[11:0]) begin HS <= io_din[11:0]; end
3: if(HBP != io_din[11:0]) begin HBP <= io_din[11:0]; end
4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; end
5: if(VFP != io_din[11:0]) begin VFP <= io_din[11:0]; end
6: if(VS != io_din[11:0]) begin VS <= io_din[11:0]; end
7: if(VBP != io_din[11:0]) begin VBP <= io_din[11:0]; end
case(cnt[2:0])
0: if(WIDTH != io_din[11:0]) WIDTH <= io_din[11:0];
1: if(HFP != io_din[11:0]) HFP <= io_din[11:0];
2: if(HS != io_din[11:0]) HS <= io_din[11:0];
3: if(HBP != io_din[11:0]) HBP <= io_din[11:0];
4: if(HEIGHT != io_din[11:0]) HEIGHT <= io_din[11:0];
5: if(VFP != io_din[11:0]) VFP <= io_din[11:0];
6: if(VS != io_din[11:0]) VS <= io_din[11:0];
7: if(VBP != io_din[11:0]) VBP <= io_din[11:0];
endcase
if(cnt == 1) begin
cfg_custom_p1 <= 0;
@@ -259,13 +280,36 @@ always@(posedge clk_sys) begin
cfg_custom_t <= ~cfg_custom_t;
cnt[2:0] <= 3'b100;
end
if(cnt == 8) pal <= io_din[15];
if(cnt == 8) lowlat <= io_din[15];
end
end
if(cmd == 'h2F) begin
cnt <= cnt + 1'd1;
case(cnt[3:0])
0: {FB_FLT,FB_FMT,FB_EN} <= io_din[4:0];
1: FB_BASE[15:0] <= io_din[15:0];
2: FB_BASE[31:16] <= io_din[15:0];
3: FB_WIDTH <= io_din[11:0];
4: FB_HEIGHT <= io_din[11:0];
5: FB_HMIN <= io_din[11:0];
6: FB_HMAX <= io_din[11:0];
7: FB_VMIN <= io_din[11:0];
8: FB_VMAX <= io_din[11:0];
endcase
end
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
if(cmd == 'h26) vol_att <= io_din[4:0];
if(cmd == 'h27) VSET <= io_din[11:0];
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
end
end
vs_d0 <= HDMI_TX_VS;
if(vs_d0 == HDMI_TX_VS) vs_d1 <= vs_d0;
vs_d2 <= vs_d1;
if(~vs_d2 & vs_d1) vs_wait <= 0;
end
always @(posedge clk_sys) begin
@@ -327,60 +371,7 @@ wire clk_100m;
wire clk_hdmi = ~HDMI_TX_CLK; // Internal HDMI clock, inverted in relation to external clock
wire clk_audio = FPGA_CLK3_50;
///////////////////////// Lite version ////////////////////////////////
wire [11:0] x;
wire [11:0] y;
sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
(
.clk(clk_hdmi),
.reset(reset),
.v_total(HEIGHT+VFP+VBP+VS),
.v_fp(VFP),
.v_bp(VBP),
.v_sync(VS),
.h_total(WIDTH+HFP+HBP+HS),
.h_fp(HFP),
.h_bp(HBP),
.h_sync(HS),
.vde_out(vde),
.hde_out(hde),
.vs_out(hdmi_vs),
.x_out(x),
.y_out(y),
.hs_out(hdmi_hs)
);
wire vde, hde;
wire hdmi_vs,hdmi_vs2;
wire hdmi_hs,hdmi_hs2;
pattern_vg
#(
.B(8),
.X_BITS(12),
.Y_BITS(12)
)
pattern_vg
(
.reset(reset),
.clk_in(clk_hdmi),
.x(x),
.y(y),
.vs_in(hdmi_vs),
.hs_in(hdmi_hs),
.de_in(vde & hde),
.vs_out(hdmi_vs2),
.hs_out(hdmi_hs2),
.de_out(hdmi_de),
.r(hdmi_data[23:16]),
.g(hdmi_data[15:8]),
.b(hdmi_data[7:0]),
.width(WIDTH),
.height(HEIGHT),
.pattern(patt)
);
//////////////////// SYSTEM MEMORY & SCALER /////////////////////////
wire reset;
sysmem_lite sysmem
@@ -389,7 +380,8 @@ sysmem_lite sysmem
.reset_core_req(reset_req),
.reset_out(reset),
.clock(clk_100m),
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_hps_cold_req(~btn_reset),
//64-bit DDR3 RAM access
@@ -416,19 +408,178 @@ sysmem_lite sysmem
.ram2_byteenable(8'hFF),
.ram2_write(0),
//HDMI frame buffer
//128-bit DDR3 RAM access
// HDMI frame buffer
.vbuf_clk(clk_100m),
.vbuf_address(0),
.vbuf_burstcount(0),
.vbuf_waitrequest(),
.vbuf_writedata(0),
.vbuf_byteenable(0),
.vbuf_write(0),
.vbuf_readdata(),
.vbuf_readdatavalid(),
.vbuf_read(0)
.vbuf_address(vbuf_address),
.vbuf_burstcount(vbuf_burstcount),
.vbuf_waitrequest(vbuf_waitrequest),
.vbuf_writedata(vbuf_writedata),
.vbuf_byteenable(vbuf_byteenable),
.vbuf_write(vbuf_write),
.vbuf_readdata(vbuf_readdata),
.vbuf_readdatavalid(vbuf_readdatavalid),
.vbuf_read(vbuf_read)
);
wire [27:0] vbuf_address;
wire [7:0] vbuf_burstcount;
wire vbuf_waitrequest;
wire [127:0] vbuf_readdata;
wire vbuf_readdatavalid;
wire vbuf_read;
wire [127:0] vbuf_writedata;
wire [15:0] vbuf_byteenable;
wire vbuf_write;
ascal
#(
.RAMBASE(32'h20000000),
.N_DW(128),
.N_AW(28)
)
ascal
(
.reset_na (~reset_req),
.run (1),
.freeze (0),
.i_clk (clk_vid),
.i_ce (ce_pix),
.i_r (r_out),
.i_g (g_out),
.i_b (b_out),
.i_hs (hs),
.i_vs (vs),
.i_fl (f1),
.i_de (de),
.iauto (1),
.himin (0),
.himax (0),
.vimin (0),
.vimax (0),
.o_clk (clk_hdmi),
.o_ce (1),
.o_r (hdmi_data[23:16]),
.o_g (hdmi_data[15:8]),
.o_b (hdmi_data[7:0]),
.o_hs (HDMI_TX_HS),
.o_vs (HDMI_TX_VS),
.o_de (hdmi_de),
.o_lltune (lltune),
.htotal (WIDTH + HFP + HBP + HS),
.hsstart (WIDTH + HFP),
.hsend (WIDTH + HFP + HS),
.hdisp (WIDTH),
.hmin (hmin),
.hmax (hmax),
.vtotal (HEIGHT + VFP + VBP + VS),
.vsstart (HEIGHT + VFP),
.vsend (HEIGHT + VFP + VS),
.vdisp (HEIGHT),
.vmin (vmin),
.vmax (vmax),
.mode ({~lowlat,FB_EN ? FB_FLT : |scaler_flt,2'b00}),
.poly_clk (clk_sys),
.poly_a (coef_addr),
.poly_dw (coef_data),
.poly_wr (coef_wr),
.o_fb_ena (FB_EN),
.o_fb_hsize (FB_WIDTH),
.o_fb_vsize (FB_HEIGHT),
.o_fb_format (FB_FMT),
.o_fb_base (FB_BASE),
.avl_clk (clk_100m),
.avl_waitrequest (vbuf_waitrequest),
.avl_readdata (vbuf_readdata),
.avl_readdatavalid(vbuf_readdatavalid),
.avl_burstcount (vbuf_burstcount),
.avl_writedata (vbuf_writedata),
.avl_address (vbuf_address),
.avl_write (vbuf_write),
.avl_read (vbuf_read),
.avl_byteenable (vbuf_byteenable)
);
reg FB_EN = 0;
reg FB_FLT = 0;
reg [2:0] FB_FMT = 0;
reg [11:0] FB_WIDTH = 0;
reg [11:0] FB_HEIGHT = 0;
reg [11:0] FB_HMIN = 0;
reg [11:0] FB_HMAX = 0;
reg [11:0] FB_VMIN = 0;
reg [11:0] FB_VMAX = 0;
reg [31:0] FB_BASE = 0;
reg [11:0] hmin;
reg [11:0] hmax;
reg [11:0] vmin;
reg [11:0] vmax;
always @(posedge clk_vid) begin
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [2:0] state;
reg [11:0] videow;
reg [11:0] videoh;
state <= state + 1'd1;
case(state)
0: if(FB_EN) begin
hmin <= FB_HMIN;
vmin <= FB_VMIN;
hmax <= FB_HMAX;
vmax <= FB_VMAX;
state<= 0;
end
else if(ARX && ARY) begin
wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
hcalc <= (WIDTH*ARY)/ARX;
end
else begin
hmin <= 0;
hmax <= WIDTH - 1'd1;
vmin <= 0;
vmax <= HEIGHT - 1'd1;
state<= 0;
end
6: begin
videow <= (!VSET && (wcalc > WIDTH)) ? WIDTH : wcalc[11:0];
videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
end
7: begin
hmin <= ((WIDTH - videow)>>1);
hmax <= ((WIDTH - videow)>>1) + videow - 1'd1;
vmin <= ((HEIGHT - videoh)>>1);
vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
end
endcase
end
wire [15:0] lltune;
pll_hdmi_adj pll_hdmi_adj
(
.clk(FPGA_CLK1_50),
.reset_na(~reset_req),
.llena(lowlat),
.lltune(lltune),
.locked(led_locked),
.i_waitrequest(adj_waitrequest),
.i_write(adj_write),
.i_address(adj_address),
.i_writedata(adj_data),
.o_waitrequest(cfg_waitrequest),
.o_write(cfg_write),
.o_address(cfg_address),
.o_writedata(cfg_data)
);
///////////////////////// HDMI output /////////////////////////////////
@@ -454,10 +605,13 @@ reg [11:0] VBP = 36;
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
wire cfg_waitrequest,adj_waitrequest;
wire cfg_write;
wire [5:0] cfg_address;
wire [31:0] cfg_data;
reg adj_write;
reg [5:0] adj_address;
reg [31:0] adj_data;
pll_hdmi_cfg pll_hdmi_cfg
(
@@ -483,30 +637,30 @@ always @(posedge FPGA_CLK1_50) begin
gotd <= cfg_got;
gotd2 <= gotd;
cfg_write <= 0;
adj_write <= 0;
custd <= cfg_custom_t;
custd2 <= custd;
if(custd2 != custd & ~gotd) begin
cfg_address <= cfg_custom_p1;
cfg_data <= cfg_custom_p2;
cfg_write <= 1;
adj_address <= cfg_custom_p1;
adj_data <= cfg_custom_p2;
adj_write <= 1;
end
if(~gotd2 & gotd) begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
adj_address <= 2;
adj_data <= 0;
adj_write <= 1;
end
old_wait <= cfg_waitrequest;
if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1;
old_wait <= adj_waitrequest;
if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
end
hdmi_config hdmi_config
(
.iCLK(FPGA_CLK1_50),
.iRST_N(cfg_ready & ~HDMI_TX_INT & ~reset_hdmi),
.iRST_N(cfg_ready & ~HDMI_TX_INT),
.I2C_SCL(HDMI_I2C_SCL),
.I2C_SDA(HDMI_I2C_SDA),
@@ -516,8 +670,20 @@ hdmi_config hdmi_config
.hdmi_limited(hdmi_limited)
);
wire [23:0] hdmi_data,hdmi_data2;
wire hdmi_de,hdmi_de2;
wire [23:0] hdmi_data;
wire [23:0] hdmi_data_sl;
wire hdmi_de;
scanlines #(1) HDMI_scanlines
(
.clk(clk_hdmi),
.scanlines(scanlines),
.din(hdmi_data),
.dout(hdmi_data_sl),
.hs(HDMI_TX_HS),
.vs(HDMI_TX_VS)
);
osd hdmi_osd
(
@@ -528,39 +694,29 @@ osd hdmi_osd
.io_din(io_din),
.clk_video(clk_hdmi),
.din(hdmi_data),
.dout(hdmi_data2),
.din(hdmi_data_sl),
.dout(HDMI_TX_D),
.de_in(hdmi_de),
.de_out(hdmi_de2)
);
vid_dim hdmi_dim
(
.clk(clk_hdmi),
.r_in(hdmi_data2[23:16]),
.g_in(hdmi_data2[15:8]),
.b_in(hdmi_data2[7:0]),
.de_in(hdmi_de2),
.hs_in(hdmi_hs2),
.vs_in(hdmi_vs2),
.r_out(HDMI_TX_D[23:16]),
.g_out(HDMI_TX_D[15:8]),
.b_out(HDMI_TX_D[7:0]),
.de_out(HDMI_TX_DE),
.hs_out(HDMI_TX_HS),
.vs_out(HDMI_TX_VS),
.dim(dim)
.osd_status(osd_status)
);
///////////////////////// VGA output //////////////////////////////////
wire [23:0] vga_q, vga_q2;
wire hs2,vs2;
wire [23:0] vga_data_sl;
scanlines #(0) VGA_scanlines
(
.clk(clk_vid),
.scanlines(scanlines),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.dout(vga_data_sl),
.hs(hs1),
.vs(vs1)
);
osd vga_osd
(
.clk_sys(clk_sys),
@@ -570,41 +726,24 @@ osd vga_osd
.io_din(io_din),
.clk_video(clk_vid),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.din(vga_data_sl),
.dout(vga_q),
.de_in(de)
);
vid_dim vga_dim
(
.clk(clk_vid),
.r_in(vga_q[23:16]),
.g_in(vga_q[15:8]),
.b_in(vga_q[7:0]),
.hs_in(hs),
.vs_in(vs),
.r_out(vga_q2[23:16]),
.g_out(vga_q2[15:8]),
.b_out(vga_q2[7:0]),
.hs_out(hs2),
.vs_out(vs2),
.dim(dim)
);
wire [23:0] vga_q;
wire [23:0] vga_o;
vga_out vga_out
(
.ypbpr_full(1),
.ypbpr_en(ypbpr_en),
.dout(vga_o),
.din(vga_scaler ? (HDMI_TX_DE ? HDMI_TX_D : 24'd0) : vga_q2)
.din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q)
);
wire vs1 = vga_scaler ? HDMI_TX_VS : vs2;
wire hs1 = vga_scaler ? HDMI_TX_HS : hs2;
wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1;
assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1;
@@ -615,58 +754,11 @@ assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
///////////////////////// Audio output ////////////////////////////////
assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : spdif;
assign AUDIO_R = SW[0] ? HDMI_I2S : anr;
assign AUDIO_L = SW[0] ? HDMI_SCLK : anl;
assign HDMI_MCLK = 0;
i2s i2s
(
.clk_sys(clk_audio),
.reset(reset),
.half_rate(~audio_96k),
.sclk(HDMI_SCLK),
.lrclk(HDMI_LRCLK),
.sdata(HDMI_I2S),
.left_chan (audio_l),
.right_chan(audio_r)
);
wire anl;
sigma_delta_dac #(15) dac_l
(
.CLK(clk_audio),
.RESET(reset),
.DACin({~audio_l[15], audio_l[14:0]}),
.DACout(anl)
);
wire anr;
sigma_delta_dac #(15) dac_r
(
.CLK(clk_audio),
.RESET(reset),
.DACin({~audio_r[15], audio_r[14:0]}),
.DACout(anr)
);
wire aspdif;
spdif toslink
(
.clk_i(clk_audio),
.rst_i(reset),
.half_rate(0),
.audio_l(audio_l),
.audio_r(audio_r),
.spdif_o(aspdif)
);
wire [15:0] audio_l, audio_l_pre;
aud_mix_top audmix_l
@@ -700,6 +792,22 @@ aud_mix_top audmix_r
.out(audio_r)
);
wire anl,anr,spdif;
audio_out audio_out
(
.reset(reset),
.clk(clk_audio),
.sample_rate(audio_96k),
.left_in(audio_l),
.right_in(audio_r),
.i2s_bclk(HDMI_SCLK),
.i2s_lrclk(HDMI_LRCLK),
.i2s_data(HDMI_I2S),
.spdif(spdif),
.dac_l(anl),
.dac_r(anr)
);
wire [28:0] aram_address;
wire [7:0] aram_burstcount;
wire aram_waitrequest;
@@ -732,12 +840,19 @@ alsa alsa
//////////////// User I/O (USB 3.0 connector) /////////////////////////
assign USER_IO[0] = 1'bZ;
assign USER_IO[1] = 1'bZ;
assign USER_IO[2] = (SW[1] & ~HDMI_I2S) ? 1'b0 : 1'bZ;
assign USER_IO[3] = 1'bZ;
assign USER_IO[4] = (SW[1] & ~HDMI_SCLK) ? 1'b0 : 1'bZ;
assign USER_IO[5] = (SW[1] & ~HDMI_LRCLK) ? 1'b0 : 1'bZ;
assign USER_IO[0] = !user_out[0] ? 1'b0 : 1'bZ;
assign USER_IO[1] = !user_out[1] ? 1'b0 : 1'bZ;
assign USER_IO[2] = !(SW[1] ? HDMI_I2S : user_out[2]) ? 1'b0 : 1'bZ;
assign USER_IO[3] = !user_out[3] ? 1'b0 : 1'bZ;
assign USER_IO[4] = !(SW[1] ? HDMI_SCLK : user_out[4]) ? 1'b0 : 1'bZ;
assign USER_IO[5] = !(SW[1] ? HDMI_LRCLK : user_out[5]) ? 1'b0 : 1'bZ;
assign user_in[0] = USER_IO[0];
assign user_in[1] = USER_IO[1];
assign user_in[2] = SW[1] | USER_IO[2];
assign user_in[3] = USER_IO[3];
assign user_in[4] = SW[1] | USER_IO[4];
assign user_in[5] = SW[1] | USER_IO[5];
/////////////////// User module connection ////////////////////////////
@@ -746,11 +861,9 @@ wire [15:0] audio_ls, audio_rs;
wire audio_s;
wire [1:0] audio_mix;
wire [7:0] r_out, g_out, b_out;
wire vs, hs, de;
wire vs, hs, de, f1;
wire [1:0] scanlines;
wire clk_sys, clk_vid, ce_pix;
wire [2:0] patt;
wire dim;
wire reset_hdmi;
wire ram_clk;
wire [28:0] ram_address;
@@ -777,38 +890,41 @@ wire uart_cts;
wire uart_rts;
wire uart_rxd;
wire uart_txd;
wire osd_status;
wire [5:0] user_out, user_in;
emu emu
(
.CLK_50M(FPGA_CLK3_50),
.RESET(reset),
.RESET_OUT(reset_hdmi),
.HPS_BUS({HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.PAL(pal),
.VGA_R(r_out),
.VGA_G(g_out),
.VGA_B(b_out),
.VGA_HS(hs_emu),
.VGA_VS(vs_emu),
.VGA_DE(de),
.VGA_F1(f1),
.VGA_SL(scanlines),
.LED_USER(led_user),
.LED_POWER(led_power),
.LED_DISK(led_disk),
.PATTERN(patt),
.DIM(dim),
.VIDEO_ARX(ARX),
.VIDEO_ARY(ARY),
.AUDIO_L(audio_ls),
.AUDIO_R(audio_rs),
.AUDIO_S(audio_s),
.AUDIO_MIX(audio_mix),
.TAPE_IN(0),
.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
.SD_SCK(SDIO_CLK),
.SD_MOSI(SDIO_CMD),
@@ -844,12 +960,17 @@ emu emu
.UART_RXD(uart_txd),
.UART_TXD(uart_rxd),
.UART_DTR(uart_dsr),
.UART_DSR(uart_dtr)
.UART_DSR(uart_dtr),
.USER_OUT(user_out),
.USER_IN(user_in),
.OSD_STATUS(osd_status)
);
endmodule
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
module sync_fix
(
@@ -876,101 +997,56 @@ always @(posedge clk) begin
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule
/////////////////////////////////////////////////////////////////////
module aud_mix_top
(
input clk,
input [4:0] att,
input [1:0] mix,
input is_signed,
input [15:0] core_audio,
input [15:0] linux_audio,
input [15:0] pre_in,
output reg [15:0] pre_out,
output reg [15:0] out
);
reg [15:0] ca;
always @(posedge clk) begin
reg [15:0] d1,d2,d3;
d1 <= core_audio; d2<=d1; d3<=d2;
if(d2 == d3) ca <= d2;
end
always @(posedge clk) begin
reg signed [16:0] a1, a2, a3, a4;
a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]};
a2 <= a1 + {linux_audio[15],linux_audio};
pre_out <= a2[16:1];
case(mix)
0: a3 <= a2;
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
endcase
if(att[4]) a4 <= 0;
else a4 <= a3 >>> att[3:0];
//clamping
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
end
endmodule
/////////////////////////////////////////////////////////////////////
module vid_dim
module aud_mix_top
(
input clk,
input clk,
input [7:0] r_in,g_in,b_in,
input de_in,
input hs_in,
input vs_in,
input [4:0] att,
input [1:0] mix,
input is_signed,
output reg [7:0] r_out,g_out,b_out,
output reg de_out,
output reg hs_out,
output reg vs_out,
input [15:0] core_audio,
input [15:0] linux_audio,
input [15:0] pre_in,
input dim
output reg [15:0] pre_out,
output reg [15:0] out
);
reg [15:0] ca;
always @(posedge clk) begin
reg hs_in1,vs_in1;
reg [15:0] d1,d2,d3;
//compensate osd
hs_in1 <= hs_in;
vs_in1 <= vs_in;
d1 <= core_audio; d2<=d1; d3<=d2;
if(d2 == d3) ca <= d2;
end
hs_out <= hs_in1;
vs_out <= vs_in1;
de_out <= de_in;
if(dim) begin
r_out <= r_in[7:2];
g_out <= g_in[7:2];
b_out <= b_in[7:2];
end
else begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
always @(posedge clk) begin
reg signed [16:0] a1, a2, a3, a4;
a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]};
a2 <= a1 + {linux_audio[15],linux_audio};
pre_out <= a2[16:1];
case(mix)
0: a3 <= a2;
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
endcase
if(att[4]) a4 <= 0;
else a4 <= a3 >>> att[3:0];
//clamping
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
end
endmodule

182
sys/video_cleaner.sv
View File

@@ -1,91 +1,91 @@
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_VS <= vs;
VGA_HS <= hs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_VS <= vs;
VGA_HS <= hs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

334
sys/video_mixer.sv
View File

@@ -1,167 +1,167 @@
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.hb_in(HBlank),
.vb_in(VBlank),
.r_in(R),
.g_in(G),
.b_in(B),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
generate
if(HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : HSync);
wire vs = (scandoubler ? vs_sd : VSync);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~HBlank;
wire vde = scandoubler ? ~vb_sd : ~VBlank;
always @(posedge clk_sys) begin
reg old_hde;
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
VGA_R <= {1'b0, r[7:1]};
VGA_G <= {1'b0, g[7:1]};
VGA_B <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
VGA_R <= {2'b00, r[7:2]};
VGA_G <= {2'b00, g[7:2]};
VGA_B <= {2'b00, b[7:2]};
end
default: begin
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
end
endcase
VGA_VS <= vs;
VGA_HS <= hs;
old_hde <= hde;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
end
endmodule
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.hb_in(HBlank),
.vb_in(VBlank),
.r_in(R),
.g_in(G),
.b_in(B),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
generate
if(HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : HSync);
wire vs = (scandoubler ? vs_sd : VSync);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~HBlank;
wire vde = scandoubler ? ~vb_sd : ~VBlank;
always @(posedge clk_sys) begin
reg old_hde;
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
VGA_R <= {1'b0, r[7:1]};
VGA_G <= {1'b0, g[7:1]};
VGA_B <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
VGA_R <= {2'b00, r[7:2]};
VGA_G <= {2'b00, g[7:2]};
VGA_B <= {2'b00, b[7:2]};
end
default: begin
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
end
endcase
VGA_VS <= vs;
VGA_HS <= hs;
old_hde <= hde;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
end
endmodule