Update SDRAM clock.

menu.sv

@@ -202,8 +202,7 @@ pll pll
 	.refclk(CLK_50M),
 	.rst(0),
 	.outclk_0(clk_sys),
-	.outclk_1(SDRAM_CLK),
-	.outclk_2(CLK_VIDEO),
+	.outclk_1(CLK_VIDEO),
 	.locked(locked)
 );
 

sdram.sdc

@@ -1,13 +1,7 @@
 derive_pll_clocks
-
-create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}] \
-                       -name SDRAM_CLK [get_ports {SDRAM_CLK}]
-
 derive_clock_uncertainty
 
-# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) 
-set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
-set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
+set clk_sdram_sys  {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}
+set_input_delay  -source_latency_included 14.0ns -clock $clk_sdram_sys [get_ports {SDRAM_DQ[*]}]
+#set_output_delay -source_latency_included -8.0ns -clock $clk_sdram_sys [get_ports {SDRAM_D*}]
 
-set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

sdram.sv

@@ -41,6 +41,7 @@ module sdram
    output            SDRAM_nWE,   // write enable
    output            SDRAM_nRAS,  // row address select
    output            SDRAM_nCAS,  // columns address select
+   output            SDRAM_CLK,
    output            SDRAM_CKE,   // clock enable
                                   //
    input       [1:0] wtbt,        // 16bit mode:  bit1 - write high byte, bit0 - write low byte,
@@ -267,4 +268,29 @@ always @(posedge clk) begin
 	if(rd & ~old_rd) {ready, new_rd} <= {1'b0, 1'b1};
 end
 
+altddio_out
+#(
+	.extend_oe_disable("OFF"),
+	.intended_device_family("Cyclone V"),
+	.invert_output("OFF"),
+	.lpm_hint("UNUSED"),
+	.lpm_type("altddio_out"),
+	.oe_reg("UNREGISTERED"),
+	.power_up_high("OFF"),
+	.width(1)
+)
+sdramclk_ddr
+(
+	.datain_h(1'b0),
+	.datain_l(1'b1),
+	.outclock(clk),
+	.dataout(SDRAM_CLK),
+	.aclr(1'b0),
+	.aset(1'b0),
+	.oe(1'b1),
+	.outclocken(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0)
+);
+
 endmodule