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Update sys.

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Sorgelig
2024-03-20 01:38:27 +08:00
parent bbe43f7e54
commit 405e4fa55b
4 changed files with 40 additions and 23 deletions
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7
sys/sys.tcl
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@@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# I2C LEDS/BUTTONS
#============================================================

2
sys/sys_top.sdc
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@@ -35,7 +35,7 @@ set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {hdmi_width[*] hdmi_height[*]}
set_false_path -to {deb_*}
set_false_path -to {deb_* btn_en btn_up}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1

21
sys/sys_top.v
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@@ -133,7 +133,7 @@ wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD;
assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ;
assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK;
assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI;
assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | SDCD_SPDIF) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
`else
assign SD_CD = mcp_sdcd;
assign SD_MISO = mcp_sdcd | SD_SPI_MISO;
@@ -188,9 +188,22 @@ wire io_dig = mcp_en ? mcp_mode : SW[3];
wire BTN_DIS = SDRAM2_DQ[15];
`endif
wire btn_r = mcp_en ? mcp_btn[1] : ~(BTN_RESET|BTN_DIS);
wire btn_o = mcp_en ? mcp_btn[2] : ~(BTN_OSD |BTN_DIS);
wire btn_u = mcp_en ? mcp_btn[0] : ~(BTN_USER |BTN_DIS);
reg BTN_EN = 0;
reg [7:0] btn_timeout = 0;
initial btn_timeout = 0;
always @(posedge FPGA_CLK2_50) begin
reg btn_up = 0;
reg btn_en = 0;
btn_up <= BTN_RESET & BTN_OSD & BTN_USER;
if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1;
btn_en <= ~BTN_DIS;
BTN_EN <= &btn_timeout & btn_en;
end
wire btn_r = mcp_en ? mcp_btn[1] : (BTN_EN & ~BTN_RESET);
wire btn_o = mcp_en ? mcp_btn[2] : (BTN_EN & ~BTN_OSD );
wire btn_u = mcp_en ? mcp_btn[0] : (BTN_EN & ~BTN_USER );
reg btn_user, btn_osd;
always @(posedge FPGA_CLK2_50) begin

33
sys/video_freak.sv
View File

@@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
wire [23:0] mul_res;
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
wire [11:0] wideres = mul_res[11:0] + hsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] oheight,htarget,wres;
reg [11:0] oheight,htarget,wres,hinteger,wideres;
reg [12:0] arxf,aryf;
reg [3:0] cnt;
reg narrow;
@@ -264,7 +262,8 @@ always @(posedge CLK_VIDEO) begin
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
7: if(mul_res <= HDMI_WIDTH) begin
cnt <= 10;
hinteger = mul_res[11:0];
cnt <= 12;
end
8: begin
@@ -285,9 +284,21 @@ always @(posedge CLK_VIDEO) begin
// [2] 1920 / 640 * 640 -> 1920
// [3] 1920 / 512 * 512 -> 1536
10: begin
narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
10: begin
hinteger <= mul_res[11:0];
mul_arg1 <= vsize;
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
mul_start <= 1;
end
11: begin
oheight <= mul_res[11:0];
end
12: begin
wideres <= hinteger + hsize;
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
wres <= hinteger == htarget ? hinteger : wideres;
end
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
@@ -299,11 +310,11 @@ always @(posedge CLK_VIDEO) begin
// to target width, meaning it is not optimal for source aspect ratio.
// otherwise it is set to narrow width that is optimal.
11: begin
13: begin
case(SCALE)
2: arxf <= {1'b1, mul_res[11:0]};
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
2: arxf <= {1'b1, hinteger};
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
4: arxf <= {1'b1, narrow ? hinteger : wres};
default: arxf <= {1'b1, div_num[11:0]};
endcase
aryf <= {1'b1, oheight};