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Release 20180313.
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Update API.
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Variable SDRAM clock and updated interface.
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memtest.sv
Re-work SDRAM module. Use detected SDRAM size. Support for 128MB module.
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README.md
Variable SDRAM clock and updated interface.
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tester.v
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vgaout.v
Re-work SDRAM module. Use detected SDRAM size. Support for 128MB module.
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Update sys. Support for SDRAM v2.
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vpll.17.qip
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vpll.v
Variable SDRAM clock and updated interface.
2018-03-13 00:47:35 +08:00

README.md

MemTest - Utility to test SDRAM daughter board.

Screen shows 4 numbers:

  • Upper left is time in minutes passed.
  • Upper right is memory frequency in MHz.
  • Middle (green) is amount of passed cycles (each cycle is 32MB)
  • Lower (red) is amount of errors.
  • Dash in cyan color will fly on top in auto mode.

Controls (keyboard)

  • Up - increase frequency
  • Down - decrease frequency
  • Enter - reset the test
  • A - auto mode, detecting the maximum frequency for module being tested. Test starts from maximum frequency. With every error frequency will be decreased.

Test is passed if amount of errors is 0. For quick test let it run for 10 minutes in auto mode. If you want to be sure, let it run for 1-2 hours. Board should pass at least 130MHz clock test. Any higher clock will assure the higher quality of the board.

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Readme 12 MiB
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Verilog 58.4%
VHDL 18.9%
SystemVerilog 18.5%
Tcl 4.1%
Batchfile 0.1%