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MCD: implement CD fader

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This commit is contained in:
Sergey Dvodnenko
2019-12-21 14:08:39 +02:00
parent cb5fbfcbaa
commit 8ef6a54ca0
3 changed files with 57 additions and 21 deletions
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9
MCD/ASIC.vhd
View File

@@ -93,6 +93,9 @@ entity ASIC is
WORDRAM1_DO : out std_logic_vector(15 downto 0);
WORDRAM1_WR : out std_logic;
FD_DAT : out std_logic_vector(10 downto 0);
FD_WR : out std_logic;
LED_RED : out std_logic;
LED_GREEN : out std_logic
);
@@ -811,6 +814,7 @@ begin
OLD_CDC_INT_N <= '1';
HOCK_OLD <= '0';
SW_CLR <= '0';
FD_WR <= '0';
INT_PEND(3) <= '0';
INT_PEND(4) <= '0';
@@ -827,6 +831,7 @@ begin
DMA_ADDR_SET <= '0';
VW_SET <= '0';
FD_WR <= '0';
if GS = GS_END then
GRON <= '0';
@@ -964,6 +969,8 @@ begin
IEN <= S68K_DI(6 downto 1);
end if;
when "0011010" => null; --$FF8034 CD fader
FD_DAT <= S68K_DI(14 downto 4);
FD_WR <= '1';
when "0011011" => --$FF8036 CDD control
if S68K_LDS_N = '0' then
HOCK <= S68K_DI(2);
@@ -1130,7 +1137,7 @@ begin
when "0011001" => --$FF8032 Inerrupt mask control
S68K_REG_DO <= x"00" & "0" & IEN & "0";
when "0011010" => --$FF8034 CD fader
S68K_REG_DO <= x"0000"; ---------------------------------------------------
S68K_REG_DO <= x"0000";
when "0011011" => --$FF8036 CDD control
S68K_REG_DO <= "0000000" & CDD_DM & "00000" & HOCK & "00";
when "0011100" => --$FF8038 CDD status 0,1

59
MCD/CDDA.vhd
View File

@@ -24,20 +24,23 @@ end CD_DAC;
architecture rtl of CD_DAC is
signal EN : std_logic;
signal EN : std_logic;
signal CD_WR_OLD : std_logic;
signal LR : std_logic;
signal FULL : std_logic;
signal EMPTY : std_logic;
signal RD_REQ : std_logic;
signal WR_REQ : std_logic;
signal FIFO_DATA : std_logic_vector(31 downto 0);
signal FIFO_Q : std_logic_vector(31 downto 0);
signal SAMPLE_CE : std_logic;
signal CD_WR_OLD : std_logic;
signal LR : std_logic;
signal FULL : std_logic;
signal EMPTY : std_logic;
signal RD_REQ : std_logic;
signal WR_REQ : std_logic;
signal FIFO_D : std_logic_vector(31 downto 0);
signal FIFO_Q : std_logic_vector(31 downto 0);
signal SAMPLE_CE : std_logic;
signal OUTL : signed(15 downto 0);
signal OUTR : signed(15 downto 0);
signal ATT : unsigned(10 downto 0);
signal ATT_CUR : unsigned(11 downto 0);
signal OUTL : signed(15 downto 0);
signal OUTR : signed(15 downto 0);
begin
@@ -47,7 +50,7 @@ begin
begin
if RST_N = '0' then
LR <= '0';
FIFO_DATA <= (others => '0');
FIFO_D <= (others => '0');
WR_REQ <= '0';
CD_WR_OLD <= '0';
elsif rising_edge(CLK) then
@@ -57,9 +60,9 @@ begin
if CD_WR = '1' and CD_WR_OLD = '0' then
LR <= not LR;
if LR = '0' then
FIFO_DATA(15 downto 0) <= CD_DI;
FIFO_D(15 downto 0) <= CD_DI;
else
FIFO_DATA(31 downto 16) <= CD_DI;
FIFO_D(31 downto 16) <= CD_DI;
if FULL = '0' and DM = '0' then
WR_REQ <= '1';
end if;
@@ -72,7 +75,7 @@ begin
FIFO : entity work.CDDA_FIFO
port map(
clock => CLK,
data => FIFO_DATA,
data => FIFO_D,
wrreq => WR_REQ,
full => FULL,
@@ -90,21 +93,41 @@ begin
CE => SAMPLE_CE
);
process( RST_N, CLK )
begin
if RST_N = '0' then
ATT <= "10000000000";
elsif rising_edge(CLK) then
if EN = '1' then
if FD_WR = '1' then
ATT <= unsigned(FD_DI);
end if;
end if;
end if;
end process;
process( RST_N, CLK )
begin
if RST_N = '0' then
RD_REQ <= '0';
ATT_CUR <= "010000000000";
elsif rising_edge(CLK) then
RD_REQ <= '0';
if EN = '1' and SAMPLE_CE = '1' then -- ~44.1kHz
if EMPTY = '0' then
RD_REQ <= '1';
OUTL <= signed(FIFO_Q(15 downto 0));
OUTR <= signed(FIFO_Q(31 downto 16));
OUTL <= resize(shift_right(signed(FIFO_Q(15 downto 0)) * signed(ATT_CUR), 10), OUTL'length);
OUTR <= resize(shift_right(signed(FIFO_Q(31 downto 16)) * signed(ATT_CUR), 10), OUTR'length);
else
OUTL <= (others => '0');
OUTR <= (others => '0');
end if;
if ATT_CUR(10 downto 0) > ATT then
ATT_CUR <= "0" & (ATT_CUR(10 downto 0) - 1);
elsif ATT_CUR(10 downto 0) < ATT then
ATT_CUR <= "0" & (ATT_CUR(10 downto 0) + 1);
end if;
end if;
end if;
end process;

10
MCD/MCD.vhd
View File

@@ -126,6 +126,9 @@ architecture rtl of MCD is
signal PCM_RAM_DI_B : std_logic_vector(7 downto 0);
signal PCM_RAM_DO_A : std_logic_vector(7 downto 0);
signal PCM_RAM_WE_A : std_logic;
signal ASIC_FD_DAT : std_logic_vector(10 downto 0);
signal ASIC_FD_WR : std_logic;
begin
@@ -247,6 +250,9 @@ begin
WORDRAM1_DO => WORDRAM1_DO,
WORDRAM1_WR => WORDRAM1_WR,
FD_DAT => ASIC_FD_DAT,
FD_WR => ASIC_FD_WR,
LED_RED => LED_RED,
LED_GREEN => LED_GREEN
);
@@ -368,8 +374,8 @@ begin
CD_DI => CDC_DATA,
CD_WR => CDC_DAT_WR,
FD_DI => (others => '0'),
FD_WR => '0',
FD_DI => ASIC_FD_DAT,
FD_WR => ASIC_FD_WR,
DM => CDD_DM,