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CPU type option. Some tweaks and cleanup.

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sorgelig
2019-03-10 08:08:54 +08:00
parent 2083843054
commit 6eba4ead42
7 changed files with 27 additions and 161 deletions
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6
CPU/t80.vhd
View File

@@ -72,7 +72,7 @@
--
-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
--
-- +k02 : Added portF4_mode signal by KdL 2018.05.14
-- +k02 : Added R800_mode signal by KdL 2018.05.14
--
library IEEE;
@@ -116,7 +116,7 @@ entity T80 is
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
portF4_mode : in std_logic;
R800_mode : in std_logic;
IntE : out std_logic;
Stop : out std_logic
);
@@ -329,7 +329,7 @@ begin
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc,
portF4_mode => portF4_mode);
R800_mode => R800_mode);
alu : T80_ALU
generic map(

8
CPU/t80_mcode.vhd
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@@ -148,7 +148,7 @@ entity T80_MCode is
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic;
portF4_mode : in std_logic
R800_mode : in std_logic
);
end T80_MCode;
@@ -194,7 +194,7 @@ architecture rtl of T80_MCode is
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State, portF4_mode)
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State, R800_mode)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
@@ -1970,7 +1970,7 @@ begin
end case;
when "11000001"|"11001001"|"11010001"|"11011001" =>
--R800 MULUB
if R800_MULU=1 and portF4_mode = '1' then
if R800_MULU=1 and R800_mode = '1' then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
@@ -1987,7 +1987,7 @@ begin
end if;
when "11000011"|"11110011" =>
--R800 MULUW
if R800_MULU=1 and portF4_mode = '1' then
if R800_MULU=1 and R800_mode = '1' then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>

6
CPU/t80_pack.vhd
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@@ -46,7 +46,7 @@
--
-- 0250 : Version alignment by KdL 2017.10.23
--
-- +k02 : Added portF4_mode signal by KdL 2018.05.14
-- +k02 : Added R800_mode signal by KdL 2018.05.14
--
library IEEE;
@@ -90,7 +90,7 @@ package T80_Pack is
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
portF4_mode : in std_logic;
R800_mode : in std_logic;
IntE : out std_logic;
Stop : out std_logic
);
@@ -188,7 +188,7 @@ package T80_Pack is
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic;
portF4_mode : in std_logic
R800_mode : in std_logic
);
end component;

6
CPU/t80a.vhd
View File

@@ -65,7 +65,7 @@
--
-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
--
-- +k02 : Added portF4_mode signal by KdL 2018.05.14
-- +k02 : Added R800_mode signal by KdL 2018.05.14
--
library IEEE;
@@ -83,7 +83,7 @@ entity T80a is
RESET_n : in std_logic;
RstKeyLock : in std_logic;
swioRESET_n : in std_logic;
portF4_mode : in std_logic;
R800_mode : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
@@ -181,7 +181,7 @@ begin
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
portF4_mode => portF4_mode);
R800_mode => R800_mode);
process (CLK_n)
begin

5
MSX.sv
View File

@@ -137,14 +137,14 @@ localparam CONF_STR = {
"O23,Scanlines,No,25%,50%,75%;",
"-;",
"O1,CPU speed,Normal,Turbo(+F11);",
"OB,CPU type,Z80,R800;",
"-;",
"O4,Slot1,Empty,MegaSCC+ 1MB;",
"O56,Slot2,Empty,MegaSCC+ 2MB,MegaRAM ASCII-8K 1MB,MegaRAM ASCII-16K 2MB;",
"-;",
"O7,Internal Mapper,2048KB RAM,4096KB RAM;",
"-;",
"RA,Warm Reset;",
"R0,Cold Reset;",
"RA,Reset;",
"J,Fire 1,Fire 2;",
"V,v",`BUILD_DATE
};
@@ -323,6 +323,7 @@ emsx_top emsx
.pDip({1'b0,~status[7],~status[6:5],~status[4],2'b00,~status[1]}),
.pLed(),
.pLedPwr(),
.pR800(status[11]),
.pDac_VR(r),
.pDac_VG(g),

46
emsx_top.vhd
View File

@@ -85,6 +85,7 @@ entity emsx_top is
pDip : in std_logic_vector( 7 downto 0); -- 0=On, 1=Off (default on shipment)
pLed : out std_logic_vector( 7 downto 0); -- 0=Off, 1=On (green)
pLedPwr : out std_logic; -- 0=Off, 1=On (red)
pR800 : in std_logic;
-- Video, Audio/CMT ports
pDac_VR : out std_logic_vector( 5 downto 0); -- RGB_Red
@@ -110,7 +111,7 @@ architecture RTL of emsx_top is
RESET_n : in std_logic;
RstKeyLock : in std_logic;
swioRESET_n : in std_logic;
portF4_mode : in std_logic;
R800_mode : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
@@ -740,8 +741,6 @@ architecture RTL of emsx_top is
-- Sound output, Toggle keys
signal vFKeys : std_logic_vector( 7 downto 0 );
signal ff_Scro : std_logic;
signal ff_Reso : std_logic;
-- DRAM arbiter
signal w_wrt_req : std_logic;
@@ -930,13 +929,11 @@ begin
Slot2Mode(0) <= io42_id212(5);
end if;
end if;
-- keyboard layout assignment
if( w_10hz = '1' )then
Kmap <= swioKmap;
end if;
end if;
end process;
-- keyboard layout assignment
Kmap <= swioKmap when rising_edge(clk21m);
-- cpu clock assignment
trueClk <= '1' when( SdPaus /= '0' )else
@@ -1156,16 +1153,7 @@ begin
end process;
-- DIP SW latch
process( clk21m )
begin
if( clk21m'event and clk21m = '1' )then
if( w_10hz = '1' and SdPaus = '0' )then -- chattering protect
ff_dip_req <= not pDip; -- convert negative logic to positive logic, and latch
else
-- hold
end if;
end if;
end process;
ff_dip_req <= not pDip when rising_edge(clk21m);
-- LEDs luminance
process( clk21m )
@@ -1727,18 +1715,6 @@ begin
end if;
end process;
-- PRNSCR key
process( reset, clk21m )
begin
if( reset = '1' )then
ff_Reso <= '0';
elsif( clk21m'event and clk21m = '1' )then
if( FirstBoot_n /= '1' or RstEna = '1' )then
ff_Reso <= Reso;
end if;
end if;
end process;
----------------------------------------------------------------
-- Sound output
----------------------------------------------------------------
@@ -2105,7 +2081,7 @@ begin
RESET_n => pSltRst_n,
RstKeyLock => RstKeyLock,
swioRESET_n => swioRESET_n,
portF4_mode => portF4_mode,
R800_mode => pR800,
CLK_n => trueClk,
WAIT_n => pSltWait_n,
INT_n => pSltInt_n,
@@ -2237,10 +2213,10 @@ begin
ff_dip_ack => ff_dip_ack , -- here to reduce LEs
SdPaus => SdPaus ,
Scro => Scro ,
ff_Scro => '0' , --ff_Scro ,
Reso => Reso ,
ff_Reso => ff_Reso ,
Scro => '0' ,
ff_Scro => '0' ,
Reso => '0' ,
ff_Reso => '0' ,
FKeys => FKeys ,
vFKeys => vFKeys ,
LevCtrl => LevCtrl ,

111
peripheral/swioports.vhd
View File

@@ -294,26 +294,6 @@ begin
end if;
-- in assignment: 'Toggle Keys' (keyboard)
if( SdPaus = '0' )then
if( io43_id212(2) = '0' )then -- BIT[2]=0 of Lock Mask
-- if( Fkeys(5 downto 4) /= vFKeys(5 downto 4) )then
-- GreenLvEna <= '1';
-- LevCtrl <= "111";
-- end if;
-- if( Fkeys(4) /= vFkeys(4) )then -- PGDOWN is Master Volume Down
-- if( MstrVol /= "111" )then
-- LevCtrl <= not (MstrVol + 1);
-- MstrVol <= MstrVol + 1;
-- else
-- LevCtrl <= "000";
-- end if;
-- end if;
-- if( Fkeys(5) /= vFkeys(5) )then -- PGUP is Master Volume Up
-- if( MstrVol /= "000" )then
-- LevCtrl <= not (MstrVol - 1);
-- MstrVol <= MstrVol - 1;
-- end if;
-- end if;
end if;
if( Fkeys(7) = '0' )then -- SHIFT key is Off
if( io43_id212(0) = '0' )then -- BIT[0]=0 of Lock Mask
if( Fkeys(1) /= vFKeys(1) )then -- F11 is TURBO selector
@@ -331,97 +311,6 @@ begin
end if;
end if;
end if;
if( io43_id212(1) = '0' )then -- BIT[1]=0 of Lock Mask
if( ff_Reso /= Reso )then -- PRNSCR is DISPLAY selector (next)
case io42_id212(2 downto 1) is
when "00" => io42_id212(2) <= '1'; -- Y/C to RGB
when "10" => io42_id212(2 downto 1) <= "01"; -- RGB to VGA
when "01" => io42_id212(2) <= '1'; -- VGA to VGA+
when "11" => io42_id212(2 downto 1) <= "00"; -- VGA+ to Y/C
end case;
end if;
end if;
if( io43_id212(2) = '0' )then -- BIT[2]=0 of Lock Mask
-- if( Fkeys(3 downto 1) /= vFKeys(3 downto 1) )then
-- GreenLvEna <= '1';
-- LevCtrl <= "111";
-- end if;
-- if( Fkeys(1) /= vFKeys(1) )then -- F11 is OPLL Volume Up
-- if( OpllVol /= "111" )then
-- LevCtrl <= OpllVol + 1;
-- OpllVol <= OpllVol + 1;
-- end if;
-- end if;
-- if( Fkeys(2) /= vFKeys(2) )then -- F10 is SCC-I Volume Up
-- if( SccVol /= "111" )then
-- LevCtrl <= SccVol + 1;
-- SccVol <= SccVol + 1;
-- end if;
-- end if;
-- if( Fkeys(3) /= vFKeys(3) )then -- F9 is PSG Volume Up
-- if( PsgVol /= "111" )then
-- LevCtrl <= PsgVol + 1;
-- PsgVol <= PsgVol + 1;
-- end if;
-- end if;
if( ff_Scro /= Scro and portF4_mode = '0' )then -- SCRLK is CMT selector
swioCmt <= not swioCmt;
end if;
end if;
else -- SHIFT key is On
if( io43_id212(1) = '0' )then -- BIT[1]=0 of Lock Mask
if( ff_Reso /= Reso )then -- SHIFT+PRNSCR is DISPLAY selector (previous)
case io42_id212(2 downto 1) is
when "11" => io42_id212(2) <= '0'; -- VGA+ to VGA
when "01" => io42_id212(2 downto 1) <= "10"; -- VGA to RGB
when "10" => io42_id212(2) <= '0'; -- RGB to Y/C
when "00" => io42_id212(2 downto 1) <= "11"; -- Y/C to VGA+
end case;
end if;
end if;
if( io43_id212(2) = '0' )then -- BIT[2]=0 of Lock Mask
-- if( Fkeys(3 downto 1) /= vFKeys(3 downto 1) )then
-- GreenLvEna <= '1';
-- LevCtrl <= "000";
-- end if;
-- if( Fkeys(1) /= vFKeys(1) )then -- SHIFT+F11 is OPLL Volume Down
-- if( OpllVol /= "000" )then
-- LevCtrl <= OpllVol - 1;
-- OpllVol <= OpllVol - 1;
-- end if;
-- end if;
-- if( Fkeys(2) /= vFKeys(2) )then -- SHIFT+F10 is SCC-I Volume Down
-- if( SccVol /= "000" )then
-- LevCtrl <= SccVol - 1;
-- SccVol <= SccVol - 1;
-- end if;
-- end if;
-- if( Fkeys(3) /= vFKeys(3) )then -- SHIFT+F9 is PSG Volume Down
-- if( PsgVol /= "000" )then
-- LevCtrl <= PsgVol - 1;
-- PsgVol <= PsgVol - 1;
-- end if;
-- end if;
end if;
-- if( io43_id212(3) = '0' )then -- BIT[3]=0 of Lock Mask
-- if( Fkeys(0) /= vFKeys(0) )then -- SHIFT+F12 is SLOT1 selector
-- io42_id212(3) <= not io42_id212(3);
-- end if; -- EXTERNAL SLOT1 >> << INTERNAL SCC-I(A)
-- end if;
if( io43_id212(4) = '0' )then -- BIT[4]=0 of Lock Mask
if( ff_Scro /= Scro )then -- SHIFT+SCRLK is SLOT2 selector
case io42_id212(5 downto 4) is
when "00" => io42_id212(5) <= '1'; -- EXTERNAL SLOT2 to INTERNAL ASCII 8K
when "10" => io42_id212(5 downto 4) <= "01"; -- INTERNAL ASCII 8K to INTERNAL SCC-I(B)
when "01" => io42_id212(5) <= '1'; -- INTERNAL SCC-I(B) to INTERNAL ASCII 16K
when "11" => io42_id212(5 downto 4) <= "00"; -- INTERNAL ASCII 16K to EXTERNAL SLOT2
end case;
end if; -- Hint! You can get SCC-I(B) quickly with a SHIFT+'double'SCRLK
end if;
end if;
end if;
-- in assignment: 'Port $40 [ID Manufacturers/Devices]' (read_n/write)