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133 Commits

Author SHA1 Message Date
RYZEN\tomas
e49c511f42 Correct size detect 2023-03-29 19:43:05 +02:00
RYZEN\tomas
4034324461 Merge remote-tracking branch 'template/master' 2022-10-08 00:25:10 +02:00
Martin Donlon
7c2a2793a4 ascal: use maximum color value for luminance (#54) 
Instead of using a luminance approximation based on the color channels, just use the maximum value from the color channels as luminance.
Move the horizontal luminance calculation back into the horizontal upscale. The benefits of calculating it when we shift in new pixel data have vanished and the timing is more difficult there.

(cherry picked from commit 5f6dc97ec1)
 2022-10-07 23:49:16 +02:00
Sorgelig
cf32d57052 fix some warnings. 
(cherry picked from commit d8eeb5b61a)
 2022-10-07 23:49:09 +02:00
RobertPeip
e87bfbe939 clock in HDMI signals in hdmi_tx_clk domain to improve timing closure (#53) 
(cherry picked from commit 64fa857380)
 2022-10-07 23:49:05 +02:00
Sorgelig
a148c4d6cb hsync/vsync polarity flags for VGA output. 
(cherry picked from commit 5ec2f3f080)
 2022-10-07 23:49:00 +02:00
Martin Donlon
4ffe4fdaa0 Increase polyphase coefficient size to 10-bits (#52) 
256 phases, 40-bits per phase

(cherry picked from commit 1ca01072d2)
 2022-10-07 23:48:55 +02:00
Martin Donlon
72c790046e Support 256 phases in upscaler (#51) 
Set FRAC to 8.
Add an additional stage in the horizontal upscale and increase division by 2 bits.

(cherry picked from commit 0b81628d79)
 2022-10-07 23:48:49 +02:00
Sorgelig
fe546910c3 Pass video rotation flag to HPS. 
(cherry picked from commit c5662f57f1)
 2022-10-07 23:48:43 +02:00
Sorgelig
2d2ea6c939 hps_io: add ioctl_upload_index. 
(cherry picked from commit 171262a66e)
 2022-10-07 23:48:38 +02:00
Sorgelig
809b50c21a Move MISTER_DUAL_SDRAM definition to sys_dual_sdram.tcl 
(cherry picked from commit 5355c2b9e8)
 2022-10-07 23:48:32 +02:00
Sorgelig
fe4986e3fb ce_pix must be delayed too. 
(cherry picked from commit ab78d221d0)
 2022-10-07 23:48:26 +02:00
Martin Donlon
a5356aefc5 Brightness adaptive scanline filters (#49) 
Interpolate between two sets of filter coefficients based on the luminosity of the source pixel. Intended to be used to simulate the widening of CRT phosphor glow as the intensity of the beam increases.

Make downscale filtering and adaptive scanlines optional

(cherry picked from commit c24d24bdbc)
 2022-10-07 23:48:15 +02:00
Sorgelig
f71e9376e1 FB mode signal to HPS. 
(cherry picked from commit 24116a17cd)
 2022-10-07 23:48:08 +02:00
Sorgelig
f4e056a699 Use 64 phases for scaling, aligned Shadow Mask, scanlines flag for HPS. 
(cherry picked from commit cb02d94f9a)
 2022-10-07 23:48:03 +02:00
RYZEN\tomas
f8b60ed935 revert template 2022-10-07 23:42:59 +02:00
Sorgelig
fd7826feba cherry pick template: Use 64 phases for scaling, aligned Shadow Mask, scanlines flag for HPS. 
Commit: cb02d94f9a [cb02d94]
 2022-10-07 23:41:35 +02:00
Martin Donlon
10e2b6c963 Use half size when height matches vertical resolution. (#67) 
If the height exactly matches the vertical resolution then v_osd_start will be set to 0, but v_cnt starts counting from 1 so the OSD will never be drawn. Maybe v_cnt should start at 0, but that will throw of some other things. This fixes the issue I am seeing in the M72 core which has a vertical resolution of 256.
 2022-08-26 05:59:57 +08:00
Sorgelig
0a27650654 Add VGA_DISABLE signal, enable Analog I/O buttons for dual SDRAM builds. 2022-07-18 01:35:47 +08:00
Sorgelig
0b10601b02 ascal: rework VRR logic to fix instability. 2022-07-18 01:34:38 +08:00
Sorgelig
e09ce4689a Bump small video buffer size to 2MB. 2022-07-08 02:52:06 +08:00
Sorgelig
a3f1522f38 ascal: adjust formatting. 2022-06-29 09:06:13 +08:00
Sorgelig
749002ddeb ascal: support for VRR. 2022-06-29 08:49:15 +08:00
Martin Donlon
85fbbf879c HDMI Pixel Repeat (#64) 
Add support for hdmi pixel repetition in aspect ratio calcs.
 2022-06-05 23:55:24 +08:00
paulb-nl
29c54fd431 Direct Video interlace fix (#63) 
Some cores don't toggle the field signal with some interlace modes
so use another way to detect the fields
 2022-06-04 06:12:13 +08:00
Sorgelig
c1080e2e8b Adjust fb_crc. 2022-05-24 12:48:18 +08:00
Sorgelig
a5ca2473ee Add command to get framebuffer parameters. 2022-05-24 04:42:45 +08:00
Sorgelig
7411d19090 Option to compile with smaller scaler buffers. 2022-05-17 21:59:42 +08:00
Sorgelig
9145c7fd68 Remove hdmi configuration. It's handled by HPS now. 2022-05-16 21:45:36 +08:00
Sorgelig
79e54ac7a3 128bit status. Example of new addressing of status bits in OSD. 2022-05-05 21:13:58 +08:00
Skooter
24de2f548b Set YC bits (YCC Quantization Range) to match the RGB quantization range as defined in CTA‐861. (#60) 2022-04-23 03:25:26 +08:00
Skooter
7f7c58a9f1 Set VIC to 0 and IT Content to Game (#59) 
VIC=0
IT Content = Game
R3 = 1
S1 = 1
 2022-04-20 21:55:23 +08:00
Martin Donlon
10e7e91107 Add two stages to adaptive polyphase (#56) 
Improve timing
Ensure optimal register usage for DSP units
 2022-04-05 20:11:24 +08:00
Sorgelig
a9d79e25b1 hps_io: fix rumble index. 2022-03-13 21:21:05 +08:00
Sorgelig
cda17d05fc Combine rumble I/O id. 2022-03-13 16:14:53 +08:00
zakk4223
6df832a944 hps_io: pass joystick rumble data to HPS (#55) 
Co-authored-by: Zakk <zakk@rsdio.com>
 2022-03-13 15:21:33 +08:00
Martin Donlon
5f6dc97ec1 ascal: use maximum color value for luminance (#54) 
Instead of using a luminance approximation based on the color channels, just use the maximum value from the color channels as luminance.
Move the horizontal luminance calculation back into the horizontal upscale. The benefits of calculating it when we shift in new pixel data have vanished and the timing is more difficult there.
 2022-03-03 18:10:22 +08:00
Sorgelig
d8eeb5b61a fix some warnings. 2022-02-27 01:26:35 +08:00
RobertPeip
64fa857380 clock in HDMI signals in hdmi_tx_clk domain to improve timing closure (#53) 2022-02-26 21:07:56 +08:00
Sorgelig
5ec2f3f080 hsync/vsync polarity flags for VGA output. 2022-02-26 15:21:48 +08:00
Martin Donlon
1ca01072d2 Increase polyphase coefficient size to 10-bits (#52) 
256 phases, 40-bits per phase
 2022-02-21 15:24:16 +08:00
Martin Donlon
0b81628d79 Support 256 phases in upscaler (#51) 
Set FRAC to 8.
Add an additional stage in the horizontal upscale and increase division by 2 bits.
 2022-02-20 15:44:28 +08:00
Sorgelig
c5662f57f1 Pass video rotation flag to HPS. 2022-02-16 06:10:29 +08:00
Sorgelig
171262a66e hps_io: add ioctl_upload_index. 2022-02-14 02:54:56 +08:00
Sorgelig
5355c2b9e8 Move MISTER_DUAL_SDRAM definition to sys_dual_sdram.tcl 2022-02-12 22:05:29 +08:00
Sorgelig
ab78d221d0 ce_pix must be delayed too. 2022-02-11 08:10:10 +08:00
Martin Donlon
c24d24bdbc Brightness adaptive scanline filters (#49) 
Interpolate between two sets of filter coefficients based on the luminosity of the source pixel. Intended to be used to simulate the widening of CRT phosphor glow as the intensity of the beam increases.

Make downscale filtering and adaptive scanlines optional
 2022-02-10 19:57:52 +08:00
Sorgelig
24116a17cd FB mode signal to HPS. 2022-01-31 23:14:05 +08:00
Sorgelig
cb02d94f9a Use 64 phases for scaling, aligned Shadow Mask, scanlines flag for HPS. 2021-12-29 02:33:56 +08:00
Grabulosaure
5775b79617 ASCAL : Optimise Nearest-neighbor mode (#47) 
Co-authored-by: Grabulosaure <dev@temlib.org>
 2021-12-26 06:47:05 +08:00