Use 64 phases for scaling, aligned Shadow Mask, scanlines flag for HPS.

2026-04-26 03:04:41 +00:00 · 2021-12-29 02:33:56 +08:00
parent 5775b79617
commit cb02d94f9a
5 changed files with 42 additions and 47 deletions
--- a/mycore.sv
+++ b/mycore.sv
@@ -26,7 +26,7 @@ module emu
 	input         RESET,

 	//Must be passed to hps_io module
-	inout  [45:0] HPS_BUS,
+	inout  [47:0] HPS_BUS,

 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
--- a/sys/ascal.vhd
+++ b/sys/ascal.vhd
@@ -151,6 +151,7 @@ ENTITY ascal IS
    o_vs  : OUT std_logic; -- V sync
    o_de  : OUT std_logic; -- Display Enable
    o_vbl : OUT std_logic; -- V blank
+    o_brd : OUT std_logic; -- border enable
    o_ce  : IN  std_logic; -- Clock Enable
    o_clk : IN  std_logic; -- Output clock
    
@@ -2579,6 +2580,7 @@ BEGIN
        o_r<=x"00";
        o_g<=x"00";
        o_b<=x"00";
+        o_brd<= not o_pev(5);
            
        CASE o_vmode(2 DOWNTO 0) IS
          WHEN "000" => -- Nearest
--- a/sys/hps_io.sv
+++ b/sys/hps_io.sv
@@ -24,13 +24,13 @@
 // Use buffer to access SD card. It's time-critical part.
 //
 // WIDE=1 for 16 bit file I/O
-// VDNUM 1..4
+// VDNUM 1..10
 // BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
 //
 module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
 (
 	input             clk_sys,
-	inout      [45:0] HPS_BUS,
+	inout      [47:0] HPS_BUS,

 	// buttons up to 32
 	output reg [31:0] joystick_0,
@@ -316,7 +316,7 @@ always@(posedge clk_sys) begin : uio_block
 				'h0X17,
 				'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
 				  'h29: io_dout <= {4'hA, stflg};
-				  'h2B: io_dout <= 1;
+				  'h2B: io_dout <= {HPS_BUS[47:46],4'b0010};
 				  'h2F: io_dout <= 1;
 				  'h32: io_dout <= gamma_bus[21];
 				  'h36: begin io_dout <= info_n; info_n <= 0; end
--- a/sys/shadowmask.sv
+++ b/sys/shadowmask.sv
@@ -9,6 +9,7 @@ module shadowmask
 	input      [23:0] din,
 	input             hs_in,vs_in,
 	input             de_in,
+	input             brd_in,
 	input             enable,

 	output reg [23:0] dout,
@@ -32,10 +33,13 @@ always @(posedge clk) begin
 	reg [3:0] vindex;
 	reg [4:0] hmax2;
 	reg [4:0] vmax2;
-	reg old_hs, old_vs;
+	reg [11:0] pcnt,pde;
+	reg old_hs, old_vs, old_brd;
+	reg next_v;

 	old_hs <= hs_in;
 	old_vs <= vs_in;
+	old_brd<= brd_in;

 	// hcount and vcount counts pixel rows and columns
 	// hindex and vindex half the value of the counters for double size patterns
@@ -49,13 +53,18 @@ always @(posedge clk) begin
 	hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x;
 	vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x;

-	hcount <= hcount + 1'b1;
-	if (hcount == hmax2) hcount <= 0;
+	pcnt <= pcnt+1'd1;
+	if(old_brd && ~brd_in) pde <= pcnt-4'd3;

-	if((old_vs && ~vs_in)) vcount <= 0;
+	hcount <= hcount+1'b1;
+	if(hcount == hmax2 || pde == pcnt) hcount <= 0;
+
+	if(~old_brd && brd_in) next_v <= 1;
+	if(old_vs && ~vs_in) vcount <= 0;
 	if(old_hs && ~hs_in) begin
-		vcount <= vcount + 1'b1;
-		hcount <= 0;
+		vcount <= vcount + next_v;
+		next_v <= 0;
+		pcnt   <= 0;
 		if (vcount == vmax2) vcount <= 0;
 	end
 end
--- a/sys/sys_top.v
+++ b/sys/sys_top.v
@@ -295,7 +295,7 @@ reg [31:0] cfg_custom_p2;
 reg  [4:0] vol_att;
 initial vol_att = 5'b11111;

-reg  [6:0] coef_addr;
+reg  [8:0] coef_addr;
 reg  [8:0] coef_data;
 reg        coef_wr = 0;

@@ -367,6 +367,7 @@ always@(posedge clk_sys) begin
 			end
 		end
 		else begin
+			cnt <= cnt + 1'd1;
 			if(cmd == 1) begin
 				cfg <= io_din;
 				cfg_set <= 1;
@@ -374,7 +375,6 @@ always@(posedge clk_sys) begin
 			end
 			if(cmd == 'h20) begin
 				cfg_set <= 0;
-				cnt <= cnt + 1'd1;
 				if(cnt<8) begin
 					case(cnt[2:0])
 						0: if(WIDTH  != io_din[11:0]) WIDTH  <= io_din[11:0];
@@ -406,7 +406,6 @@ always@(posedge clk_sys) begin
 				end
 			end
 			if(cmd == 'h2F) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
 					1: LFB_BASE[15:0]  <= io_din[15:0];
@@ -423,12 +422,14 @@ always@(posedge clk_sys) begin
 			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
 			if(cmd == 'h26) vol_att <= io_din[4:0];
 			if(cmd == 'h27) VSET <= io_din[11:0];
-			if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
+			if(cmd == 'h2A) begin
+				if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[8:0]};
+				else coef_addr <= io_din[8:0];
+			end
 			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
 			if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
 			if(cmd == 'h38) vs_line <= io_din[11:0];
 			if(cmd == 'h39) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					 0: acx_att          <= io_din[4:0];
 					 1: aflt_rate[15:0]  <= io_din;
@@ -448,7 +449,6 @@ always@(posedge clk_sys) begin
 				endcase
 			end
 			if(cmd == 'h3A) begin
-				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
 					 0: arc1x <= io_din[12:0];
 					 1: arc1y <= io_din[12:0];
@@ -456,7 +456,6 @@ always@(posedge clk_sys) begin
 					 3: arc2y <= io_din[12:0];
 				endcase
 			end
-
 `ifndef MISTER_DEBUG_NOHDMI
 			if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din};
 `endif
@@ -626,7 +625,7 @@ wire  [15:0] vbuf_byteenable;
 wire         vbuf_write;

 wire  [23:0] hdmi_data;
-wire         hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
+wire         hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
 wire         freeze;

 `ifndef MISTER_DEBUG_NOHDMI
@@ -642,6 +641,7 @@ ascal
 		.PALETTE2("false"),
 	`endif
 `endif
+	.FRAC(6),
 	.N_DW(128),
 	.N_AW(28)
 )
@@ -675,6 +675,7 @@ ascal
 	.o_vs     (hdmi_vs),
 	.o_de     (hdmi_de),
 	.o_vbl    (hdmi_vbl),
+	.o_brd    (hdmi_brd),
 	.o_lltune (lltune),
 	.htotal   (WIDTH + HFP + HBP + HS),
 	.hsstart  (WIDTH + HFP),
@@ -1057,8 +1058,6 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c
 );

 `ifndef MISTER_DEBUG_NOHDMI
-wire [23:0] hdmi_data_sl;
-wire        hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;

 `ifdef MISTER_FB
 reg dis_output;
@@ -1071,22 +1070,6 @@ end
 wire dis_output = 0;
 `endif

-scanlines #(1) HDMI_scanlines
-(
-	.clk(clk_hdmi),
-
-	.scanlines(LFB_EN ? 2'b00 : scanlines),
-	.din(dis_output ? 24'd0 : hdmi_data),
-	.hs_in(hdmi_hs),
-	.vs_in(hdmi_vs),
-	.de_in(hdmi_de),
-	
-	.dout(hdmi_data_sl),
-	.hs_out(hdmi_hs_sl),
-	.vs_out(hdmi_vs_sl),
-	.de_out(hdmi_de_sl)
-);
-
 wire [23:0] hdmi_data_mask;
 wire        hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;

@@ -1101,10 +1084,11 @@ shadowmask HDMI_shadowmask
 	.cmd_wr(shadowmask_wr),
 	.cmd_in(shadowmask_data),

-	.din(hdmi_data_sl),
-	.hs_in(hdmi_hs_sl),
-	.vs_in(hdmi_vs_sl),
-	.de_in(hdmi_de_sl),
+	.din(dis_output ? 24'd0 : hdmi_data),
+	.hs_in(hdmi_hs),
+	.vs_in(hdmi_vs),
+	.de_in(hdmi_de),
+	.brd_in(hdmi_brd),
 	.enable(~LFB_EN),

 	.dout(hdmi_data_mask),
@@ -1496,12 +1480,12 @@ wire  [6:0] user_out, user_in;

 assign clk_ihdmi= clk_vid;
 assign ce_hpix  = ce_pix;
-assign hr_out   = r_out;
-assign hg_out   = g_out;
-assign hb_out   = b_out;
-assign hhs_fix  = hs_fix;
-assign hvs_fix  = vs_fix;
-assign hde_emu  = de_emu;
+assign hr_out   = vga_data_sl[23:16];
+assign hg_out   = vga_data_sl[15:8];
+assign hb_out   = vga_data_sl[7:0];
+assign hhs_fix  = vga_hs_sl;
+assign hvs_fix  = vga_vs_sl;
+assign hde_emu  = vga_de_sl;

 wire uart_dtr;
 wire uart_dsr;
@@ -1542,7 +1526,7 @@ emu emu
 (
 	.CLK_50M(FPGA_CLK2_50),
 	.RESET(reset),
-	.HPS_BUS({f1, HDMI_TX_VS, 
+	.HPS_BUS({scanlines,f1, HDMI_TX_VS, 
 				 clk_100m, clk_ihdmi,
 				 ce_hpix, hde_emu, hhs_fix, hvs_fix, 
 				 io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),