mirror of
https://github.com/MiSTer-devel/Intv_MiSTer.git
synced 2026-05-17 03:03:52 +00:00
77edfa2fc2
I got this message on every build, so I assume it's known: Critical Warning (18010): Register emu:emu|intv_core:intv_core|jlp:i_jlp|crccount[4] will power up to High
473 lines
12 KiB
Systemverilog
473 lines
12 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE,
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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output LED_USER, // 1 - ON, 0 - OFF.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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//////////////////////////////////////////////////////////////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_F1 = 0;
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assign AUDIO_S = 1;
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assign AUDIO_MIX = 0;
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assign LED_USER = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign HDMI_BOB_DEINT = 0;
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assign VGA_SCALER= 0;
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assign VGA_DISABLE = 0;
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assign BUTTONS = 0;
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//////////////////////////////////////////////////////////////////
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wire [1:0] ar = status[4:3];
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wire [12:0] arx = (!ar) ? 12'd760 : (ar - 1'd1);
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wire [12:0] ary = (!ar) ? 12'd561 : 12'd0;
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`include "build_id.v"
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// Status Bit Map:
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// Upper Lower
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// 0 1 2 3 4 5 6
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// 01234567890123456789012345678901 23456789012345678901234567890123
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// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
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// XX XXXXXXXXXXXXXXXXXXXXXX
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localparam CONF_STR = {
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"Intellivision;;",
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"-;",
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"FS,ROMINTBIN;",
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"O58,MAP,Auto,0,1,2,3,4,5,6,7,8,9;",
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"OMN,Format,Auto,Raw,Intellicart;",
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"O9,ECS,Off,On;",
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"OA,Voice,On,Off;",
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"OO,JLP Acceleration,On,Off;",
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"d1S0,SAV,JLP RW FLASH:;",
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"O34,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"OCE,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"d0OH,Vertical Crop,Disabled,216p(5x);",
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"d0OIL,Crop Offset,0,2,4,8,10,12,-12,-10,-8,-6,-4,-2;",
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"OFG,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
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"OB,Video standard,NTSC,PAL;",
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"O1,Swap Joystick,Off,On;",
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"-;",
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"R0,Reset;",
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"J1,Action Up,Action Left,Action Right,Clear,Enter,0,1,2,3,4,5,6,7,8,9;",
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"V,v",`BUILD_DATE
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};
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wire forced_scandoubler;
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wire [1:0] buttons;
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wire [63:0] status;
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wire [10:0] ps2_key;
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wire ioctl_download;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire ioctl_wait;
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wire img_mounted;
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wire [63:0] img_size;
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wire img_readonly;
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wire [31:0] sd_lba;
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din;
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wire sd_buff_wr;
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wire [31:0] joystick_0,joystick_1;
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wire [15:0] joystick_analog_l,joystick_analog_r;
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wire [21:0] gamma_bus;
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wire clk_sys,pll_locked;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1),
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.joystick_l_analog_0(joystick_analog_l),
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.joystick_r_analog_0(joystick_analog_r),
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.forced_scandoubler(forced_scandoubler),
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.gamma_bus(gamma_bus),
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.buttons(buttons),
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.status(status),
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.status_menumask(menumask), //en216p),
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.ioctl_download(ioctl_download),
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.ioctl_index(ioctl_index),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wait(ioctl_wait),
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.img_mounted(img_mounted),
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.img_size(img_size),
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.img_readonly(img_readonly),
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.sd_lba('{sd_lba}),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din('{sd_buff_din}),
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.sd_buff_wr(sd_buff_wr),
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.ps2_key(ps2_key)
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);
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wire pal = status[11];
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wire swap = status[1];
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wire ecs = status[9];
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wire ivoice =!status[10];
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wire jlp =!status[24];
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wire [1:0] menumask = {jlp,en216p};
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wire [3:0] mapp = status[8:5];
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wire [1:0] format = status[23:22];
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wire [7:0] CORE_R,CORE_G,CORE_B;
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wire CORE_HS,CORE_VS,CORE_DE,CORE_CE;
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wire CORE_HBLANK,CORE_VBLANK;
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intv_core intv_core
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(
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.clksys(clk_sys),
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.pll_locked(pll_locked),
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.pal(pal),
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.swap(swap),
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.ecs(ecs),
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.ivoice(ivoice),
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.jlp(jlp),
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.mapp(mapp),
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.format(format),
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.reset(RESET | status[0]),
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.vga_clk(CLK_VIDEO),
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.vga_ce(CORE_CE),
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.vga_r(CORE_R),
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.vga_g(CORE_G),
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.vga_b(CORE_B),
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.vga_hs(CORE_HS),
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.vga_vs(CORE_VS),
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.vga_de(CORE_DE),
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.vga_vb(CORE_VBLANK),
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.vga_hb(CORE_HBLANK),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1),
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.joystick_analog_0(joystick_analog_l),
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.joystick_analog_1(joystick_analog_r),
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.ps2_key(ps2_key),
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.ioctl_download(ioctl_download),
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.ioctl_index(ioctl_index),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wait(ioctl_wait),
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.img_mounted(img_mounted),
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.img_size(img_size),
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.img_readonly(img_readonly),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.audio_l(AUDIO_L),
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.audio_r(AUDIO_R)
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);
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wire [2:0] scale = status[14:12];
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wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
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assign VGA_SL = sl[1:0];
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wire vcrop_en = status[17];
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wire [3:0] vcopt = status[21:18];
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reg en216p;
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reg [4:0] voff;
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always @(posedge CLK_VIDEO) begin
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en216p <= ((HDMI_WIDTH == 1920) && (HDMI_HEIGHT == 1080) && !forced_scandoubler && !scale);
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voff <= (vcopt < 6) ? {vcopt,1'b0} : ({vcopt,1'b0} - 5'd24);
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end
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wire vga_de;
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video_freak video_freak
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(
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.*,
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.VGA_DE_IN(vga_de),
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.ARX((!ar) ? arx : (ar - 1'd1)),
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.ARY((!ar) ? ary : 12'd0),
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.CROP_SIZE((en216p & vcrop_en) ? 10'd216 : 10'd0),
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.CROP_OFF(voff),
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.SCALE(status[16:15])
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);
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video_mixer #(.LINE_LENGTH(520), .GAMMA(1)) video_mixer
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(
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.scandoubler(scale || forced_scandoubler),
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.hq2x(scale==1),
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.gamma_bus(gamma_bus),
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.CLK_VIDEO(CLK_VIDEO),
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.ce_pix(CORE_CE),
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.R(CORE_R),
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.G(CORE_G),
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.B(CORE_B),
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.HSync(CORE_HS),
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.VSync(CORE_VS),
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.HBlank(CORE_HBLANK),
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.VBlank(CORE_VBLANK),
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.CE_PIXEL(CE_PIXEL),
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.VGA_R(VGA_R),
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.VGA_G(VGA_G),
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.VGA_B(VGA_B),
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.VGA_VS(VGA_VS),
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.VGA_HS(VGA_HS),
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.VGA_DE(vga_de)
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);
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pll pll
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(
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.refclk(CLK_50M),
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll),
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.locked(pll_locked),
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.outclk_0(clk_sys)
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);
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wire [63:0] reconfig_to_pll;
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wire [63:0] reconfig_from_pll;
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wire cfg_waitrequest;
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reg cfg_write;
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reg [5:0] cfg_address;
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reg [31:0] cfg_data;
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pll_cfg pll_cfg
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(
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.mgmt_clk(CLK_50M),
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.mgmt_reset(0),
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.mgmt_waitrequest(cfg_waitrequest),
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.mgmt_read(0),
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.mgmt_readdata(),
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.mgmt_write(cfg_write),
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.mgmt_address(cfg_address),
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.mgmt_writedata(cfg_data),
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.reconfig_to_pll(reconfig_to_pll),
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.reconfig_from_pll(reconfig_from_pll)
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);
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// NTSC : 3.579545MHz * 12 = 42.95454MHz
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// PAL : 4MHz * 12 = 48MHz
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// STIC : CLK * 12
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// IVOICE : CLK
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reg tv_reset = 0;
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always @(posedge CLK_50M) begin
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reg pald = 0, pald2 = 0;
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reg [2:0] state = 0;
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pald <= pal;
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pald2 <= pald;
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cfg_write <= 0;
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if(pald2 != pald) state <= 1;
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if(!cfg_waitrequest) begin
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if(state) state<=state+1'd1;
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case(state)
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0: tv_reset <= 0;
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1: begin
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tv_reset <= 1;
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cfg_address <= 0; // Waitrequest mode
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cfg_data <= 0;
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cfg_write <= 1;
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end
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2: begin
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cfg_address <= 3; // N counter
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cfg_data <= 32'h00010000;
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cfg_write <= 1;
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end
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3: begin
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cfg_address <= 4; // M counter
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cfg_data <= 32'h00000404;
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cfg_write <= 1;
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end
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4: begin
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cfg_address <= 5; // C0 counter
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cfg_data <= pald2 ? 32'h00020504 : 32'h00000505;
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cfg_write <= 1;
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end
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5: begin
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cfg_address <= 7; // M frac
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cfg_data <= pald2 ? 32'hA3D709E8 : 32'h9745BF27;
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cfg_write <= 1;
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end
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6: begin
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cfg_address <= 2; // Start reconf
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cfg_data <= 0;
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cfg_write <= 1;
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end
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endcase
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end
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end
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endmodule
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