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https://github.com/MiSTer-devel/Intv_MiSTer.git
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Sys Update and 20250903 Release
I got this message on every build, so I assume it's known: Critical Warning (18010): Register emu:emu|intv_core:intv_core|jlp:i_jlp|crccount[4] will power up to High
This commit is contained in:
Brendan Saricks
5
Intv.qsf
5
Intv.qsf
@@ -13,7 +13,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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@@ -60,4 +60,5 @@ set_global_assignment -name SEED 1
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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4
intv.sv
4
intv.sv
@@ -54,6 +54,8 @@ module emu
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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output LED_USER, // 1 - ON, 0 - OFF.
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output [1:0] LED_POWER,
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@@ -153,6 +155,8 @@ assign LED_USER = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign HDMI_BOB_DEINT = 0;
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assign VGA_SCALER= 0;
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assign VGA_DISABLE = 0;
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BIN
releases/Intellivision_20250903.rbf
Normal file
BIN
releases/Intellivision_20250903.rbf
Normal file
Binary file not shown.
@@ -99,6 +99,11 @@ generate
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assign G = {RGB_fix[7:4],RGB_fix[7:4]};
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assign B = {RGB_fix[3:0],RGB_fix[3:0]};
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end
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else if(DW == 18) begin
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assign R = {RGB_fix[17:12],RGB_fix[17:16]};
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assign G = {RGB_fix[11: 6],RGB_fix[11:10]};
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assign B = {RGB_fix[ 5: 0],RGB_fix[ 5: 4]};
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end
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else begin // 24
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assign R = RGB_fix[23:16];
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assign G = RGB_fix[15:8];
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221
sys/ascal.vhd
221
sys/ascal.vhd
@@ -103,7 +103,7 @@ USE ieee.numeric_std.ALL;
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-- DOWNSCALE : True=Support downscaling False=Downscaling disabled
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-- BYTESWAP : Little/Big endian byte swap
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-- FRAC : Fractional bits, subpixel resolution
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-- OHRES : Max. output horizontal resolution. Must be a power of two.
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-- OHRES : Max. output horizontal resolution. 1024, 2048, 2304, 2560, 4096
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-- (Used for sizing line buffers)
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-- IHRES : Max. input horizontal resolution. Must be a power of two.
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-- (Used for sizing line buffers)
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@@ -125,7 +125,7 @@ ENTITY ascal IS
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ADAPTIVE : boolean := true;
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DOWNSCALE_NN : boolean := false;
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FRAC : natural RANGE 4 TO 8 :=4;
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OHRES : natural RANGE 1 TO 4096 :=2048;
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OHRES : natural RANGE 1 TO 4096 :=2304;
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IHRES : natural RANGE 1 TO 2048 :=2048;
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N_DW : natural RANGE 64 TO 128 := 128;
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N_AW : natural RANGE 8 TO 32 := 32;
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@@ -201,9 +201,10 @@ ENTITY ascal IS
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i_vdmax : OUT natural RANGE 0 TO 4095;
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-- Output video parameters
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run : IN std_logic :='1'; -- 1=Enable output image. 0=No image
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freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes
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mode : IN unsigned(4 DOWNTO 0);
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run : IN std_logic :='1'; -- 1=Enable output image. 0=No image
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freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes
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mode : IN unsigned(4 DOWNTO 0);
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bob_deint : IN std_logic := '0';
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-- SYNC |_________________________/"""""""""\_______|
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-- DE |""""""""""""""""""\________________________|
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-- RGB | <#IMAGE#> ^HDISP |
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@@ -222,6 +223,7 @@ ENTITY ascal IS
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vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp
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vrr : IN std_logic := '0';
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vrrmax : IN natural RANGE 0 TO 4095 := 0;
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swblack : IN std_logic := '0'; -- will output 3 black frame on every resolution switch
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-- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp
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format : IN unsigned(1 DOWNTO 0) :="01";
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@@ -256,6 +258,9 @@ ENTITY ascal IS
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BEGIN
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ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure;
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ASSERT OHRES = 1024 OR OHRES = 2048 OR OHRES = 2304 OR
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OHRES = 2560 OR OHRES = 4096 REPORT "OHRES" SEVERITY failure;
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END ENTITY ascal;
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@@ -287,10 +292,39 @@ ARCHITECTURE rtl OF ascal IS
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END IF;
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END FUNCTION to_std_logic;
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----------------------------------------------------------
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FUNCTION ohres_h(CONSTANT r : natural) RETURN natural IS
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BEGIN
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CASE r IS
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WHEN 1024 => RETURN 1024;
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WHEN 2048 => RETURN 2048;
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WHEN OTHERS => RETURN 4096;
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END CASE;
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END FUNCTION;
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FUNCTION ohres_l(CONSTANT r : natural) RETURN natural IS
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BEGIN
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CASE r IS
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WHEN 1024 => RETURN 1024;
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WHEN 2048 | 2304 | 2560 => RETURN 2048;
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WHEN OTHERS => RETURN 4096;
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END CASE;
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END FUNCTION;
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FUNCTION ohres_m(CONSTANT r : natural) RETURN natural IS
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BEGIN
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CASE r IS
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WHEN 1024 | 2048 | 2304 => RETURN 256;
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WHEN OTHERS => RETURN 512;
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END CASE;
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END FUNCTION;
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CONSTANT OHRESH : natural := ohres_h(OHRES);
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CONSTANT OHRESL : natural := ohres_l(OHRES);
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CONSTANT OHRESM : natural := ohres_m(OHRES);
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----------------------------------------------------------
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CONSTANT NB_BURST : natural :=ilog2(N_BURST);
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CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits
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CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length
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CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits
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CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length
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----------------------------------------------------------
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TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0);
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@@ -318,6 +352,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
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SIGNAL i_ppix : type_pix;
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SIGNAL i_freeze : std_logic;
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SIGNAL i_bob_deint : std_logic;
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SIGNAL i_count : unsigned(2 DOWNTO 0);
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SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12;
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SIGNAL i_hrsize,i_vrsize : uint12;
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@@ -333,6 +368,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL i_de_delay : natural RANGE 0 TO 31;
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SIGNAL i_intercnt : natural RANGE 0 TO 3;
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SIGNAL i_inter,i_half,i_flm : std_logic;
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SIGNAL i_wfl : std_logic_vector(2 DOWNTO 0);
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SIGNAL i_write,i_wreq,i_alt,i_line,i_wline,i_wline_mem : std_logic;
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SIGNAL i_walt,i_walt_mem,i_wreq_mem : std_logic;
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SIGNAL i_wdelay : natural RANGE 0 TO 7;
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@@ -362,7 +398,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL i_hacc,i_vacc : uint13;
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SIGNAL i_hdown,i_vdown : std_logic;
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SIGNAL i_divcpt : natural RANGE 0 TO 36;
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SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1;
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SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRESH-1;
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SIGNAL i_lwr,i_bil : std_logic;
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SIGNAL i_ldw,i_ldrm : type_pix;
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SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix;
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@@ -410,6 +446,8 @@ ARCHITECTURE rtl OF ascal IS
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-- Output
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SIGNAL o_run : std_logic;
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SIGNAL o_freeze : std_logic;
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SIGNAL o_bob_deint : std_logic;
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SIGNAL o_iwfl : std_logic_vector(2 DOWNTO 0);
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SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
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SIGNAL o_format : unsigned(5 DOWNTO 0);
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SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
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@@ -456,13 +494,21 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL o_reset_na : std_logic;
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SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1);
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ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check";
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SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1);
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SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRESL-1);
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SIGNAL o_linf0,o_linf1,o_linf2,o_linf3 : arr_pix(0 TO OHRESM-1);
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ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check";
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SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRES-1;
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SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix;
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ATTRIBUTE ramstyle OF o_linf0 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_linf1 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_linf2 : SIGNAL IS "no_rw_check";
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ATTRIBUTE ramstyle OF o_linf3 : SIGNAL IS "no_rw_check";
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SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRESH-1;
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SIGNAL o_ldr0,o_ldr1,o_ldr2,o_ldr3,o_ldw : type_pix;
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SIGNAL o_ler0,o_ler1,o_ler2,o_ler3 : type_pix;
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SIGNAL o_lex0,o_lex1,o_lex2,o_lex3 : std_logic;
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SIGNAL o_wr : unsigned(3 DOWNTO 0);
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SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3,o_vcpt2 : uint12;
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SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12;
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@@ -472,7 +518,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL o_hfrac : arr_frac(0 TO 9);
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ATTRIBUTE ramstyle OF o_hfrac : SIGNAL IS "logic"; -- avoid blockram shift register
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SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
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SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRESH-1;
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SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 11);
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SIGNAL o_hsp,o_vss : std_logic;
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SIGNAL o_vcarrym,o_prim : boolean;
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@@ -490,8 +536,9 @@ ARCHITECTURE rtl OF ascal IS
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TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15;
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SIGNAL o_off : arr_uint4(0 TO 2);
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SIGNAL o_bibu : std_logic :='0';
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SIGNAL o_dcptv : arr_uint12(1 TO 14);
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SIGNAL o_dcpt : uint12;
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SIGNAL o_dcptv : arr_uint12(13 TO 14);
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SIGNAL o_dcpt_clr, o_dcpt_inc : std_logic;
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SIGNAL o_dcptv_clr, o_dcptv_inc : std_logic_vector(1 TO 12);
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SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix;
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SIGNAL o_hpixq : arr_pixq(2 TO 8);
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ATTRIBUTE ramstyle OF o_hpixq : SIGNAL IS "logic"; -- avoid blockram shift register
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@@ -499,7 +546,6 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL o_vpix_outer : arr_pix(0 TO 2);
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SIGNAL o_vpix_inner : arr_pix(0 TO 6);
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SIGNAL o_vpe : std_logic;
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SIGNAL o_div : arr_div(0 TO 2); --uint12;
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SIGNAL o_dir : arr_frac(0 TO 2);
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@@ -510,6 +556,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL o_divrun : std_logic;
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SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0);
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SIGNAL o_vacptl : unsigned(1 DOWNTO 0);
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signal o_newres : integer range 0 to 3;
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-----------------------------------------------------------------------------
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FUNCTION shift_ishift(shift : unsigned(0 TO 119);
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@@ -528,11 +575,11 @@ ARCHITECTURE rtl OF ascal IS
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END CASE;
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END FUNCTION;
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FUNCTION shift_ipack( i_dw : unsigned(N_DW-1 DOWNTO 0);
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acpt : natural RANGE 0 TO 15;
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shift : unsigned(0 TO 119);
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pix : type_pix;
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format : unsigned(1 DOWNTO 0)) RETURN unsigned IS
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FUNCTION shift_ipack(i_dw : unsigned(N_DW-1 DOWNTO 0);
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acpt : natural RANGE 0 TO 15;
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shift : unsigned(0 TO 119);
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pix : type_pix;
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format : unsigned(1 DOWNTO 0)) RETURN unsigned IS
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VARIABLE dw : unsigned(N_DW-1 DOWNTO 0);
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BEGIN
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dw:=i_dw;
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@@ -1130,6 +1177,7 @@ BEGIN
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i_pushhead<='0';
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i_eol<='0'; -- End Of Line
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i_freeze <=freeze; -- <ASYNC>
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i_bob_deint <= bob_deint;
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i_iauto<=iauto; -- <ASYNC>
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i_wreq<='0';
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i_wr<='0';
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@@ -1190,11 +1238,13 @@ BEGIN
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i_vcpt<=0;
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IF i_inter='1' AND i_flm='0' AND i_half='0' AND INTER THEN
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i_line<='1';
|
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i_wfl(o_ibuf1) <= '0';
|
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i_adrsi<=to_unsigned(N_BURST * i_hburst,32) +
|
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to_unsigned(N_BURST * to_integer(
|
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unsigned'("00") & to_std_logic(HEADER)),32);
|
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ELSE
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i_line<='0';
|
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i_wfl(o_ibuf0) <= '1';
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i_adrsi<=to_unsigned(N_BURST * to_integer(
|
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unsigned'("00") & to_std_logic(HEADER)),32);
|
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END IF;
|
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@@ -1204,8 +1254,8 @@ BEGIN
|
||||
i_vcpt>=i_vmin AND i_vcpt<=i_vmax);
|
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|
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-- Detects end of frame for triple buffering.
|
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i_endframe0<=i_vs AND (NOT i_inter OR i_flm);
|
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i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm);
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i_endframe0<=i_vs AND (NOT i_inter OR i_flm OR i_bob_deint);
|
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i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm OR i_bob_deint);
|
||||
|
||||
i_vss<=to_std_logic(i_vcpt>=i_vmin AND i_vcpt<=i_vmax);
|
||||
|
||||
@@ -1453,12 +1503,12 @@ BEGIN
|
||||
-- Push pixels to downscaling line buffer
|
||||
i_lwr<=i_hnp4 AND i_ven5 AND i_pce;
|
||||
IF i_lwr='1' THEN
|
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i_lwad<=(i_lwad+1) MOD OHRES;
|
||||
i_lwad<=(i_lwad+1) MOD OHRESH;
|
||||
END IF;
|
||||
i_ldw<=i_hpix;
|
||||
|
||||
IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN
|
||||
i_lrad<=(i_lrad+1) MOD OHRES;
|
||||
i_lrad<=(i_lrad+1) MOD OHRESH;
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------
|
||||
@@ -1817,7 +1867,7 @@ BEGIN
|
||||
VARIABLE shift_v : unsigned(0 TO N_DW+15);
|
||||
VARIABLE hpix_v : type_pix;
|
||||
VARIABLE hcarry_v,vcarry_v : boolean;
|
||||
VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1;
|
||||
VARIABLE dif_v : natural RANGE 0 TO 8*OHRESH-1;
|
||||
VARIABLE off_v : natural RANGE 0 TO 15;
|
||||
BEGIN
|
||||
IF o_reset_na='0' THEN
|
||||
@@ -1862,6 +1912,8 @@ BEGIN
|
||||
o_isync <= '0';
|
||||
o_isync2 <= o_isync;
|
||||
o_freeze <= freeze;
|
||||
o_bob_deint <= bob_deint;
|
||||
o_iwfl <= i_wfl;
|
||||
o_inter <=i_inter; -- <ASYNC>
|
||||
o_iendframe0<=i_endframe0; -- <ASYNC>
|
||||
o_iendframe02<=o_iendframe0;
|
||||
@@ -1890,6 +1942,14 @@ BEGIN
|
||||
o_ivsize<=i_vrsize; -- <ASYNC>
|
||||
o_hdown<=i_hdown; -- <ASYNC>
|
||||
o_vdown<=i_vdown; -- <ASYNC>
|
||||
|
||||
IF (o_newres > 0) then
|
||||
o_newres <= o_newres- 1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
IF (swblack = '1' and o_fb_ena = '0' and (o_ihsize /= i_hrsize or o_ivsize /= i_vrsize)) then
|
||||
o_newres <= 3;
|
||||
END IF;
|
||||
|
||||
-- Simultaneous change of input and output framebuffers
|
||||
@@ -2086,7 +2146,26 @@ BEGIN
|
||||
o_read<=o_read_pre AND o_run;
|
||||
o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video
|
||||
|
||||
o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride);
|
||||
----
|
||||
-- When bob deinterlacing we read lines from one buffer (the most current) but we read them twice
|
||||
-- (in contrast to weave deinterlacing where we read each 480p line from alternating buffers)
|
||||
-- To counteract the severe vibrating/motion with bob deinterlacing, we need to offset one field
|
||||
-- by a half-line. This is done by only reading the first line of the 'even' frame once
|
||||
|
||||
IF o_inter='1' AND o_bob_deint='1' THEN
|
||||
IF o_iwfl(o_obuf0)='0' THEN
|
||||
IF o_vacpt=0 OR o_rline='1' THEN
|
||||
o_adrs_pre <= to_integer(o_vacpt) * to_integer(o_stride);
|
||||
ELSE
|
||||
o_adrs_pre <= (to_integer(o_vacpt)-1) * to_integer(o_stride);
|
||||
END IF;
|
||||
ELSE
|
||||
o_adrs_pre <= to_integer(o_vacpt(11 DOWNTO 1) & "0") * to_integer(o_stride);
|
||||
END IF;
|
||||
ELSE
|
||||
o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride);
|
||||
END IF;
|
||||
|
||||
IF o_adrsa='1' THEN
|
||||
IF o_fload=2 THEN
|
||||
o_adrs<=to_unsigned(o_hbcpt * N_BURST,32);
|
||||
@@ -2103,6 +2182,9 @@ BEGIN
|
||||
------------------------------------------------------
|
||||
-- Copy from buffered memory to pixel lines
|
||||
o_sh<='0';
|
||||
o_dcpt_clr <= '0';
|
||||
o_dcpt_inc <= '0';
|
||||
|
||||
CASE o_copy IS
|
||||
WHEN sWAIT =>
|
||||
o_copyv(0)<='0';
|
||||
@@ -2121,7 +2203,7 @@ BEGIN
|
||||
o_hacc <=o_hacc_ini;
|
||||
o_hacc_next<=o_hacc_ini + 2*o_ihsize;
|
||||
o_hacpt <=x"000";
|
||||
o_dcpt<=0;
|
||||
o_dcpt_clr <= '1';
|
||||
o_dshi<=2;
|
||||
o_acpt<=0;
|
||||
o_first<='1';
|
||||
@@ -2149,17 +2231,17 @@ BEGIN
|
||||
WHEN sCOPY =>
|
||||
-- dshi : Force shift first two or three pixels of each line
|
||||
IF o_dshi=0 THEN
|
||||
dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
|
||||
IF dif_v>=4*OHRES THEN
|
||||
dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRESH)) MOD (8*OHRESH);
|
||||
IF dif_v>=4*OHRESH THEN
|
||||
o_hacc<=o_hacc_next;
|
||||
o_hacc_next<=o_hacc_next + 2*o_ihsize;
|
||||
hcarry_v:=false;
|
||||
ELSE
|
||||
o_hacc<=dif_v;
|
||||
o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
|
||||
o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRESH)) MOD (4*OHRESH);
|
||||
hcarry_v:=true;
|
||||
END IF;
|
||||
o_dcpt<=(o_dcpt+1) MOD 4096;
|
||||
o_dcpt_inc <= '1';
|
||||
ELSE
|
||||
o_dshi<=o_dshi-1;
|
||||
hcarry_v:=false;
|
||||
@@ -2219,6 +2301,9 @@ BEGIN
|
||||
hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8),
|
||||
b=>o_fb_pal_dr(7 DOWNTO 0));
|
||||
END IF;
|
||||
IF (o_newres > 0) then
|
||||
hpix_v := (others => (others => '0'));
|
||||
END IF;
|
||||
o_hpix0<=hpix_v;
|
||||
o_hpix1<=o_hpix0;
|
||||
o_hpix2<=o_hpix1;
|
||||
@@ -2526,13 +2611,19 @@ BEGIN
|
||||
o_hfrac(2 TO 9) <= o_hfrac(1 TO 8);
|
||||
|
||||
o_copyv(1 TO 14)<=o_copyv(0 TO 13);
|
||||
o_dcptv_clr(1 TO 12)<=o_dcpt_clr & o_dcptv_clr(1 TO 11);
|
||||
o_dcptv_inc(1 TO 12)<=o_dcpt_inc & o_dcptv_inc(1 TO 11);
|
||||
|
||||
o_dcptv(1)<=o_dcpt;
|
||||
IF o_dcptv(1)>=o_hsize THEN
|
||||
o_copyv(2)<='0';
|
||||
IF o_dcptv_clr(12)='1' THEN
|
||||
o_dcptv(13) <= 0;
|
||||
ELSIF o_dcptv_inc(12)='1' THEN
|
||||
o_dcptv(13) <= (o_dcptv(13) + 1) MOD OHRESH;
|
||||
END IF;
|
||||
o_dcptv(14)<=o_dcptv(13);
|
||||
|
||||
IF o_dcptv(13)>=o_hsize THEN
|
||||
o_copyv(14)<='0';
|
||||
END IF;
|
||||
o_dcptv(2)<=o_dcptv(1) MOD OHRES;
|
||||
o_dcptv(3 TO 14)<=o_dcptv(2 TO 13);
|
||||
|
||||
-- C2
|
||||
o_hpixq(2)<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0);
|
||||
@@ -2625,17 +2716,39 @@ BEGIN
|
||||
OLBUF:PROCESS(o_clk) IS
|
||||
BEGIN
|
||||
IF rising_edge(o_clk) THEN
|
||||
-----------------------------------------------
|
||||
-- WRITES
|
||||
IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF;
|
||||
IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF;
|
||||
IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF;
|
||||
IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF;
|
||||
IF o_wr(0)='1' AND o_wadl < OHRESL THEN o_line0(o_wadl MOD OHRESL)<=o_ldw; END IF;
|
||||
IF o_wr(1)='1' AND o_wadl < OHRESL THEN o_line1(o_wadl MOD OHRESL)<=o_ldw; END IF;
|
||||
IF o_wr(2)='1' AND o_wadl < OHRESL THEN o_line2(o_wadl MOD OHRESL)<=o_ldw; END IF;
|
||||
IF o_wr(3)='1' AND o_wadl < OHRESL THEN o_line3(o_wadl MOD OHRESL)<=o_ldw; END IF;
|
||||
IF OHRES = 2304 OR OHRES = 2560 THEN
|
||||
IF o_wr(0)='1' AND o_wadl >= OHRESL THEN o_linf0(o_wadl MOD OHRESM)<=o_ldw; END IF;
|
||||
IF o_wr(1)='1' AND o_wadl >= OHRESL THEN o_linf1(o_wadl MOD OHRESM)<=o_ldw; END IF;
|
||||
IF o_wr(2)='1' AND o_wadl >= OHRESL THEN o_linf2(o_wadl MOD OHRESM)<=o_ldw; END IF;
|
||||
IF o_wr(3)='1' AND o_wadl >= OHRESL THEN o_linf3(o_wadl MOD OHRESM)<=o_ldw; END IF;
|
||||
END IF;
|
||||
|
||||
-----------------------------------------------
|
||||
-- READS
|
||||
o_ldr0<=o_line0(o_radl0);
|
||||
o_ldr1<=o_line1(o_radl1);
|
||||
o_ldr2<=o_line2(o_radl2);
|
||||
o_ldr3<=o_line3(o_radl3);
|
||||
o_ldr0<=o_line0(o_radl0 MOD OHRESL);
|
||||
o_ldr1<=o_line1(o_radl1 MOD OHRESL);
|
||||
o_ldr2<=o_line2(o_radl2 MOD OHRESL);
|
||||
o_ldr3<=o_line3(o_radl3 MOD OHRESL);
|
||||
|
||||
IF OHRES = 2304 OR OHRES = 2560 THEN
|
||||
o_ler0<=o_linf0(o_radl0 MOD OHRESM);
|
||||
o_ler1<=o_linf1(o_radl1 MOD OHRESM);
|
||||
o_ler2<=o_linf2(o_radl2 MOD OHRESM);
|
||||
o_ler3<=o_linf3(o_radl3 MOD OHRESM);
|
||||
END IF;
|
||||
|
||||
o_lex0 <= to_std_logic(o_radl0 >= OHRESL);
|
||||
o_lex1 <= to_std_logic(o_radl1 >= OHRESL);
|
||||
o_lex2 <= to_std_logic(o_radl2 >= OHRESL);
|
||||
o_lex3 <= to_std_logic(o_radl3 >= OHRESL);
|
||||
-----------------------------------------------
|
||||
|
||||
END IF;
|
||||
END PROCESS OLBUF;
|
||||
|
||||
@@ -2721,16 +2834,17 @@ BEGIN
|
||||
VSCAL:PROCESS(o_clk) IS
|
||||
VARIABLE pixq_v : arr_pix(0 TO 3);
|
||||
VARIABLE vlumpix_v : type_pix;
|
||||
VARIABLE r1_v, r2_v : natural RANGE 0 TO OHRES-1;
|
||||
VARIABLE r1_v, r2_v : natural RANGE 0 TO OHRESH-1;
|
||||
VARIABLE fracnn_v : std_logic;
|
||||
VARIABLE o_l0_v, o_l1_v, o_l2_v, o_l3_v : type_pix;
|
||||
BEGIN
|
||||
IF rising_edge(o_clk) THEN
|
||||
IF o_ce='1' THEN
|
||||
o_v_hmin_adj<=o_hmin + 5;
|
||||
|
||||
fracnn_v := o_vfrac(o_vfrac'left);
|
||||
r1_v := (o_hcpt - o_v_hmin_adj + OHRES) MOD OHRES;
|
||||
r2_v := (o_hcpt - o_hmin + OHRES) MOD OHRES;
|
||||
r1_v := (o_hcpt - o_v_hmin_adj + OHRESH) MOD OHRESH;
|
||||
r2_v := (o_hcpt - o_hmin + OHRESH) MOD OHRESH;
|
||||
|
||||
-- CYCLE 1 -----------------------------------------
|
||||
-- Read mem
|
||||
@@ -2757,11 +2871,16 @@ BEGIN
|
||||
|
||||
-- CYCLE 2 -----------------------------------------
|
||||
-- Lines reordering
|
||||
IF o_lex0='0' THEN o_l0_v := o_ldr0; ELSE o_l0_v := o_ler0; END IF;
|
||||
IF o_lex1='0' THEN o_l1_v := o_ldr1; ELSE o_l1_v := o_ler1; END IF;
|
||||
IF o_lex2='0' THEN o_l2_v := o_ldr2; ELSE o_l2_v := o_ler2; END IF;
|
||||
IF o_lex3='0' THEN o_l3_v := o_ldr3; ELSE o_l3_v := o_ler3; END IF;
|
||||
|
||||
CASE o_vacptl IS
|
||||
WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3);
|
||||
WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0);
|
||||
WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1);
|
||||
WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2);
|
||||
WHEN "10" => pixq_v:=(o_l0_v,o_l1_v,o_l2_v,o_l3_v);
|
||||
WHEN "11" => pixq_v:=(o_l1_v,o_l2_v,o_l3_v,o_l0_v);
|
||||
WHEN "00" => pixq_v:=(o_l2_v,o_l3_v,o_l0_v,o_l1_v);
|
||||
WHEN OTHERS => pixq_v:=(o_l3_v,o_l0_v,o_l1_v,o_l2_v);
|
||||
END CASE;
|
||||
|
||||
IF fracnn_v = '0' THEN
|
||||
|
||||
@@ -27,7 +27,7 @@
|
||||
// VDNUM 1..10
|
||||
// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
|
||||
//
|
||||
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
|
||||
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=0, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0, STRLEN=$size(CONF_STR)>>3)
|
||||
(
|
||||
input clk_sys,
|
||||
inout [48:0] HPS_BUS,
|
||||
@@ -39,7 +39,7 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
|
||||
output reg [31:0] joystick_3,
|
||||
output reg [31:0] joystick_4,
|
||||
output reg [31:0] joystick_5,
|
||||
|
||||
|
||||
// analog -127..+127, Y: [15:8], X: [7:0]
|
||||
output reg [15:0] joystick_l_analog_0,
|
||||
output reg [15:0] joystick_l_analog_1,
|
||||
@@ -226,14 +226,13 @@ video_calc video_calc
|
||||
.new_vmode(new_vmode),
|
||||
.video_rotated(video_rotated),
|
||||
|
||||
.par_num(byte_cnt[3:0]),
|
||||
.par_num(byte_cnt[4:0]),
|
||||
.dout(vc_dout)
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
localparam STRLEN = $size(CONF_STR)>>3;
|
||||
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
|
||||
localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1;
|
||||
|
||||
wire [7:0] conf_byte;
|
||||
generate
|
||||
@@ -281,7 +280,7 @@ always@(posedge clk_sys) begin : uio_block
|
||||
stflg <= stflg + 1'd1;
|
||||
status_req <= status_in;
|
||||
end
|
||||
|
||||
|
||||
old_upload_req <= ioctl_upload_req;
|
||||
if(~old_upload_req & ioctl_upload_req) upload_req <= 1;
|
||||
|
||||
@@ -502,7 +501,7 @@ always@(posedge clk_sys) begin : uio_block
|
||||
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
|
||||
//Video res.
|
||||
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
|
||||
'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout;
|
||||
|
||||
//RTC
|
||||
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
@@ -523,7 +522,7 @@ always@(posedge clk_sys) begin : uio_block
|
||||
|
||||
//menu mask
|
||||
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
|
||||
|
||||
|
||||
//sdram size set
|
||||
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
|
||||
|
||||
@@ -630,7 +629,7 @@ always@(posedge clk_sys) begin : fio_block
|
||||
reg has_cmd;
|
||||
reg [26:0] addr;
|
||||
reg wr;
|
||||
|
||||
|
||||
ioctl_rd <= 0;
|
||||
ioctl_wr <= wr;
|
||||
wr <= 0;
|
||||
@@ -663,7 +662,7 @@ always@(posedge clk_sys) begin : fio_block
|
||||
FIO_FILE_TX:
|
||||
begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
case(cnt)
|
||||
0: if(io_din[7:0] == 8'hAA) begin
|
||||
ioctl_addr <= 0;
|
||||
ioctl_upload <= 1;
|
||||
@@ -872,7 +871,7 @@ module video_calc
|
||||
input new_vmode,
|
||||
input video_rotated,
|
||||
|
||||
input [3:0] par_num,
|
||||
input [4:0] par_num,
|
||||
output reg [15:0] dout
|
||||
);
|
||||
|
||||
@@ -893,6 +892,9 @@ always @(posedge clk_sys) begin
|
||||
13: dout <= vid_vtime_hdmi[31:16];
|
||||
14: dout <= vid_ccnt[15:0];
|
||||
15: dout <= vid_ccnt[31:16];
|
||||
16: dout <= vid_pixrep;
|
||||
17: dout <= vid_de_h;
|
||||
18: dout <= vid_de_v;
|
||||
default dout <= 0;
|
||||
endcase
|
||||
end
|
||||
@@ -902,24 +904,44 @@ reg [31:0] vid_vcnt = 0;
|
||||
reg [31:0] vid_ccnt = 0;
|
||||
reg [7:0] vid_nres = 0;
|
||||
reg [1:0] vid_int = 0;
|
||||
reg [7:0] vid_pixrep;
|
||||
reg [15:0] vid_de_h;
|
||||
reg [7:0] vid_de_v;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
integer hcnt;
|
||||
integer vcnt;
|
||||
integer ccnt;
|
||||
reg old_vs= 0, old_de = 0, old_vmode = 0;
|
||||
reg [7:0] pcnt;
|
||||
reg [7:0] de_v;
|
||||
reg [15:0] de_h;
|
||||
reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0;
|
||||
reg [3:0] resto = 0;
|
||||
reg calch = 0;
|
||||
|
||||
if(calch & de) ccnt <= ccnt + 1;
|
||||
pcnt <= pcnt + 1'd1;
|
||||
|
||||
old_hs_vclk <= hs;
|
||||
de_h <= de_h + 1'd1;
|
||||
if(old_hs_vclk & ~hs) de_h <= 1;
|
||||
|
||||
old_de_vclk <= de;
|
||||
if(calch & ~old_de_vclk & de) vid_de_h <= de_h;
|
||||
|
||||
if(ce_pix) begin
|
||||
old_vs <= vs;
|
||||
old_hs <= hs;
|
||||
old_de <= de;
|
||||
old_de1 <= old_de;
|
||||
pcnt <= 1;
|
||||
|
||||
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
|
||||
if(calch & de) hcnt <= hcnt + 1;
|
||||
if(old_de & ~de) calch <= 0;
|
||||
if(~old_de1 & old_de) vid_pixrep <= pcnt;
|
||||
if(old_hs & ~hs) de_v <= de_v + 1'd1;
|
||||
if(calch & ~old_de & de) vid_de_v <= de_v;
|
||||
|
||||
if(old_vs & ~vs) begin
|
||||
vid_int <= {vid_int[0],f1};
|
||||
@@ -939,6 +961,7 @@ always @(posedge clk_vid) begin
|
||||
hcnt <= 0;
|
||||
ccnt <= 0;
|
||||
calch <= 1;
|
||||
de_v <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1008,8 +1031,15 @@ module confstr_rom #(parameter CONF_STR, STRLEN)
|
||||
output reg [7:0] conf_byte
|
||||
);
|
||||
|
||||
wire [7:0] rom[STRLEN];
|
||||
initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
|
||||
reg [7:0] rom[STRLEN];
|
||||
|
||||
initial begin
|
||||
if( CONF_STR=="" )
|
||||
$readmemh("cfgstr.hex",rom);
|
||||
else
|
||||
for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
|
||||
end
|
||||
|
||||
always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -75,7 +75,7 @@ always @(posedge CLK) begin
|
||||
END <= 0;
|
||||
rd <= READ;
|
||||
len <= I2C_WLEN;
|
||||
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
|
||||
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b1, 3'b011, 9'b111111111};
|
||||
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
|
||||
SD_COUNTER <= 0;
|
||||
end else begin
|
||||
|
||||
@@ -8,10 +8,12 @@ module mcp23009
|
||||
|
||||
output reg [2:0] btn,
|
||||
input [2:0] led,
|
||||
output reg sd_cd,
|
||||
output reg flg_sd_cd,
|
||||
output reg flg_present,
|
||||
output reg flg_mode,
|
||||
|
||||
output scl,
|
||||
inout sda
|
||||
output scl,
|
||||
inout sda
|
||||
);
|
||||
|
||||
|
||||
@@ -50,7 +52,9 @@ always@(posedge clk) begin
|
||||
idx <= 0;
|
||||
btn <= 0;
|
||||
rw <= 0;
|
||||
sd_cd <= 1;
|
||||
flg_sd_cd <= 1;
|
||||
flg_present <= 0;
|
||||
flg_mode <= 1;
|
||||
end
|
||||
else begin
|
||||
if(~&init_data[idx]) begin
|
||||
@@ -84,7 +88,10 @@ always@(posedge clk) begin
|
||||
state <= 0;
|
||||
rw <= 0;
|
||||
if(!error) begin
|
||||
if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
|
||||
if(rw) begin
|
||||
{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
|
||||
flg_present <= 1;
|
||||
end
|
||||
rw <= ~rw;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -1,44 +1,5 @@
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
||||
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
||||
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
module altera_pll_reconfig_core
|
||||
#(
|
||||
parameter reconf_width = 64,
|
||||
parameter device_family = "Stratix V",
|
||||
parameter device_family = "Cyclone V",
|
||||
// MIF Streaming parameters
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
@@ -1883,7 +1883,7 @@ module fpll_dprio_init (
|
||||
endmodule
|
||||
module dyn_phase_shift
|
||||
#(
|
||||
parameter device_family = "Stratix V"
|
||||
parameter device_family = "Cyclone V"
|
||||
) (
|
||||
|
||||
input wire clk,
|
||||
@@ -2112,7 +2112,7 @@ endmodule
|
||||
module generic_lcell_comb
|
||||
#(
|
||||
//parameter
|
||||
parameter family = "Stratix V",
|
||||
parameter family = "Cyclone V",
|
||||
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
|
||||
parameter dont_touch = "on"
|
||||
) (
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
module altera_pll_reconfig_top
|
||||
#(
|
||||
parameter reconf_width = 64,
|
||||
parameter device_family = "Stratix V",
|
||||
parameter device_family = "Cyclone V",
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
|
||||
|
||||
@@ -1,86 +1,86 @@
|
||||
// megafunction wizard: %Altera PLL Reconfig v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_cfg.v
|
||||
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_cfg #(
|
||||
parameter ENABLE_BYTEENABLE = 0,
|
||||
parameter BYTEENABLE_WIDTH = 4,
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
parameter reconf_width = 64,
|
||||
parameter WAIT_FOR_LOCK = 1
|
||||
) (
|
||||
input wire mgmt_clk, // mgmt_clk.clk
|
||||
input wire mgmt_reset, // mgmt_reset.reset
|
||||
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
|
||||
input wire mgmt_read, // .read
|
||||
input wire mgmt_write, // .write
|
||||
output wire [31:0] mgmt_readdata, // .readdata
|
||||
input wire [5:0] mgmt_address, // .address
|
||||
input wire [31:0] mgmt_writedata, // .writedata
|
||||
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
|
||||
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
|
||||
);
|
||||
|
||||
altera_pll_reconfig_top #(
|
||||
.device_family ("Cyclone V"),
|
||||
.ENABLE_MIF (0),
|
||||
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
|
||||
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
|
||||
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
|
||||
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
|
||||
.reconf_width (reconf_width),
|
||||
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
|
||||
) pll_cfg_inst (
|
||||
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
|
||||
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
|
||||
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
|
||||
.mgmt_read (mgmt_read), // .read
|
||||
.mgmt_write (mgmt_write), // .write
|
||||
.mgmt_readdata (mgmt_readdata), // .readdata
|
||||
.mgmt_address (mgmt_address), // .address
|
||||
.mgmt_writedata (mgmt_writedata), // .writedata
|
||||
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
|
||||
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
|
||||
.mgmt_byteenable (4'b0000) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
|
||||
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
|
||||
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_cfg.vo
|
||||
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
||||
// megafunction wizard: %Altera PLL Reconfig v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_cfg.v
|
||||
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_cfg #(
|
||||
parameter ENABLE_BYTEENABLE = 0,
|
||||
parameter BYTEENABLE_WIDTH = 4,
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
parameter reconf_width = 64,
|
||||
parameter WAIT_FOR_LOCK = 1
|
||||
) (
|
||||
input wire mgmt_clk, // mgmt_clk.clk
|
||||
input wire mgmt_reset, // mgmt_reset.reset
|
||||
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
|
||||
input wire mgmt_read, // .read
|
||||
input wire mgmt_write, // .write
|
||||
output wire [31:0] mgmt_readdata, // .readdata
|
||||
input wire [5:0] mgmt_address, // .address
|
||||
input wire [31:0] mgmt_writedata, // .writedata
|
||||
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
|
||||
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
|
||||
);
|
||||
|
||||
altera_pll_reconfig_top #(
|
||||
.device_family ("Cyclone V"),
|
||||
.ENABLE_MIF (0),
|
||||
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
|
||||
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
|
||||
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
|
||||
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
|
||||
.reconf_width (reconf_width),
|
||||
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
|
||||
) pll_cfg_inst (
|
||||
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
|
||||
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
|
||||
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
|
||||
.mgmt_read (mgmt_read), // .read
|
||||
.mgmt_write (mgmt_write), // .write
|
||||
.mgmt_readdata (mgmt_readdata), // .readdata
|
||||
.mgmt_address (mgmt_address), // .address
|
||||
.mgmt_writedata (mgmt_writedata), // .writedata
|
||||
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
|
||||
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
|
||||
.mgmt_byteenable (4'b0000) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
|
||||
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
|
||||
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_cfg.vo
|
||||
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
||||
1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,4 @@
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
||||
|
||||
@@ -58,10 +58,10 @@ localparam DW = WIDE ? 15 : 7;
|
||||
localparam SZ = OCTAL ? 8 : 1;
|
||||
localparam SW = SZ-1;
|
||||
|
||||
wire [7:0] DATA_TOKEN_CMD25 = 8'hfc;
|
||||
wire [7:0] STOP_TRAN = 8'hfd;
|
||||
wire [7:0] DATA_TOKEN = 8'hfe;
|
||||
wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
|
||||
localparam DATA_TOKEN_CMD25 = 8'hfc;
|
||||
localparam STOP_TRAN = 8'hfd;
|
||||
localparam DATA_TOKEN = 8'hfe;
|
||||
localparam WRITE_DATA_RESPONSE = 8'he5;
|
||||
|
||||
// number of bytes to wait after a command before sending the reply
|
||||
localparam NCR = 5+3; // 5 bytes are required (command length)
|
||||
|
||||
@@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
|
||||
#============================================================
|
||||
# ARDUINO
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
|
||||
|
||||
#============================================================
|
||||
# I2C LEDS/BUTTONS
|
||||
#============================================================
|
||||
|
||||
@@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}]
|
||||
set_false_path -from [get_ports {BTN_*}]
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -from [get_ports {VGA_EN}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
@@ -34,6 +35,7 @@ set_false_path -from {cfg[*]}
|
||||
set_false_path -from {VSET[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
||||
set_false_path -to {deb_* btn_en btn_up}
|
||||
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||
@@ -58,6 +60,7 @@ set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
||||
set_false_path -from {arx* ary*}
|
||||
set_false_path -from {vs_line*}
|
||||
set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
|
||||
|
||||
set_false_path -from {ascal|o_ihsize*}
|
||||
set_false_path -from {ascal|o_ivsize*}
|
||||
@@ -70,4 +73,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
|
||||
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
||||
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
||||
|
||||
set_false_path -from {mcp23009|sd_cd}
|
||||
set_false_path -from {mcp23009|flg_*}
|
||||
set_false_path -to {sysmem|fpga_interfaces|clocks_resets|f2h*}
|
||||
|
||||
937
sys/sys_top.v
937
sys/sys_top.v
File diff suppressed because it is too large
Load Diff
@@ -7,23 +7,27 @@ module vga_out
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [5:0] red = din[23:18];
|
||||
wire [5:0] green = din[15:10];
|
||||
wire [5:0] blue = din[7:2];
|
||||
wire [7:0] red = din[23:16];
|
||||
wire [7:0] green = din[15:8];
|
||||
wire [7:0] blue = din[7:0];
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
|
||||
// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
reg [7:0] y, pb, pr;
|
||||
reg [23:0] rgb;
|
||||
@@ -33,32 +37,33 @@ always @(posedge clk) begin
|
||||
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
reg [23:0] din1, din2;
|
||||
reg hsync2, vsync2, csync2;
|
||||
reg hsync1, vsync1, csync1;
|
||||
reg hsync2, vsync2, csync2, de2;
|
||||
reg hsync1, vsync1, csync1, de1;
|
||||
|
||||
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
|
||||
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
|
||||
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
|
||||
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
|
||||
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
|
||||
pr_1r <= 19'd32768 + {red, 7'd0};
|
||||
|
||||
y_1g <= {green, 9'd0} + {green, 2'd0};
|
||||
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
|
||||
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
|
||||
y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
|
||||
pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
|
||||
pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
|
||||
|
||||
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
|
||||
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
|
||||
pr_1b <= {blue, 6'd0} + {blue, 3'd0};
|
||||
y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
|
||||
pb_1b <= {blue, 7'd0};
|
||||
pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
|
||||
|
||||
y_2 <= y_1r + y_1g + y_1b;
|
||||
pb_2 <= pb_1r - pb_1g + pb_1b;
|
||||
pr_2 <= pr_1r - pr_1g - pr_1b;
|
||||
|
||||
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
|
||||
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
|
||||
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
|
||||
y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
|
||||
pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
|
||||
pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
|
||||
|
||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||
de_o <= de2; de2 <= de1; de1 <= de;
|
||||
|
||||
rgb <= din2; din2 <= din1; din1 <= din;
|
||||
end
|
||||
|
||||
@@ -26,6 +26,10 @@ module video_cleaner
|
||||
//optional de
|
||||
input DE_in,
|
||||
|
||||
//optional interlace support
|
||||
input interlace,
|
||||
input f1,
|
||||
|
||||
// video output signals
|
||||
output reg [7:0] VGA_R,
|
||||
output reg [7:0] VGA_G,
|
||||
@@ -56,14 +60,19 @@ always @(posedge clk_vid) begin
|
||||
HBlank_out <= hbl;
|
||||
|
||||
VGA_HS <= hs;
|
||||
if(~VGA_HS & hs) VGA_VS <= vs;
|
||||
|
||||
VGA_R <= R;
|
||||
VGA_G <= G;
|
||||
VGA_B <= B;
|
||||
DE_out <= DE_in;
|
||||
|
||||
if(HBlank_out & ~hbl) VBlank_out <= vbl;
|
||||
if (interlace & f1) begin
|
||||
VGA_VS <= vs;
|
||||
VBlank_out <= vbl;
|
||||
end else begin
|
||||
if(~VGA_HS & hs) VGA_VS <= vs;
|
||||
if(HBlank_out & ~hbl) VBlank_out <= vbl;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] oheight,wres;
|
||||
reg [11:0] oheight,htarget,wres,hinteger,wideres;
|
||||
reg [12:0] arxf,aryf;
|
||||
reg [3:0] cnt;
|
||||
reg narrow;
|
||||
@@ -188,11 +186,18 @@ always @(posedge CLK_VIDEO) begin
|
||||
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
// example ideal and non-ideal cases:
|
||||
// [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels)
|
||||
// [2] 640x480 4:3 VGA graphics mode (square pixels)
|
||||
// [3] 512x512 4:3 X68000 graphics mode (non-square pixels)
|
||||
0: begin
|
||||
div_num <= HDMI_HEIGHT;
|
||||
div_den <= vsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 -> 2
|
||||
// [2] 1080 / 480 -> 2
|
||||
// [3] 1080 / 512 -> 2
|
||||
|
||||
1: if(!div_res[11:0]) begin
|
||||
// screen resolution is lower than video resolution.
|
||||
@@ -206,6 +211,9 @@ always @(posedge CLK_VIDEO) begin
|
||||
mul_arg2 <= div_res[11:0];
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 -> 800
|
||||
// [2] 1080 / 480 * 480 -> 960
|
||||
// [3] 1080 / 512 * 512 -> 1024
|
||||
|
||||
2: begin
|
||||
oheight <= mul_res[11:0];
|
||||
@@ -219,27 +227,43 @@ always @(posedge CLK_VIDEO) begin
|
||||
mul_arg2 <= arx_i;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 * 4 -> 3200
|
||||
// [2] 1080 / 480 * 480 * 4 -> 3840
|
||||
// [3] 1080 / 512 * 512 * 4 -> 4096
|
||||
|
||||
4: begin
|
||||
div_num <= mul_res;
|
||||
div_den <= ary_i;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 480 * 480 * 4 / 3 -> 1066
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 -> 1280
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 -> 1365
|
||||
// saved as htarget
|
||||
|
||||
5: begin
|
||||
htarget <= div_res[11:0];
|
||||
div_num <= div_res;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// computes wide scaling factor as a ceiling division
|
||||
// [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2
|
||||
|
||||
6: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
|
||||
|
||||
7: if(mul_res <= HDMI_WIDTH) begin
|
||||
cnt <= 10;
|
||||
hinteger = mul_res[11:0];
|
||||
cnt <= 12;
|
||||
end
|
||||
|
||||
8: begin
|
||||
@@ -247,23 +271,50 @@ always @(posedge CLK_VIDEO) begin
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1920 / 720 -> 2
|
||||
// [2] 1920 / 640 -> 3
|
||||
// [3] 1920 / 512 -> 3
|
||||
|
||||
9: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1920 / 720 * 720 -> 1440
|
||||
// [2] 1920 / 640 * 640 -> 1920
|
||||
// [3] 1920 / 512 * 512 -> 1536
|
||||
|
||||
10: begin
|
||||
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
|
||||
wres <= wideres;
|
||||
10: begin
|
||||
hinteger <= mul_res[11:0];
|
||||
mul_arg1 <= vsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
11: begin
|
||||
oheight <= mul_res[11:0];
|
||||
end
|
||||
|
||||
12: begin
|
||||
wideres <= hinteger + hsize;
|
||||
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
||||
wres <= hinteger == htarget ? hinteger : wideres;
|
||||
end
|
||||
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
|
||||
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
|
||||
// [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false
|
||||
// 1. narrow flag is true when mul_res[11:0] narrow width is closer to
|
||||
// htarget aspect ratio target width or when wideres wider width
|
||||
// does not fit to the screen.
|
||||
// 2. wres becomes wideres only when mul_res[11:0] narrow width not equal
|
||||
// to target width, meaning it is not optimal for source aspect ratio.
|
||||
// otherwise it is set to narrow width that is optimal.
|
||||
|
||||
11: begin
|
||||
13: begin
|
||||
case(SCALE)
|
||||
2: arxf <= {1'b1, mul_res[11:0]};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
||||
2: arxf <= {1'b1, hinteger};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
|
||||
4: arxf <= {1'b1, narrow ? hinteger : wres};
|
||||
default: arxf <= {1'b1, div_num[11:0]};
|
||||
endcase
|
||||
aryf <= {1'b1, oheight};
|
||||
|
||||
@@ -36,13 +36,15 @@ module yc_out
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [7:0] red = din[23:16];
|
||||
@@ -61,6 +63,7 @@ typedef struct {
|
||||
logic hsync;
|
||||
logic vsync;
|
||||
logic csync;
|
||||
logic de;
|
||||
} phase_t;
|
||||
|
||||
localparam MAX_PHASES = 7'd8;
|
||||
@@ -211,11 +214,11 @@ always_ff @(posedge clk) begin
|
||||
end
|
||||
|
||||
// Adjust sync timing correctly
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync;
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
|
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|
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phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user