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Clock speed fix

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jimmystones
2021-06-24 21:37:01 +01:00
parent cdd9cbd419
commit d43a43ddf4
4 changed files with 2 additions and 3 deletions
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2
InputTest.sv
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@@ -306,7 +306,7 @@ wire ce_pix;
jtframe_cen24 divider
(
.clk(clk_sys),
.cen4(ce_pix)
.cen6(ce_pix)
);
/////////////////// VIDEO ////////////////////

BIN
release/InputTest_20210624.rbf
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1
src/Makefile
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@@ -3,7 +3,6 @@ CPU=z80
CODE=boot_rom
OBJ=boot_rom.rel
DATALOC=0xC000
#DATALOC=0x8000
all: $(CODE).bin

2
verilator/sim.v
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@@ -65,7 +65,7 @@ wire ce_pix;
jtframe_cen24 divider
(
.clk(clk_sys),
.cen4(ce_pix)
.cen6(ce_pix)
);
/* verilator lint_on PINMISSING */