mister-devel/InputTest_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/InputTest_MiSTer.git synced 2026-05-24 03:03:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

Some code

Browse Source
This commit is contained in:
jimmystones
2021-06-20 22:51:20 +01:00
parent e6977c6702
commit a15319a151
34 changed files with 3875 additions and 4568 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
Makefile
View File

@@ -1,20 +0,0 @@
SDCC=sdcc
CPU=z80
CODE=boot_rom
all: $(CODE).hex
%.ihx: %.c
$(SDCC) -m$(CPU) $<
%.hex: %.ihx
mv $< $@
%.bin: %.hex
srec_cat $< -intel -o $@ -binary
disasm: $(CODE).bin
z80dasm -a -t -g 0 $<
clean:
rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym

61
boot_rom.c
View File

@@ -1,61 +0,0 @@
// boot_rom.c
// Boot ROM for the Z80 system on a chip (SoC)
// (c) 2015 Till Harbaum
#include <stdlib.h> // for abs()
// draw a pixel
// At 160x100 pixel screen size a byte is sufficient to hold the x and
// y coordinates- Video memory begins at address 0 and is write only.
// The address space is shared with the ROM which is read only.
void put_pixel(unsigned char x, unsigned char y, unsigned char color) {
*((unsigned char*)(160*y+x)) = color;
}
// bresenham algorithm to draw a line
void draw_line(unsigned char x, unsigned char y,
unsigned char x2, unsigned char y2,
unsigned char color) {
unsigned char longest, shortest, numerator, i;
char dx1 = (x<x2)?1:-1;
char dy1 = (y<y2)?1:-1;
char dx2, dy2;
longest = abs(x2 - x);
shortest = abs(y2 - y);
if(longest<shortest) {
longest = abs(y2 - y);
shortest = abs(x2 - x);
dx2 = 0;
dy2 = dy1;
} else {
dx2 = dx1;
dy2 = 0;
}
numerator = longest/2;
for(i=0;i<=longest;i++) {
put_pixel(x,y,color) ;
if(numerator >= longest-shortest) {
numerator += shortest ;
numerator -= longest ;
x += dx1;
y += dy1;
} else {
numerator += shortest ;
x += dx2;
y += dy2;
}
}
}
void main() {
int i;
unsigned char color = 0;
// draw colorful lines forever ...
while(1) {
for(i=0;i<10;i++) draw_line(0,0,19,i,color++);
for(i=19;i>=0;i--) draw_line(0,0,i,9,color++);
}
}

6
build.sh Normal file
View File

@@ -0,0 +1,6 @@
cd src
make
cd ..
cd verilator
./verilate.sh
cd ..

4
files.qip
View File

@@ -3,6 +3,6 @@ set_global_assignment -name QIP_FILE rtl/T80/t80.qip
set_global_assignment -name QIP_FILE rtl/tv80/TV80.qip
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VERILOG_FILE rtl/vga.v
set_global_assignment -name VERILOG_FILE rtl/video.v
set_global_assignment -name VERILOG_FILE rtl/soc.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/bram.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dpram.v

1175
rtl/T80/T80.vhd
View File

File diff suppressed because it is too large Load Diff

376
rtl/T80/T80_ALU.vhd
View File

@@ -1,376 +0,0 @@
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
-- 0240 : Added GB operations
-- 0242 : Cleanup
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
if IR(2 downto 0) = "110" or XY_State /= "00" then
F_Out(Flag_X) <= WZ(11);
F_Out(Flag_Y) <= WZ(13);
else
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2035
rtl/T80/T80_MCode.vhd
View File

File diff suppressed because it is too large Load Diff

152
rtl/T80/T80_Reg.vhd
View File

@@ -1,152 +0,0 @@
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0);
DIRSet : in std_logic;
DIR : in std_logic_vector(127 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if rising_edge(Clk) then
if DIRSet = '1' then
RegsL(0) <= DIR( 7 downto 0);
RegsH(0) <= DIR( 15 downto 8);
RegsL(1) <= DIR( 23 downto 16);
RegsH(1) <= DIR( 31 downto 24);
RegsL(2) <= DIR( 39 downto 32);
RegsH(2) <= DIR( 47 downto 40);
RegsL(3) <= DIR( 55 downto 48);
RegsH(3) <= DIR( 63 downto 56);
RegsL(4) <= DIR( 71 downto 64);
RegsH(4) <= DIR( 79 downto 72);
RegsL(5) <= DIR( 87 downto 80);
RegsH(5) <= DIR( 95 downto 88);
RegsL(6) <= DIR(103 downto 96);
RegsH(6) <= DIR(111 downto 104);
RegsL(7) <= DIR(119 downto 112);
RegsH(7) <= DIR(127 downto 120);
elsif CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
end;

216
rtl/T80/T80pa.vhd
View File

@@ -1,216 +0,0 @@
--
-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- File history :
--
-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
--
-- v2.0: rewritten for more precise timings.
-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
--
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
--
-- v2.2: Interrupt acknowledge cycle has been corrected
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
--
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80pa is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CEN_p : in std_logic := '1';
CEN_n : in std_logic := '1';
WAIT_n : in std_logic := '1';
INT_n : in std_logic := '1';
NMI_n : in std_logic := '1';
BUSRQ_n : in std_logic := '1';
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet : in std_logic := '0';
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80pa;
architecture rtl of T80pa is
signal IntCycle_n : std_logic;
signal IntCycleD_n : std_logic_vector(1 downto 0);
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal BUSAK : std_logic;
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal CEN_pol : std_logic;
signal A_int : std_logic_vector(15 downto 0);
signal A_last : std_logic_vector(15 downto 0);
begin
A <= A_int when NoRead = '0' or Write = '1' else A_last;
BUSAK_n <= BUSAK;
u0 : work.T80
generic map(
Mode => Mode,
IOWait => 1
)
port map(
CEN => CEN_p and not CEN_pol,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => '1',
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK,
CLK_n => CLK,
A => A_int,
DInst => DI, -- valid at beginning of T3
DI => DI_Reg, -- latched at middle of T3
DO => DO,
REG => REG,
MC => MCycle,
TS => TState,
OUT0 => OUT0,
IntCycle_n => IntCycle_n,
DIRSet => DIRSet,
DIR => DIR
);
process(CLK)
begin
if rising_edge(CLK) then
if RESET_n = '0' then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
CEN_pol <= '0';
elsif CEN_p = '1' and CEN_pol = '0' then
CEN_pol <= '1';
if MCycle = "001" then
if TState = "010" then
IORQ_n <= '1';
MREQ_n <= '1';
RD_n <= '1';
end if;
else
if TState = "001" and IORQ = '1' then
WR_n <= not Write;
RD_n <= Write;
IORQ_n <= '0';
end if;
end if;
elsif CEN_n = '1' and CEN_pol = '1' then
if TState = "010" then
CEN_pol <= not WAIT_n;
else
CEN_pol <= '0';
end if;
if TState = "011" and BUSAK = '1' then
DI_Reg <= DI;
end if;
if MCycle = "001" then
if TState = "001" then
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycleD_n(1);
A_last <= A_int;
end if;
if TState = "011" then
IntCycleD_n <= "11";
RD_n <= '1';
MREQ_n <= '0';
end if;
if TState = "100" then
MREQ_n <= '1';
end if;
else
if NoRead = '0' and IORQ = '0' then
if TState = "001" then
RD_n <= Write;
MREQ_n <= '0';
A_last <= A_int;
end if;
end if;
if TState = "010" then
WR_n <= not Write;
end if;
if TState = "011" then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
end if;
end if;
end if;
end if;
end process;
end;

192
rtl/T80/T80s.vhd
View File

@@ -1,192 +0,0 @@
--
-- Z80 compatible microprocessor core, synchronous top level
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed read with wait
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity T80s is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CEN : in std_logic := '1';
WAIT_n : in std_logic := '1';
INT_n : in std_logic := '1';
NMI_n : in std_logic := '1';
BUSRQ_n : in std_logic := '1';
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80s;
architecture rtl of T80s is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : work.T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
OUT0 => OUT0,
IntCycle_n => IntCycle_n
);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif rising_edge(CLK) then
if CEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = 1 then
if TState = 1 or (TState = 2 and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = 3 then
MREQ_n <= '0';
end if;
else
if (TState = 1 or (TState = 2 and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = 2 and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = 1 or (TState = 2 and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = 2 and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

6
rtl/T80/t80.qip
View File

@@ -1,6 +0,0 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ]

54
rtl/bram.v
View File

@@ -1,54 +0,0 @@
`timescale 1ns / 1ps
module dpram #(
parameter width_a = 8,
parameter widthad_a = 10,
parameter init_file= ""
) (
// Port A
input wire clock_a,
input wire wren_a,
input wire [widthad_a-1:0] address_a,
input wire [width_a-1:0] data_a,
output reg [width_a-1:0] q_a,
// Port B
input wire clock_b,
input wire wren_b,
input wire [widthad_a-1:0] address_b,
input wire [width_a-1:0] data_b,
output reg [width_a-1:0] q_b,
input wire byteena_a,
input wire byteena_b
);
initial begin
$display("Loading rom.");
$display(init_file);
if (init_file>0)
$readmemh(init_file, mem);
end
// Shared memory
reg [width_a-1:0] mem [(2**widthad_a)-1:0];
// Port A
always @(posedge clock_a) begin
q_a <= mem[address_a];
if(wren_a) begin
q_a <= data_a;
mem[address_a] <= data_a;
end
end
// Port B
always @(posedge clock_b) begin
q_b <= mem[address_b];
if(wren_b) begin
q_b <= data_b;
mem[address_b] <= data_b;
end
end
endmodule

52
rtl/dpram.v Normal file
View File

@@ -0,0 +1,52 @@
`timescale 1ns / 1ps
module dpram #(
parameter address_width = 10,
parameter data_width = 8
) (
input wire clock_a,
input wire wren_a,
input wire [address_width-1:0] address_a,
input wire [data_width-1:0] data_a,
output reg [data_width-1:0] q_a,
input wire clock_b,
input wire wren_b,
input wire [address_width-1:0] address_b,
input wire [data_width-1:0] data_b,
output reg [data_width-1:0] q_b
);
localparam ramLength = (2**address_width);
reg [data_width-1:0] mem [ramLength-1:0];
`ifdef SIMULATION
integer j;
initial
begin
for (j = 0; j < ramLength; j = j + 1)
begin
mem[j] = 0;
end
end
`endif
// Port A
always @(posedge clock_a) begin
q_a <= mem[address_a];
if(wren_a) begin
q_a <= data_a;
mem[address_a] <= data_a;
end
end
// Port B
always @(posedge clock_b) begin
q_b <= mem[address_b];
if(wren_b) begin
q_b <= data_b;
mem[address_b] <= data_b;
end
end
endmodule

168
rtl/soc.v
View File

@@ -1,56 +1,46 @@
`timescale 1ns / 1ps
module soc (
input clk_sys,
input pixel_clock,
output VGA_HS,
output VGA_VS,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HB,
output VGA_VB,
output VGA_DE
);
input clk_sys,
input clk_pix,
input [13:0] dn_addr,
input dn_wr,
input [7:0] dn_data,
input [7:0] inputs,
output VGA_HS,
output VGA_VS,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HB,
output VGA_VB,
output VGA_DE
);
///////////////////////////////////////////////////
wire [3:0] r, g, b;
wire vs,hs;
wire ce_pix;
wire hblank, vblank;
wire interlace;
// include VGA controller
vga vga (
.pclk ( pixel_clock),
.cpu_clk ( cpu_clock ),
// Video subsystem
video video (
.pclk ( clk_pix ),
.cpu_clk ( clk_sys ),
.cpu_wr ( !cpu_wr_n && !cpu_addr[15] ),
.cpu_addr ( cpu_addr[13:0] ),
.cpu_data ( cpu_dout ),
// video output as fed into the VGA outputs
.hs (VGA_HS),
.vs (VGA_VS),
.r (VGA_R),
.g (VGA_G),
.b (VGA_B),
.VGA_HB(VGA_HB),
.VGA_VB(VGA_VB),
.VGA_DE(VGA_DE)
.cpu_addr ( cpu_addr[15:0] ),
.cpu_data ( cpu_dout ),
.hs (VGA_HS),
.vs (VGA_VS),
.r (VGA_R),
.g (VGA_G),
.b (VGA_B),
.hb (VGA_HB),
.vb (VGA_VB),
.de (VGA_DE)
);
// The CPU is kept in reset for 256 cycles after power on
reg [7:0] cpu_reset_cnt = 8'h00;
wire cpu_reset = (cpu_reset_cnt != 255);
always @(posedge cpu_clock)
always @(posedge clk_sys)
if(cpu_reset_cnt != 255)
cpu_reset_cnt <= cpu_reset_cnt + 8'd1;
// CPU control signals
wire cpu_clock = clk_sys;
wire [15:0] cpu_addr;
wire [7:0] cpu_din;
wire [7:0] cpu_dout;
@@ -59,26 +49,9 @@ wire cpu_wr_n;
wire cpu_mreq_n;
// include Z80 CPU
/*
T80s T80s (
.RESET_n ( !cpu_reset ),
.CLK ( cpu_clock ),
.WAIT_n ( 1'b1 ),
.INT_n ( 1'b1 ),
.NMI_n ( 1'b1 ),
.BUSRQ_n ( 1'b1 ),
.MREQ_n ( cpu_mreq_n ),
.RD_n ( cpu_rd_n ),
.WR_n ( cpu_wr_n ),
.A ( cpu_addr ),
.DI ( cpu_din ),
.DO ( cpu_dout )
);
*/
tv80s T80x (
.reset_n ( !cpu_reset ),
.clk ( cpu_clock ),
.clk ( clk_sys ),
.wait_n ( 1'b1 ),
.int_n ( 1'b1 ),
.nmi_n ( 1'b1 ),
@@ -88,47 +61,64 @@ tv80s T80x (
.wr_n ( cpu_wr_n ),
.A ( cpu_addr ),
.di ( cpu_din ),
.dout ( cpu_dout )
.dout ( cpu_dout ),
.m1_n (),
.iorq_n (),
.rfsh_n (),
.halt_n (),
.busak_n ()
);
// map 4k RAM into upper half of the address space (A15=1)
// and 4k ROM into the lower half (A15=0)
wire [7:0] ram_data_out, rom_data_out;
assign cpu_din = cpu_addr[15]?ram_data_out:rom_data_out;
// include 4k program code from boot_rom
wire [7:0] ram_data_out;
wire [7:0] rom_data_out;
dpram #( .init_file("rom.hex"),.widthad_a(12),.width_a(8)) rom
wire rom_cs = cpu_addr[15:14] == 2'b00;
wire ram_cs = cpu_addr[15] == 1'b1;
wire in0_cs = cpu_addr == 16'h4000;
wire in1_cs = cpu_addr == 16'h4001;
assign cpu_din = ram_cs ? ram_data_out :
rom_cs ? rom_data_out :
in0_cs ? {VGA_HS, VGA_VS, 6'b101000} :
in1_cs ? inputs :
8'b00000000;
always @(posedge clk_sys)
begin
//$display("%b %x %d", cpu_addr, cpu_addr, cpu_addr);
//$display("%x = %x", cpu_addr, cpu_din);
// $display("rom_cs %b ram_cs %b in1_cs %b", rom_cs, ram_cs, in1_cs);
end
dpram #(12,8) rom
(
.clock_a(cpu_clock),
.address_a(cpu_addr[11:0]),
.wren_a(1'b0),
.q_a(rom_data_out),
.clock_b(cpu_clock),
.wren_b(1'b0)
.clock_a(clk_sys),
.address_a(cpu_addr[11:0]),
.wren_a(1'b0),
.data_a(),
.q_a(rom_data_out),
.clock_b(clk_sys),
.address_b(dn_addr[11:0]),
.wren_b(dn_wr),
.data_b(dn_data),
.q_b()
);
dpram #( .init_file(""),.widthad_a(12),.width_a(8)) ram
dpram #(12,8) ram
(
.clock_a(cpu_clock),
.address_a(cpu_addr[11:0]),
.wren_a(!cpu_wr_n && cpu_addr[15]),
.q_a(ram_data_out),
.data_a(cpu_dout),
.clock_b(cpu_clock),
.address_b(cpu_addr[11:0]),
.wren_b(1'b0),
.q_b(),
.data_b(),
.clock_a(clk_sys),
.address_a(cpu_addr[11:0]),
.wren_a(!cpu_wr_n && ram_cs),
.data_a(cpu_dout),
.q_a(ram_data_out),
.clock_b(clk_sys),
.address_b(cpu_addr[11:0]),
.wren_b(1'b0),
.data_b(),
.q_b()
);
endmodule

97
rtl/vga.v → rtl/video.v
View File

@@ -1,20 +1,10 @@
`timescale 1ns / 1ps
// A simple system-on-a-chip (SoC) for the MiST
// (c) 2015 Till Harbaum
// VGA controller generating 160x100 pixles. The VGA mode ised is 640x400
// combining every 4 row and column
// http://tinyvga.com/vga-timing/640x400@70Hz
module vga (
// pixel clock
input pclk,
// CPU interface (write only!)
input cpu_clk,
module video (
input pclk, // pixel clock
input cpu_clk, //
input cpu_wr,
input [13:0] cpu_addr,
input [15:0] cpu_addr,
input [7:0] cpu_data,
// VGA output
@@ -23,9 +13,9 @@ module vga (
output [7:0] r,
output [7:0] g,
output [7:0] b,
output reg VGA_HB,
output reg VGA_VB,
output VGA_DE
output reg hb,
output reg vb,
output reg de
);
// 640x400 70HZ VESA according to http://tinyvga.com/vga-timing/640x400@70Hz
@@ -39,29 +29,34 @@ parameter VFP = 12; // unused time before vsync
parameter VS = 2; // width of vsync
parameter VBP = 35; // unused time after vsync
parameter VGA_WIDTH = 320; // width of backbuffer
parameter VGA_HEIGHT = 200; // height of backbuffer
reg[9:0] h_cnt; // horizontal pixel counter
reg[9:0] v_cnt; // vertical pixel counter
reg hblank;
reg vblank;
reg [15:0] video_counter;
reg [7:0] pixel;
// both counters count from the begin of the visibla area
// 16000 bytes of internal video memory for 160x100 pixel at 8 Bit (RGB 332)
reg [7:0] vmem [(VGA_WIDTH*VGA_HEIGHT)-1:0];
// horizontal pixel counter
always@(posedge pclk) begin
always@(posedge pclk)
begin
if(h_cnt==H+HFP+HS+HBP-1) h_cnt <= 0;
else h_cnt <= h_cnt + 1;
// generate negative hsync signal
if(h_cnt == H+HFP) hs <= 1'b0;
if(h_cnt == H+HFP+HS) hs <= 1'b1;
end
end
// veritical pixel counter
always@(posedge pclk) begin
always@(posedge pclk)
begin
// the vertical counter is processed at the begin of each hsync
if(h_cnt == H+HFP) begin
if(h_cnt == H+HFP)
begin
if(v_cnt==VS+VBP+V+VFP-1) v_cnt <= 0;
else v_cnt <= v_cnt + 1;
@@ -71,20 +66,15 @@ always@(posedge pclk) begin
end
end
// read VRAM
reg [13:0] video_counter;
reg [7:0] pixel;
reg de;
// 16000 bytes of internal video memory for 160x100 pixel at 8 Bit (RGB 332)
reg [7:0] vmem [160*100-1:0];
// write VRAM via CPU interface
always @(posedge cpu_clk)
begin
if(cpu_wr)
vmem[cpu_addr] <= cpu_data;
end
always@(posedge pclk) begin
always@(posedge pclk)
begin
// The video counter is being reset at the begin of each vsync.
// Otherwise it's increased every fourth pixel in the visible area.
// At the end of the first three of four lines the counter is
@@ -93,41 +83,38 @@ always@(posedge pclk) begin
// VGA lines.
// visible area?
if(v_cnt < V)
VGA_VB<=0;
else
VGA_VB<=1;
if(h_cnt < H)
VGA_HB<=0;
else
VGA_HB<=1;
if(v_cnt < V)
vb<=0;
else
vb<=1;
if(h_cnt < H)
hb<=0;
else
hb<=1;
if((v_cnt < V) && (h_cnt < H)) begin
if(h_cnt[1:0] == 2'b11)
video_counter <= video_counter + 14'd1;
if(h_cnt[0] == 1'b1)
video_counter <= video_counter + 16'd1;
//pixel <= (v_cnt[2] ^ h_cnt[2])?8'h00:8'hff; // checkboard
//pixel <= (v_cnt[4] ^ h_cnt[4])?8'h00:8'hff; // checkboard
//pixel <= video_counter[7:0]; // color pattern
pixel <= vmem[video_counter]; // read VRAM
de<=1;
end else begin
if(h_cnt == H+HFP) begin
if(v_cnt == V+VFP)
video_counter <= 14'd0;
else if((v_cnt < V) && (v_cnt[1:0] != 2'b11))
video_counter <= video_counter - 14'd160;
video_counter <= 16'd0;
else if((v_cnt < V) && (v_cnt[0] != 1'b1))
video_counter <= video_counter - VGA_WIDTH;
de<=0;
end
pixel <= 8'h00; // black
pixel <= 8'hF0; // black
end
end
// seperate 8 bits into three colors (332)
assign r = { pixel[7:5], pixel[7:5] , pixel[7:6]};
assign g = { pixel[4:2], pixel[4:2] , pixel[4:3]};
assign b = { pixel[1:0], pixel[1:0] , pixel[1:0],pixel[1:0] };
assign VGA_DE = de;
assign b = { pixel[1:0], pixel[1:0] , pixel[1:0], pixel[1:0] };
endmodule

24
src/Makefile Normal file
View File

@@ -0,0 +1,24 @@
SDCC=sdcc
CPU=z80
CODE=boot_rom
OBJ=boot_rom.rel font.rel
all: $(CODE).bin
%.rel: %.c
$(SDCC) -m$(CPU) -c $<
%.ihx: $(OBJ)
$(SDCC) -m$(CPU) $(OBJ)
%.hex: %.ihx
mv $< $@
%.bin: %.hex
srec_cat $< -intel -o $@ -binary
disasm: $(CODE).bin
z80dasm -a -t -g 0 $<
clean:
rm -rf *~ *.asm *.ihx *.lk *.lst *.map *.noi *.rel *.sym *.hex *.bin

670
src/boot_rom.asm Normal file
View File

@@ -0,0 +1,670 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.8.0 #10562 (Linux)
;--------------------------------------------------------
.module boot_rom
.optsdcc -mz80
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _main
.globl _draw_line
.globl _cls
.globl _put_pixel
.globl _abs
.globl _cur_y
.globl _cur_x
.globl _y
.globl _color
.globl _input1_cache
.globl _input0_cache
.globl _vsync_last
.globl _vsync
.globl _hsync_last
.globl _hsync
.globl _input1
.globl _input0
.globl _VGA_HEIGHT
.globl _VGA_WIDTH
.globl _putchar
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _DATA
_input0 = 0x4000
_input1 = 0x4001
_hsync::
.ds 1
_hsync_last::
.ds 1
_vsync::
.ds 1
_vsync_last::
.ds 1
_input0_cache::
.ds 1
_input1_cache::
.ds 1
_color::
.ds 1
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _INITIALIZED
_y::
.ds 1
_cur_x::
.ds 2
_cur_y::
.ds 2
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area _DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area _HOME
.area _GSINIT
.area _GSFINAL
.area _GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area _HOME
.area _HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area _CODE
;boot_rom.c:26: int putchar(int c) {
; ---------------------------------
; Function putchar
; ---------------------------------
_putchar::
push ix
ld ix,#0
add ix,sp
ld hl, #-11
add hl, sp
ld sp, hl
;boot_rom.c:28: unsigned int *dptr = (unsigned int*)(VGA_WIDTH*(8*cur_y) + 8*cur_x);
ld hl, (_cur_y)
add hl, hl
add hl, hl
add hl, hl
ld bc, (_VGA_WIDTH)
push hl
push bc
call __mulint
pop af
pop af
ld c, l
ld b, h
ld hl, (_cur_x)
add hl, hl
add hl, hl
add hl, hl
add hl, bc
inc sp
inc sp
push hl
;boot_rom.c:31: if(c < 32) {
ld a, 4 (ix)
sub a, #0x20
ld a, 5 (ix)
rla
ccf
rra
sbc a, #0x80
jr NC,00108$
;boot_rom.c:32: if(c == '\r') { cur_x=0; }
ld a, 4 (ix)
sub a, #0x0d
or a, 5 (ix)
jr NZ,00102$
ld hl, #0x0000
ld (_cur_x), hl
00102$:
;boot_rom.c:33: if(c == '\n') {
ld a, 4 (ix)
sub a, #0x0a
or a, 5 (ix)
jp NZ,00122$
;boot_rom.c:34: cur_y++;
ld iy, #_cur_y
inc 0 (iy)
jr NZ,00192$
inc 1 (iy)
00192$:
;boot_rom.c:35: cur_x=0;
ld hl, #0x0000
ld (_cur_x), hl
;boot_rom.c:36: if(cur_y >= 12) { cur_y = 0; }
ld a, 0 (iy)
sub a, #0x0c
ld a, 1 (iy)
sbc a, #0x00
jp C,00122$
ld l, #0x00
ld (_cur_y), hl
;boot_rom.c:38: return;
jp 00122$
00108$:
;boot_rom.c:41: if(c < 0) return;
bit 7, 5 (ix)
jp NZ,00122$
;boot_rom.c:43: p = font+8*(unsigned char)(c-32);
ld bc, #_font+0
ld a, 4 (ix)
add a, #0xe0
ld l, a
ld h, #0x00
add hl, hl
add hl, hl
add hl, hl
add hl, bc
ld -9 (ix), l
ld -8 (ix), h
;boot_rom.c:44: for(i=0;i<8;i++) {
ld bc, #0x0000
00120$:
;boot_rom.c:45: unsigned char l = *p++;
ld l, -9 (ix)
ld h, -8 (ix)
ld a, (hl)
ld -3 (ix), a
ld a, -9 (ix)
add a, #0x02
ld -9 (ix), a
jr NC,00193$
inc -8 (ix)
00193$:
;boot_rom.c:46: for(j=0;j<8;j++) {
ld -2 (ix), #0x08
ld -1 (ix), #0x00
pop de
push de
00119$:
;boot_rom.c:47: *dptr++ = (l & 0x80) ? color : 0x00;
ld -5 (ix), e
ld -4 (ix), d
inc de
inc de
bit 7, -3 (ix)
jr Z,00124$
ld a,(#_color + 0)
ld -7 (ix), a
ld -6 (ix), #0x00
jr 00125$
00124$:
ld -7 (ix), #0x00
ld -6 (ix), #0x00
00125$:
ld l, -5 (ix)
ld h, -4 (ix)
ld a, -7 (ix)
ld (hl), a
inc hl
ld a, -6 (ix)
ld (hl), a
;boot_rom.c:48: l <<= 1;
ld a, -3 (ix)
add a, a
ld -3 (ix), a
ld l, -2 (ix)
ld h, -1 (ix)
dec hl
ld -2 (ix), l
ld -1 (ix), h
;boot_rom.c:46: for(j=0;j<8;j++) {
ld a, h
or a, l
jr NZ,00119$
;boot_rom.c:50: dptr += (VGA_WIDTH-8);
ld hl, (_VGA_WIDTH)
ld a, l
add a, #0xf8
ld l, a
ld a, h
adc a, #0xff
ld h, a
add hl, hl
add hl, de
inc sp
inc sp
push hl
;boot_rom.c:44: for(i=0;i<8;i++) {
inc bc
ld a, c
sub a, #0x08
ld a, b
rla
ccf
rra
sbc a, #0x80
jp C, 00120$
;boot_rom.c:53: cur_x++;
ld iy, #_cur_x
inc 0 (iy)
jr NZ,00195$
inc 1 (iy)
00195$:
;boot_rom.c:54: if(cur_x >= 20) {
ld a, 0 (iy)
sub a, #0x14
ld a, 1 (iy)
sbc a, #0x00
jr C,00116$
;boot_rom.c:55: cur_x = 0;
ld hl, #0x0000
ld (_cur_x), hl
;boot_rom.c:56: cur_y++;
ld iy, #_cur_y
inc 0 (iy)
jr NZ,00196$
inc 1 (iy)
00196$:
;boot_rom.c:58: if(cur_y >= 12)
ld a, 0 (iy)
sub a, #0x0c
ld a, 1 (iy)
sbc a, #0x00
jr C,00116$
;boot_rom.c:59: cur_y = 0;
ld l, #0x00
ld (_cur_y), hl
00116$:
;boot_rom.c:61: return;
00122$:
;boot_rom.c:62: }
ld sp, ix
pop ix
ret
_VGA_WIDTH:
.dw #0x0140
_VGA_HEIGHT:
.dw #0x00c8
;boot_rom.c:65: void put_pixel(unsigned int x, unsigned int y, unsigned char color) {
; ---------------------------------
; Function put_pixel
; ---------------------------------
_put_pixel::
;boot_rom.c:66: *((unsigned int*)(VGA_WIDTH*y+x)) = color;
ld hl, (_VGA_WIDTH)
ld iy, #4
add iy, sp
ld c, 0 (iy)
ld b, 1 (iy)
push bc
push hl
call __mulint
pop af
pop af
ld c, l
ld b, h
ld a, c
ld hl, #2
add hl, sp
add a, (hl)
ld c, a
ld a, b
inc hl
adc a, (hl)
ld l, c
ld h, a
ld iy, #6
add iy, sp
ld c, 0 (iy)
ld b, #0x00
ld (hl), c
inc hl
ld (hl), b
;boot_rom.c:67: }
ret
;boot_rom.c:69: void cls(unsigned char color) {
; ---------------------------------
; Function cls
; ---------------------------------
_cls::
push ix
ld ix,#0
add ix,sp
dec sp
;boot_rom.c:73: for(i=0;i<VGA_HEIGHT;i++) {
ld bc, #0x0000
00107$:
ld hl, (_VGA_HEIGHT)
ld a, c
sub a, l
ld a, b
sbc a, h
jr NC,00102$
;boot_rom.c:74: for(unsigned int x=0;x<VGA_HEIGHT;x++) {
ld a, 4 (ix)
ld -1 (ix), a
ld de, #0x0000
00104$:
ld hl, (_VGA_HEIGHT)
ld a, e
sub a, l
ld a, d
sbc a, h
jr NC,00115$
;boot_rom.c:76: put_pixel(x,i, color);
push bc
push de
ld a, -1 (ix)
push af
inc sp
push bc
push de
call _put_pixel
pop af
pop af
inc sp
pop de
pop bc
;boot_rom.c:77: color++;
inc -1 (ix)
;boot_rom.c:74: for(unsigned int x=0;x<VGA_HEIGHT;x++) {
inc de
jr 00104$
00115$:
ld a, -1 (ix)
ld 4 (ix), a
;boot_rom.c:73: for(i=0;i<VGA_HEIGHT;i++) {
inc bc
jr 00107$
00102$:
;boot_rom.c:81: cur_x = 0;
ld hl, #0x0000
ld (_cur_x), hl
;boot_rom.c:82: cur_y = 0;
ld l, #0x00
ld (_cur_y), hl
;boot_rom.c:83: }
inc sp
pop ix
ret
;boot_rom.c:86: void draw_line(unsigned int x, unsigned int y,
; ---------------------------------
; Function draw_line
; ---------------------------------
_draw_line::
push ix
ld ix,#0
add ix,sp
ld hl, #-18
add hl, sp
ld sp, hl
;boot_rom.c:90: int dx1 = (x<x2)?1:-1;
ld a, 4 (ix)
sub a, 8 (ix)
ld a, 5 (ix)
sbc a, 9 (ix)
jr NC,00112$
ld bc, #0x0001
jr 00113$
00112$:
ld bc, #0xffff
00113$:
ld -12 (ix), c
ld -11 (ix), b
;boot_rom.c:91: int dy1 = (y<y2)?1:-1;
ld a, 6 (ix)
sub a, 10 (ix)
ld a, 7 (ix)
sbc a, 11 (ix)
jr NC,00114$
ld bc, #0x0001
jr 00115$
00114$:
ld bc, #0xffff
00115$:
ld -10 (ix), c
ld -9 (ix), b
;boot_rom.c:94: longest = abs(x2 - x);
ld a, 8 (ix)
sub a, 4 (ix)
ld c, a
ld a, 9 (ix)
sbc a, 5 (ix)
ld b, a
push bc
call _abs
pop af
ld -2 (ix), l
ld -1 (ix), h
;boot_rom.c:95: shortest = abs(y2 - y);
ld a, 10 (ix)
sub a, 6 (ix)
ld e, a
ld a, 11 (ix)
sbc a, 7 (ix)
ld d, a
push de
push de
call _abs
pop af
pop de
ld -4 (ix), l
ld -3 (ix), h
;boot_rom.c:96: if(longest<shortest) {
ld a, -2 (ix)
sub a, -4 (ix)
ld a, -1 (ix)
sbc a, -3 (ix)
jr NC,00102$
;boot_rom.c:97: longest = abs(y2 - y);
push de
call _abs
pop af
ld -2 (ix), l
ld -1 (ix), h
;boot_rom.c:98: shortest = abs(x2 - x);
push bc
call _abs
pop af
ld -4 (ix), l
ld -3 (ix), h
;boot_rom.c:99: dx2 = 0;
ld bc, #0x0000
;boot_rom.c:100: dy2 = dy1;
ld a, -10 (ix)
ld -8 (ix), a
ld a, -9 (ix)
ld -7 (ix), a
jr 00103$
00102$:
;boot_rom.c:102: dx2 = dx1;
ld c, -12 (ix)
ld b, -11 (ix)
;boot_rom.c:103: dy2 = 0;
ld -8 (ix), #0x00
ld -7 (ix), #0x00
00103$:
;boot_rom.c:106: numerator = longest/2;
ld e, -2 (ix)
ld d, -1 (ix)
srl d
rr e
;boot_rom.c:107: for(i=0;i<=longest;i++) {
ld a, -2 (ix)
sub a, -4 (ix)
ld -14 (ix), a
ld a, -1 (ix)
sbc a, -3 (ix)
ld -13 (ix), a
ld -6 (ix), #0x00
ld -5 (ix), #0x00
00108$:
;boot_rom.c:108: put_pixel(x,y,color) ;
push bc
push de
ld a, 12 (ix)
push af
inc sp
ld l, 6 (ix)
ld h, 7 (ix)
push hl
ld l, 4 (ix)
ld h, 5 (ix)
push hl
call _put_pixel
pop af
pop af
inc sp
pop de
pop bc
;boot_rom.c:110: numerator += shortest ;
ld a, -4 (ix)
add a, e
ld -16 (ix), a
ld a, -3 (ix)
adc a, d
ld -15 (ix), a
;boot_rom.c:109: if(numerator >= longest-shortest) {
ld a, e
sub a, -14 (ix)
ld a, d
sbc a, -13 (ix)
jr C,00105$
;boot_rom.c:110: numerator += shortest ;
;boot_rom.c:111: numerator -= longest ;
ld a, -16 (ix)
ld d, -15 (ix)
sub a, -2 (ix)
ld e, a
ld a, d
sbc a, -1 (ix)
ld d, a
;boot_rom.c:112: x += dx1;
ld a, -12 (ix)
ld -18 (ix), a
ld a, -11 (ix)
ld -17 (ix), a
ld a, 4 (ix)
add a, -18 (ix)
ld 4 (ix), a
ld a, 5 (ix)
adc a, -17 (ix)
ld 5 (ix), a
;boot_rom.c:113: y += dy1;
ld a, -10 (ix)
ld -18 (ix), a
ld a, -9 (ix)
ld -17 (ix), a
ld a, 6 (ix)
add a, -18 (ix)
ld 6 (ix), a
ld a, 7 (ix)
adc a, -17 (ix)
ld 7 (ix), a
jr 00109$
00105$:
;boot_rom.c:115: numerator += shortest ;
ld e, -16 (ix)
ld d, -15 (ix)
;boot_rom.c:116: x += dx2;
inc sp
inc sp
push bc
ld a, 4 (ix)
add a, -18 (ix)
ld 4 (ix), a
ld a, 5 (ix)
adc a, -17 (ix)
ld 5 (ix), a
;boot_rom.c:117: y += dy2;
ld a, -8 (ix)
ld -18 (ix), a
ld a, -7 (ix)
ld -17 (ix), a
ld a, 6 (ix)
add a, -18 (ix)
ld 6 (ix), a
ld a, 7 (ix)
adc a, -17 (ix)
ld 7 (ix), a
00109$:
;boot_rom.c:107: for(i=0;i<=longest;i++) {
inc -6 (ix)
jr NZ,00142$
inc -5 (ix)
00142$:
ld a, -2 (ix)
sub a, -6 (ix)
ld a, -1 (ix)
sbc a, -5 (ix)
jp NC, 00108$
;boot_rom.c:120: }
ld sp, ix
pop ix
ret
;boot_rom.c:123: void main() {
; ---------------------------------
; Function main
; ---------------------------------
_main::
;boot_rom.c:124: while(1) {
00108$:
;boot_rom.c:127: input0_cache = input0;
ld a,(#_input0 + 0)
ld iy, #_input0_cache
ld 0 (iy), a
;boot_rom.c:128: hsync = input0_cache & 0x80;
ld c, 0 (iy)
ld a, c
and a, #0x80
ld (#_hsync + 0),a
;boot_rom.c:129: vsync = input0_cache & 0x40;
ld a, c
and a, #0x40
ld (#_vsync + 0),a
;boot_rom.c:131: if(hsync && !hsync_last){
ld a,(#_hsync + 0)
or a, a
jr Z,00102$
ld a,(#_hsync_last + 0)
or a, a
jr NZ,00102$
;boot_rom.c:132: y++;
ld hl, #_y+0
inc (hl)
00102$:
;boot_rom.c:134: if(vsync && !vsync_last){
ld a,(#_vsync + 0)
or a, a
jr Z,00105$
ld a,(#_vsync_last + 0)
or a, a
jr NZ,00105$
;boot_rom.c:135: y=0;
ld hl,#_y + 0
ld (hl), #0x00
;boot_rom.c:138: input1_cache = input1;
ld a,(#_input1 + 0)
ld (#_input1_cache + 0),a
00105$:
;boot_rom.c:141: hsync_last = hsync;
ld a,(#_hsync + 0)
ld (#_hsync_last + 0),a
;boot_rom.c:142: vsync_last = vsync;
ld a,(#_vsync + 0)
ld (#_vsync_last + 0),a
;boot_rom.c:144: }
jr 00108$
.area _CODE
.area _INITIALIZER
__xinit__y:
.db #0x00 ; 0
__xinit__cur_x:
.dw #0x0000
__xinit__cur_y:
.dw #0x0000
.area _CABS (ABS)

BIN
src/boot_rom.bin Normal file
View File

Binary file not shown.

144
src/boot_rom.c Normal file
View File

@@ -0,0 +1,144 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h> // for abs()
extern unsigned char font[];
const unsigned int VGA_WIDTH = 320;
const unsigned int VGA_HEIGHT = 200;
unsigned char __at (0x4000) input0;
unsigned char __at (0x4001) input1;
unsigned char y = 0;
unsigned char hsync;
unsigned char hsync_last;
unsigned char vsync;
unsigned char vsync_last;
unsigned char input0_cache;
unsigned char input1_cache;
unsigned int cur_x=0;
unsigned int cur_y=0;
unsigned char color;
int putchar(int c) {
unsigned int *p;
unsigned int *dptr = (unsigned int*)(VGA_WIDTH*(8*cur_y) + 8*cur_x);
int i, j;
if(c < 32) {
if(c == '\r') { cur_x=0; }
if(c == '\n') {
cur_y++;
cur_x=0;
if(cur_y >= 12) { cur_y = 0; }
}
return;
}
if(c < 0) return;
p = font+8*(unsigned char)(c-32);
for(i=0;i<8;i++) {
unsigned char l = *p++;
for(j=0;j<8;j++) {
*dptr++ = (l & 0x80) ? color : 0x00;
l <<= 1;
}
dptr += (VGA_WIDTH-8);
}
cur_x++;
if(cur_x >= 20) {
cur_x = 0;
cur_y++;
if(cur_y >= 12)
cur_y = 0;
}
return;
}
// draw a pixel
void put_pixel(unsigned int x, unsigned int y, unsigned char color) {
*((unsigned int*)(VGA_WIDTH*y+x)) = color;
}
void cls(unsigned char color) {
unsigned int i;
unsigned int *p = (unsigned int*)0;
for(i=0;i<VGA_HEIGHT;i++) {
for(unsigned int x=0;x<VGA_HEIGHT;x++) {
//memset(p, color, VGA_WIDTH);
put_pixel(x,i, color);
color++;
//p += VGA_WIDTH;
}
}
cur_x = 0;
cur_y = 0;
}
// bresenham algorithm to draw a line
void draw_line(unsigned int x, unsigned int y,
unsigned int x2, unsigned int y2,
unsigned char color) {
unsigned int longest, shortest, numerator, i;
int dx1 = (x<x2)?1:-1;
int dy1 = (y<y2)?1:-1;
int dx2, dy2;
longest = abs(x2 - x);
shortest = abs(y2 - y);
if(longest<shortest) {
longest = abs(y2 - y);
shortest = abs(x2 - x);
dx2 = 0;
dy2 = dy1;
} else {
dx2 = dx1;
dy2 = 0;
}
numerator = longest/2;
for(i=0;i<=longest;i++) {
put_pixel(x,y,color) ;
if(numerator >= longest-shortest) {
numerator += shortest ;
numerator -= longest ;
x += dx1;
y += dy1;
} else {
numerator += shortest ;
x += dx2;
y += dy2;
}
}
}
void main() {
while(1) {
// get inputs
input0_cache = input0;
hsync = input0_cache & 0x80;
vsync = input0_cache & 0x40;
if(hsync && !hsync_last){
y++;
}
if(vsync && !vsync_last){
y=0;
// process inputs
input1_cache = input1;
}
hsync_last = hsync;
vsync_last = vsync;
}
}

12
src/boot_rom.lk Normal file
View File

@@ -0,0 +1,12 @@
-mjwx
-i boot_rom.ihx
-b _CODE = 0x0200
-b _DATA = 0x8000
-k /usr/bin/../share/sdcc/lib/z80
-k /usr/share/sdcc/lib/z80
-l z80
/usr/bin/../share/sdcc/lib/z80/crt0.rel
boot_rom.rel
font.rel
-e

670
src/boot_rom.lst Normal file
View File

@@ -0,0 +1,670 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ANSI-C Compiler
3 ; Version 3.8.0 #10562 (Linux)
4 ;--------------------------------------------------------
5 .module boot_rom
6 .optsdcc -mz80
7
8 ;--------------------------------------------------------
9 ; Public variables in this module
10 ;--------------------------------------------------------
11 .globl _main
12 .globl _draw_line
13 .globl _cls
14 .globl _put_pixel
15 .globl _abs
16 .globl _cur_y
17 .globl _cur_x
18 .globl _y
19 .globl _color
20 .globl _input1_cache
21 .globl _input0_cache
22 .globl _vsync_last
23 .globl _vsync
24 .globl _hsync_last
25 .globl _hsync
26 .globl _input1
27 .globl _input0
28 .globl _VGA_HEIGHT
29 .globl _VGA_WIDTH
30 .globl _putchar
31 ;--------------------------------------------------------
32 ; special function registers
33 ;--------------------------------------------------------
34 ;--------------------------------------------------------
35 ; ram data
36 ;--------------------------------------------------------
37 .area _DATA
4000 38 _input0 = 0x4000
4001 39 _input1 = 0x4001
0000 40 _hsync::
0000 41 .ds 1
0001 42 _hsync_last::
0001 43 .ds 1
0002 44 _vsync::
0002 45 .ds 1
0003 46 _vsync_last::
0003 47 .ds 1
0004 48 _input0_cache::
0004 49 .ds 1
0005 50 _input1_cache::
0005 51 .ds 1
0006 52 _color::
0006 53 .ds 1
54 ;--------------------------------------------------------
55 ; ram data
56 ;--------------------------------------------------------
57 .area _INITIALIZED
0000 58 _y::
0000 59 .ds 1
0001 60 _cur_x::
0001 61 .ds 2
0003 62 _cur_y::
0003 63 .ds 2
64 ;--------------------------------------------------------
65 ; absolute external ram data
66 ;--------------------------------------------------------
67 .area _DABS (ABS)
68 ;--------------------------------------------------------
69 ; global & static initialisations
70 ;--------------------------------------------------------
71 .area _HOME
72 .area _GSINIT
73 .area _GSFINAL
74 .area _GSINIT
75 ;--------------------------------------------------------
76 ; Home
77 ;--------------------------------------------------------
78 .area _HOME
79 .area _HOME
80 ;--------------------------------------------------------
81 ; code
82 ;--------------------------------------------------------
83 .area _CODE
84 ;boot_rom.c:26: int putchar(int c) {
85 ; ---------------------------------
86 ; Function putchar
87 ; ---------------------------------
0000 88 _putchar::
0000 DD E5 [15] 89 push ix
0002 DD 21 00 00 [14] 90 ld ix,#0
0006 DD 39 [15] 91 add ix,sp
0008 21 F5 FF [10] 92 ld hl, #-11
000B 39 [11] 93 add hl, sp
000C F9 [ 6] 94 ld sp, hl
95 ;boot_rom.c:28: unsigned int *dptr = (unsigned int*)(VGA_WIDTH*(8*cur_y) + 8*cur_x);
000D 2Ar03r00 [16] 96 ld hl, (_cur_y)
0010 29 [11] 97 add hl, hl
0011 29 [11] 98 add hl, hl
0012 29 [11] 99 add hl, hl
0013 ED 4Br61r01 [20] 100 ld bc, (_VGA_WIDTH)
0017 E5 [11] 101 push hl
0018 C5 [11] 102 push bc
0019 CDr00r00 [17] 103 call __mulint
001C F1 [10] 104 pop af
001D F1 [10] 105 pop af
001E 4D [ 4] 106 ld c, l
001F 44 [ 4] 107 ld b, h
0020 2Ar01r00 [16] 108 ld hl, (_cur_x)
0023 29 [11] 109 add hl, hl
0024 29 [11] 110 add hl, hl
0025 29 [11] 111 add hl, hl
0026 09 [11] 112 add hl, bc
0027 33 [ 6] 113 inc sp
0028 33 [ 6] 114 inc sp
0029 E5 [11] 115 push hl
116 ;boot_rom.c:31: if(c < 32) {
002A DD 7E 04 [19] 117 ld a, 4 (ix)
002D D6 20 [ 7] 118 sub a, #0x20
002F DD 7E 05 [19] 119 ld a, 5 (ix)
0032 17 [ 4] 120 rla
0033 3F [ 4] 121 ccf
0034 1F [ 4] 122 rra
0035 DE 80 [ 7] 123 sbc a, #0x80
0037 30 42 [12] 124 jr NC,00108$
125 ;boot_rom.c:32: if(c == '\r') { cur_x=0; }
0039 DD 7E 04 [19] 126 ld a, 4 (ix)
003C D6 0D [ 7] 127 sub a, #0x0d
003E DD B6 05 [19] 128 or a, 5 (ix)
0041 20 06 [12] 129 jr NZ,00102$
0043 21 00 00 [10] 130 ld hl, #0x0000
0046 22r01r00 [16] 131 ld (_cur_x), hl
0049 132 00102$:
133 ;boot_rom.c:33: if(c == '\n') {
0049 DD 7E 04 [19] 134 ld a, 4 (ix)
004C D6 0A [ 7] 135 sub a, #0x0a
004E DD B6 05 [19] 136 or a, 5 (ix)
0051 C2r5Cr01 [10] 137 jp NZ,00122$
138 ;boot_rom.c:34: cur_y++;
0054 FD 21r03r00 [14] 139 ld iy, #_cur_y
0058 FD 34 00 [23] 140 inc 0 (iy)
005B 20 03 [12] 141 jr NZ,00192$
005D FD 34 01 [23] 142 inc 1 (iy)
0060 143 00192$:
144 ;boot_rom.c:35: cur_x=0;
0060 21 00 00 [10] 145 ld hl, #0x0000
0063 22r01r00 [16] 146 ld (_cur_x), hl
147 ;boot_rom.c:36: if(cur_y >= 12) { cur_y = 0; }
0066 FD 7E 00 [19] 148 ld a, 0 (iy)
0069 D6 0C [ 7] 149 sub a, #0x0c
006B FD 7E 01 [19] 150 ld a, 1 (iy)
006E DE 00 [ 7] 151 sbc a, #0x00
0070 DAr5Cr01 [10] 152 jp C,00122$
0073 2E 00 [ 7] 153 ld l, #0x00
0075 22r03r00 [16] 154 ld (_cur_y), hl
155 ;boot_rom.c:38: return;
0078 C3r5Cr01 [10] 156 jp 00122$
007B 157 00108$:
158 ;boot_rom.c:41: if(c < 0) return;
007B DD CB 05 7E [20] 159 bit 7, 5 (ix)
007F C2r5Cr01 [10] 160 jp NZ,00122$
161 ;boot_rom.c:43: p = font+8*(unsigned char)(c-32);
0082 01r00r00 [10] 162 ld bc, #_font+0
0085 DD 7E 04 [19] 163 ld a, 4 (ix)
0088 C6 E0 [ 7] 164 add a, #0xe0
008A 6F [ 4] 165 ld l, a
008B 26 00 [ 7] 166 ld h, #0x00
008D 29 [11] 167 add hl, hl
008E 29 [11] 168 add hl, hl
008F 29 [11] 169 add hl, hl
0090 09 [11] 170 add hl, bc
0091 DD 75 F7 [19] 171 ld -9 (ix), l
0094 DD 74 F8 [19] 172 ld -8 (ix), h
173 ;boot_rom.c:44: for(i=0;i<8;i++) {
0097 01 00 00 [10] 174 ld bc, #0x0000
009A 175 00120$:
176 ;boot_rom.c:45: unsigned char l = *p++;
009A DD 6E F7 [19] 177 ld l, -9 (ix)
009D DD 66 F8 [19] 178 ld h, -8 (ix)
00A0 7E [ 7] 179 ld a, (hl)
00A1 DD 77 FD [19] 180 ld -3 (ix), a
00A4 DD 7E F7 [19] 181 ld a, -9 (ix)
00A7 C6 02 [ 7] 182 add a, #0x02
00A9 DD 77 F7 [19] 183 ld -9 (ix), a
00AC 30 03 [12] 184 jr NC,00193$
00AE DD 34 F8 [23] 185 inc -8 (ix)
00B1 186 00193$:
187 ;boot_rom.c:46: for(j=0;j<8;j++) {
00B1 DD 36 FE 08 [19] 188 ld -2 (ix), #0x08
00B5 DD 36 FF 00 [19] 189 ld -1 (ix), #0x00
00B9 D1 [10] 190 pop de
00BA D5 [11] 191 push de
00BB 192 00119$:
193 ;boot_rom.c:47: *dptr++ = (l & 0x80) ? color : 0x00;
00BB DD 73 FB [19] 194 ld -5 (ix), e
00BE DD 72 FC [19] 195 ld -4 (ix), d
00C1 13 [ 6] 196 inc de
00C2 13 [ 6] 197 inc de
00C3 DD CB FD 7E [20] 198 bit 7, -3 (ix)
00C7 28 0C [12] 199 jr Z,00124$
00C9 3Ar06r00 [13] 200 ld a,(#_color + 0)
00CC DD 77 F9 [19] 201 ld -7 (ix), a
00CF DD 36 FA 00 [19] 202 ld -6 (ix), #0x00
00D3 18 08 [12] 203 jr 00125$
00D5 204 00124$:
00D5 DD 36 F9 00 [19] 205 ld -7 (ix), #0x00
00D9 DD 36 FA 00 [19] 206 ld -6 (ix), #0x00
00DD 207 00125$:
00DD DD 6E FB [19] 208 ld l, -5 (ix)
00E0 DD 66 FC [19] 209 ld h, -4 (ix)
00E3 DD 7E F9 [19] 210 ld a, -7 (ix)
00E6 77 [ 7] 211 ld (hl), a
00E7 23 [ 6] 212 inc hl
00E8 DD 7E FA [19] 213 ld a, -6 (ix)
00EB 77 [ 7] 214 ld (hl), a
215 ;boot_rom.c:48: l <<= 1;
00EC DD 7E FD [19] 216 ld a, -3 (ix)
00EF 87 [ 4] 217 add a, a
00F0 DD 77 FD [19] 218 ld -3 (ix), a
00F3 DD 6E FE [19] 219 ld l, -2 (ix)
00F6 DD 66 FF [19] 220 ld h, -1 (ix)
00F9 2B [ 6] 221 dec hl
00FA DD 75 FE [19] 222 ld -2 (ix), l
00FD DD 74 FF [19] 223 ld -1 (ix), h
224 ;boot_rom.c:46: for(j=0;j<8;j++) {
0100 7C [ 4] 225 ld a, h
0101 B5 [ 4] 226 or a, l
0102 20 B7 [12] 227 jr NZ,00119$
228 ;boot_rom.c:50: dptr += (VGA_WIDTH-8);
0104 2Ar61r01 [16] 229 ld hl, (_VGA_WIDTH)
0107 7D [ 4] 230 ld a, l
0108 C6 F8 [ 7] 231 add a, #0xf8
010A 6F [ 4] 232 ld l, a
010B 7C [ 4] 233 ld a, h
010C CE FF [ 7] 234 adc a, #0xff
010E 67 [ 4] 235 ld h, a
010F 29 [11] 236 add hl, hl
0110 19 [11] 237 add hl, de
0111 33 [ 6] 238 inc sp
0112 33 [ 6] 239 inc sp
0113 E5 [11] 240 push hl
241 ;boot_rom.c:44: for(i=0;i<8;i++) {
0114 03 [ 6] 242 inc bc
0115 79 [ 4] 243 ld a, c
0116 D6 08 [ 7] 244 sub a, #0x08
0118 78 [ 4] 245 ld a, b
0119 17 [ 4] 246 rla
011A 3F [ 4] 247 ccf
011B 1F [ 4] 248 rra
011C DE 80 [ 7] 249 sbc a, #0x80
011E DAr9Ar00 [10] 250 jp C, 00120$
251 ;boot_rom.c:53: cur_x++;
0121 FD 21r01r00 [14] 252 ld iy, #_cur_x
0125 FD 34 00 [23] 253 inc 0 (iy)
0128 20 03 [12] 254 jr NZ,00195$
012A FD 34 01 [23] 255 inc 1 (iy)
012D 256 00195$:
257 ;boot_rom.c:54: if(cur_x >= 20) {
012D FD 7E 00 [19] 258 ld a, 0 (iy)
0130 D6 14 [ 7] 259 sub a, #0x14
0132 FD 7E 01 [19] 260 ld a, 1 (iy)
0135 DE 00 [ 7] 261 sbc a, #0x00
0137 38 23 [12] 262 jr C,00116$
263 ;boot_rom.c:55: cur_x = 0;
0139 21 00 00 [10] 264 ld hl, #0x0000
013C 22r01r00 [16] 265 ld (_cur_x), hl
266 ;boot_rom.c:56: cur_y++;
013F FD 21r03r00 [14] 267 ld iy, #_cur_y
0143 FD 34 00 [23] 268 inc 0 (iy)
0146 20 03 [12] 269 jr NZ,00196$
0148 FD 34 01 [23] 270 inc 1 (iy)
014B 271 00196$:
272 ;boot_rom.c:58: if(cur_y >= 12)
014B FD 7E 00 [19] 273 ld a, 0 (iy)
014E D6 0C [ 7] 274 sub a, #0x0c
0150 FD 7E 01 [19] 275 ld a, 1 (iy)
0153 DE 00 [ 7] 276 sbc a, #0x00
0155 38 05 [12] 277 jr C,00116$
278 ;boot_rom.c:59: cur_y = 0;
0157 2E 00 [ 7] 279 ld l, #0x00
0159 22r03r00 [16] 280 ld (_cur_y), hl
015C 281 00116$:
282 ;boot_rom.c:61: return;
015C 283 00122$:
284 ;boot_rom.c:62: }
015C DD F9 [10] 285 ld sp, ix
015E DD E1 [14] 286 pop ix
0160 C9 [10] 287 ret
0161 288 _VGA_WIDTH:
0161 40 01 289 .dw #0x0140
0163 290 _VGA_HEIGHT:
0163 C8 00 291 .dw #0x00c8
292 ;boot_rom.c:65: void put_pixel(unsigned int x, unsigned int y, unsigned char color) {
293 ; ---------------------------------
294 ; Function put_pixel
295 ; ---------------------------------
0165 296 _put_pixel::
297 ;boot_rom.c:66: *((unsigned int*)(VGA_WIDTH*y+x)) = color;
0165 2Ar61r01 [16] 298 ld hl, (_VGA_WIDTH)
0168 FD 21 04 00 [14] 299 ld iy, #4
016C FD 39 [15] 300 add iy, sp
016E FD 4E 00 [19] 301 ld c, 0 (iy)
0171 FD 46 01 [19] 302 ld b, 1 (iy)
0174 C5 [11] 303 push bc
0175 E5 [11] 304 push hl
0176 CDr00r00 [17] 305 call __mulint
0179 F1 [10] 306 pop af
017A F1 [10] 307 pop af
017B 4D [ 4] 308 ld c, l
017C 44 [ 4] 309 ld b, h
017D 79 [ 4] 310 ld a, c
017E 21 02 00 [10] 311 ld hl, #2
0181 39 [11] 312 add hl, sp
0182 86 [ 7] 313 add a, (hl)
0183 4F [ 4] 314 ld c, a
0184 78 [ 4] 315 ld a, b
0185 23 [ 6] 316 inc hl
0186 8E [ 7] 317 adc a, (hl)
0187 69 [ 4] 318 ld l, c
0188 67 [ 4] 319 ld h, a
0189 FD 21 06 00 [14] 320 ld iy, #6
018D FD 39 [15] 321 add iy, sp
018F FD 4E 00 [19] 322 ld c, 0 (iy)
0192 06 00 [ 7] 323 ld b, #0x00
0194 71 [ 7] 324 ld (hl), c
0195 23 [ 6] 325 inc hl
0196 70 [ 7] 326 ld (hl), b
327 ;boot_rom.c:67: }
0197 C9 [10] 328 ret
329 ;boot_rom.c:69: void cls(unsigned char color) {
330 ; ---------------------------------
331 ; Function cls
332 ; ---------------------------------
0198 333 _cls::
0198 DD E5 [15] 334 push ix
019A DD 21 00 00 [14] 335 ld ix,#0
019E DD 39 [15] 336 add ix,sp
01A0 3B [ 6] 337 dec sp
338 ;boot_rom.c:73: for(i=0;i<VGA_HEIGHT;i++) {
01A1 01 00 00 [10] 339 ld bc, #0x0000
01A4 340 00107$:
01A4 2Ar63r01 [16] 341 ld hl, (_VGA_HEIGHT)
01A7 79 [ 4] 342 ld a, c
01A8 95 [ 4] 343 sub a, l
01A9 78 [ 4] 344 ld a, b
01AA 9C [ 4] 345 sbc a, h
01AB 30 32 [12] 346 jr NC,00102$
347 ;boot_rom.c:74: for(unsigned int x=0;x<VGA_HEIGHT;x++) {
01AD DD 7E 04 [19] 348 ld a, 4 (ix)
01B0 DD 77 FF [19] 349 ld -1 (ix), a
01B3 11 00 00 [10] 350 ld de, #0x0000
01B6 351 00104$:
01B6 2Ar63r01 [16] 352 ld hl, (_VGA_HEIGHT)
01B9 7B [ 4] 353 ld a, e
01BA 95 [ 4] 354 sub a, l
01BB 7A [ 4] 355 ld a, d
01BC 9C [ 4] 356 sbc a, h
01BD 30 17 [12] 357 jr NC,00115$
358 ;boot_rom.c:76: put_pixel(x,i, color);
01BF C5 [11] 359 push bc
01C0 D5 [11] 360 push de
01C1 DD 7E FF [19] 361 ld a, -1 (ix)
01C4 F5 [11] 362 push af
01C5 33 [ 6] 363 inc sp
01C6 C5 [11] 364 push bc
01C7 D5 [11] 365 push de
01C8 CDr65r01 [17] 366 call _put_pixel
01CB F1 [10] 367 pop af
01CC F1 [10] 368 pop af
01CD 33 [ 6] 369 inc sp
01CE D1 [10] 370 pop de
01CF C1 [10] 371 pop bc
372 ;boot_rom.c:77: color++;
01D0 DD 34 FF [23] 373 inc -1 (ix)
374 ;boot_rom.c:74: for(unsigned int x=0;x<VGA_HEIGHT;x++) {
01D3 13 [ 6] 375 inc de
01D4 18 E0 [12] 376 jr 00104$
01D6 377 00115$:
01D6 DD 7E FF [19] 378 ld a, -1 (ix)
01D9 DD 77 04 [19] 379 ld 4 (ix), a
380 ;boot_rom.c:73: for(i=0;i<VGA_HEIGHT;i++) {
01DC 03 [ 6] 381 inc bc
01DD 18 C5 [12] 382 jr 00107$
01DF 383 00102$:
384 ;boot_rom.c:81: cur_x = 0;
01DF 21 00 00 [10] 385 ld hl, #0x0000
01E2 22r01r00 [16] 386 ld (_cur_x), hl
387 ;boot_rom.c:82: cur_y = 0;
01E5 2E 00 [ 7] 388 ld l, #0x00
01E7 22r03r00 [16] 389 ld (_cur_y), hl
390 ;boot_rom.c:83: }
01EA 33 [ 6] 391 inc sp
01EB DD E1 [14] 392 pop ix
01ED C9 [10] 393 ret
394 ;boot_rom.c:86: void draw_line(unsigned int x, unsigned int y,
395 ; ---------------------------------
396 ; Function draw_line
397 ; ---------------------------------
01EE 398 _draw_line::
01EE DD E5 [15] 399 push ix
01F0 DD 21 00 00 [14] 400 ld ix,#0
01F4 DD 39 [15] 401 add ix,sp
01F6 21 EE FF [10] 402 ld hl, #-18
01F9 39 [11] 403 add hl, sp
01FA F9 [ 6] 404 ld sp, hl
405 ;boot_rom.c:90: int dx1 = (x<x2)?1:-1;
01FB DD 7E 04 [19] 406 ld a, 4 (ix)
01FE DD 96 08 [19] 407 sub a, 8 (ix)
0201 DD 7E 05 [19] 408 ld a, 5 (ix)
0204 DD 9E 09 [19] 409 sbc a, 9 (ix)
0207 30 05 [12] 410 jr NC,00112$
0209 01 01 00 [10] 411 ld bc, #0x0001
020C 18 03 [12] 412 jr 00113$
020E 413 00112$:
020E 01 FF FF [10] 414 ld bc, #0xffff
0211 415 00113$:
0211 DD 71 F4 [19] 416 ld -12 (ix), c
0214 DD 70 F5 [19] 417 ld -11 (ix), b
418 ;boot_rom.c:91: int dy1 = (y<y2)?1:-1;
0217 DD 7E 06 [19] 419 ld a, 6 (ix)
021A DD 96 0A [19] 420 sub a, 10 (ix)
021D DD 7E 07 [19] 421 ld a, 7 (ix)
0220 DD 9E 0B [19] 422 sbc a, 11 (ix)
0223 30 05 [12] 423 jr NC,00114$
0225 01 01 00 [10] 424 ld bc, #0x0001
0228 18 03 [12] 425 jr 00115$
022A 426 00114$:
022A 01 FF FF [10] 427 ld bc, #0xffff
022D 428 00115$:
022D DD 71 F6 [19] 429 ld -10 (ix), c
0230 DD 70 F7 [19] 430 ld -9 (ix), b
431 ;boot_rom.c:94: longest = abs(x2 - x);
0233 DD 7E 08 [19] 432 ld a, 8 (ix)
0236 DD 96 04 [19] 433 sub a, 4 (ix)
0239 4F [ 4] 434 ld c, a
023A DD 7E 09 [19] 435 ld a, 9 (ix)
023D DD 9E 05 [19] 436 sbc a, 5 (ix)
0240 47 [ 4] 437 ld b, a
0241 C5 [11] 438 push bc
0242 CDr00r00 [17] 439 call _abs
0245 F1 [10] 440 pop af
0246 DD 75 FE [19] 441 ld -2 (ix), l
0249 DD 74 FF [19] 442 ld -1 (ix), h
443 ;boot_rom.c:95: shortest = abs(y2 - y);
024C DD 7E 0A [19] 444 ld a, 10 (ix)
024F DD 96 06 [19] 445 sub a, 6 (ix)
0252 5F [ 4] 446 ld e, a
0253 DD 7E 0B [19] 447 ld a, 11 (ix)
0256 DD 9E 07 [19] 448 sbc a, 7 (ix)
0259 57 [ 4] 449 ld d, a
025A D5 [11] 450 push de
025B D5 [11] 451 push de
025C CDr00r00 [17] 452 call _abs
025F F1 [10] 453 pop af
0260 D1 [10] 454 pop de
0261 DD 75 FC [19] 455 ld -4 (ix), l
0264 DD 74 FD [19] 456 ld -3 (ix), h
457 ;boot_rom.c:96: if(longest<shortest) {
0267 DD 7E FE [19] 458 ld a, -2 (ix)
026A DD 96 FC [19] 459 sub a, -4 (ix)
026D DD 7E FF [19] 460 ld a, -1 (ix)
0270 DD 9E FD [19] 461 sbc a, -3 (ix)
0273 30 27 [12] 462 jr NC,00102$
463 ;boot_rom.c:97: longest = abs(y2 - y);
0275 D5 [11] 464 push de
0276 CDr00r00 [17] 465 call _abs
0279 F1 [10] 466 pop af
027A DD 75 FE [19] 467 ld -2 (ix), l
027D DD 74 FF [19] 468 ld -1 (ix), h
469 ;boot_rom.c:98: shortest = abs(x2 - x);
0280 C5 [11] 470 push bc
0281 CDr00r00 [17] 471 call _abs
0284 F1 [10] 472 pop af
0285 DD 75 FC [19] 473 ld -4 (ix), l
0288 DD 74 FD [19] 474 ld -3 (ix), h
475 ;boot_rom.c:99: dx2 = 0;
028B 01 00 00 [10] 476 ld bc, #0x0000
477 ;boot_rom.c:100: dy2 = dy1;
028E DD 7E F6 [19] 478 ld a, -10 (ix)
0291 DD 77 F8 [19] 479 ld -8 (ix), a
0294 DD 7E F7 [19] 480 ld a, -9 (ix)
0297 DD 77 F9 [19] 481 ld -7 (ix), a
029A 18 0E [12] 482 jr 00103$
029C 483 00102$:
484 ;boot_rom.c:102: dx2 = dx1;
029C DD 4E F4 [19] 485 ld c, -12 (ix)
029F DD 46 F5 [19] 486 ld b, -11 (ix)
487 ;boot_rom.c:103: dy2 = 0;
02A2 DD 36 F8 00 [19] 488 ld -8 (ix), #0x00
02A6 DD 36 F9 00 [19] 489 ld -7 (ix), #0x00
02AA 490 00103$:
491 ;boot_rom.c:106: numerator = longest/2;
02AA DD 5E FE [19] 492 ld e, -2 (ix)
02AD DD 56 FF [19] 493 ld d, -1 (ix)
02B0 CB 3A [ 8] 494 srl d
02B2 CB 1B [ 8] 495 rr e
496 ;boot_rom.c:107: for(i=0;i<=longest;i++) {
02B4 DD 7E FE [19] 497 ld a, -2 (ix)
02B7 DD 96 FC [19] 498 sub a, -4 (ix)
02BA DD 77 F2 [19] 499 ld -14 (ix), a
02BD DD 7E FF [19] 500 ld a, -1 (ix)
02C0 DD 9E FD [19] 501 sbc a, -3 (ix)
02C3 DD 77 F3 [19] 502 ld -13 (ix), a
02C6 DD 36 FA 00 [19] 503 ld -6 (ix), #0x00
02CA DD 36 FB 00 [19] 504 ld -5 (ix), #0x00
02CE 505 00108$:
506 ;boot_rom.c:108: put_pixel(x,y,color) ;
02CE C5 [11] 507 push bc
02CF D5 [11] 508 push de
02D0 DD 7E 0C [19] 509 ld a, 12 (ix)
02D3 F5 [11] 510 push af
02D4 33 [ 6] 511 inc sp
02D5 DD 6E 06 [19] 512 ld l, 6 (ix)
02D8 DD 66 07 [19] 513 ld h, 7 (ix)
02DB E5 [11] 514 push hl
02DC DD 6E 04 [19] 515 ld l, 4 (ix)
02DF DD 66 05 [19] 516 ld h, 5 (ix)
02E2 E5 [11] 517 push hl
02E3 CDr65r01 [17] 518 call _put_pixel
02E6 F1 [10] 519 pop af
02E7 F1 [10] 520 pop af
02E8 33 [ 6] 521 inc sp
02E9 D1 [10] 522 pop de
02EA C1 [10] 523 pop bc
524 ;boot_rom.c:110: numerator += shortest ;
02EB DD 7E FC [19] 525 ld a, -4 (ix)
02EE 83 [ 4] 526 add a, e
02EF DD 77 F0 [19] 527 ld -16 (ix), a
02F2 DD 7E FD [19] 528 ld a, -3 (ix)
02F5 8A [ 4] 529 adc a, d
02F6 DD 77 F1 [19] 530 ld -15 (ix), a
531 ;boot_rom.c:109: if(numerator >= longest-shortest) {
02F9 7B [ 4] 532 ld a, e
02FA DD 96 F2 [19] 533 sub a, -14 (ix)
02FD 7A [ 4] 534 ld a, d
02FE DD 9E F3 [19] 535 sbc a, -13 (ix)
0301 38 4D [12] 536 jr C,00105$
537 ;boot_rom.c:110: numerator += shortest ;
538 ;boot_rom.c:111: numerator -= longest ;
0303 DD 7E F0 [19] 539 ld a, -16 (ix)
0306 DD 56 F1 [19] 540 ld d, -15 (ix)
0309 DD 96 FE [19] 541 sub a, -2 (ix)
030C 5F [ 4] 542 ld e, a
030D 7A [ 4] 543 ld a, d
030E DD 9E FF [19] 544 sbc a, -1 (ix)
0311 57 [ 4] 545 ld d, a
546 ;boot_rom.c:112: x += dx1;
0312 DD 7E F4 [19] 547 ld a, -12 (ix)
0315 DD 77 EE [19] 548 ld -18 (ix), a
0318 DD 7E F5 [19] 549 ld a, -11 (ix)
031B DD 77 EF [19] 550 ld -17 (ix), a
031E DD 7E 04 [19] 551 ld a, 4 (ix)
0321 DD 86 EE [19] 552 add a, -18 (ix)
0324 DD 77 04 [19] 553 ld 4 (ix), a
0327 DD 7E 05 [19] 554 ld a, 5 (ix)
032A DD 8E EF [19] 555 adc a, -17 (ix)
032D DD 77 05 [19] 556 ld 5 (ix), a
557 ;boot_rom.c:113: y += dy1;
0330 DD 7E F6 [19] 558 ld a, -10 (ix)
0333 DD 77 EE [19] 559 ld -18 (ix), a
0336 DD 7E F7 [19] 560 ld a, -9 (ix)
0339 DD 77 EF [19] 561 ld -17 (ix), a
033C DD 7E 06 [19] 562 ld a, 6 (ix)
033F DD 86 EE [19] 563 add a, -18 (ix)
0342 DD 77 06 [19] 564 ld 6 (ix), a
0345 DD 7E 07 [19] 565 ld a, 7 (ix)
0348 DD 8E EF [19] 566 adc a, -17 (ix)
034B DD 77 07 [19] 567 ld 7 (ix), a
034E 18 39 [12] 568 jr 00109$
0350 569 00105$:
570 ;boot_rom.c:115: numerator += shortest ;
0350 DD 5E F0 [19] 571 ld e, -16 (ix)
0353 DD 56 F1 [19] 572 ld d, -15 (ix)
573 ;boot_rom.c:116: x += dx2;
0356 33 [ 6] 574 inc sp
0357 33 [ 6] 575 inc sp
0358 C5 [11] 576 push bc
0359 DD 7E 04 [19] 577 ld a, 4 (ix)
035C DD 86 EE [19] 578 add a, -18 (ix)
035F DD 77 04 [19] 579 ld 4 (ix), a
0362 DD 7E 05 [19] 580 ld a, 5 (ix)
0365 DD 8E EF [19] 581 adc a, -17 (ix)
0368 DD 77 05 [19] 582 ld 5 (ix), a
583 ;boot_rom.c:117: y += dy2;
036B DD 7E F8 [19] 584 ld a, -8 (ix)
036E DD 77 EE [19] 585 ld -18 (ix), a
0371 DD 7E F9 [19] 586 ld a, -7 (ix)
0374 DD 77 EF [19] 587 ld -17 (ix), a
0377 DD 7E 06 [19] 588 ld a, 6 (ix)
037A DD 86 EE [19] 589 add a, -18 (ix)
037D DD 77 06 [19] 590 ld 6 (ix), a
0380 DD 7E 07 [19] 591 ld a, 7 (ix)
0383 DD 8E EF [19] 592 adc a, -17 (ix)
0386 DD 77 07 [19] 593 ld 7 (ix), a
0389 594 00109$:
595 ;boot_rom.c:107: for(i=0;i<=longest;i++) {
0389 DD 34 FA [23] 596 inc -6 (ix)
038C 20 03 [12] 597 jr NZ,00142$
038E DD 34 FB [23] 598 inc -5 (ix)
0391 599 00142$:
0391 DD 7E FE [19] 600 ld a, -2 (ix)
0394 DD 96 FA [19] 601 sub a, -6 (ix)
0397 DD 7E FF [19] 602 ld a, -1 (ix)
039A DD 9E FB [19] 603 sbc a, -5 (ix)
039D D2rCEr02 [10] 604 jp NC, 00108$
605 ;boot_rom.c:120: }
03A0 DD F9 [10] 606 ld sp, ix
03A2 DD E1 [14] 607 pop ix
03A4 C9 [10] 608 ret
609 ;boot_rom.c:123: void main() {
610 ; ---------------------------------
611 ; Function main
612 ; ---------------------------------
03A5 613 _main::
614 ;boot_rom.c:124: while(1) {
03A5 615 00108$:
616 ;boot_rom.c:127: input0_cache = input0;
03A5 3A 00 40 [13] 617 ld a,(#_input0 + 0)
03A8 FD 21r04r00 [14] 618 ld iy, #_input0_cache
03AC FD 77 00 [19] 619 ld 0 (iy), a
620 ;boot_rom.c:128: hsync = input0_cache & 0x80;
03AF FD 4E 00 [19] 621 ld c, 0 (iy)
03B2 79 [ 4] 622 ld a, c
03B3 E6 80 [ 7] 623 and a, #0x80
03B5 32r00r00 [13] 624 ld (#_hsync + 0),a
625 ;boot_rom.c:129: vsync = input0_cache & 0x40;
03B8 79 [ 4] 626 ld a, c
03B9 E6 40 [ 7] 627 and a, #0x40
03BB 32r02r00 [13] 628 ld (#_vsync + 0),a
629 ;boot_rom.c:131: if(hsync && !hsync_last){
03BE 3Ar00r00 [13] 630 ld a,(#_hsync + 0)
03C1 B7 [ 4] 631 or a, a
03C2 28 0A [12] 632 jr Z,00102$
03C4 3Ar01r00 [13] 633 ld a,(#_hsync_last + 0)
03C7 B7 [ 4] 634 or a, a
03C8 20 04 [12] 635 jr NZ,00102$
636 ;boot_rom.c:132: y++;
03CA 21r00r00 [10] 637 ld hl, #_y+0
03CD 34 [11] 638 inc (hl)
03CE 639 00102$:
640 ;boot_rom.c:134: if(vsync && !vsync_last){
03CE 3Ar02r00 [13] 641 ld a,(#_vsync + 0)
03D1 B7 [ 4] 642 or a, a
03D2 28 11 [12] 643 jr Z,00105$
03D4 3Ar03r00 [13] 644 ld a,(#_vsync_last + 0)
03D7 B7 [ 4] 645 or a, a
03D8 20 0B [12] 646 jr NZ,00105$
647 ;boot_rom.c:135: y=0;
03DA 21r00r00 [10] 648 ld hl,#_y + 0
03DD 36 00 [10] 649 ld (hl), #0x00
650 ;boot_rom.c:138: input1_cache = input1;
03DF 3A 01 40 [13] 651 ld a,(#_input1 + 0)
03E2 32r05r00 [13] 652 ld (#_input1_cache + 0),a
03E5 653 00105$:
654 ;boot_rom.c:141: hsync_last = hsync;
03E5 3Ar00r00 [13] 655 ld a,(#_hsync + 0)
03E8 32r01r00 [13] 656 ld (#_hsync_last + 0),a
657 ;boot_rom.c:142: vsync_last = vsync;
03EB 3Ar02r00 [13] 658 ld a,(#_vsync + 0)
03EE 32r03r00 [13] 659 ld (#_vsync_last + 0),a
660 ;boot_rom.c:144: }
03F1 18 B2 [12] 661 jr 00108$
662 .area _CODE
663 .area _INITIALIZER
0000 664 __xinit__y:
0000 00 665 .db #0x00 ; 0
0001 666 __xinit__cur_x:
0001 00 00 667 .dw #0x0000
0003 668 __xinit__cur_y:
0003 00 00 669 .dw #0x0000
670 .area _CABS (ABS)

241
src/boot_rom.map Normal file
View File

@@ -0,0 +1,241 @@
ASxxxx Linker V03.00 + NoICE + sdld, page 1.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000000 .__.ABS.
00000000 l__BSEG
00000000 l__BSS
00000000 l__CABS
00000000 l__DABS
00000000 l__HEADER
00000000 l__HEAP
00000000 l__HOME
00000000 s__CABS
00000000 s__DABS
00000000 s__HEADER
00000000 s__HEADER0
00000000 s__HEADER1
00000000 s__HEADER2
00000000 s__HEADER3
00000000 s__HEADER4
00000000 s__HEADER5
00000000 s__HEADER6
00000000 s__HEADER7
00000000 s__HEADER8
00000001 l__GSFINAL
00000003 l__HEADER0
00000003 l__HEADER2
00000003 l__HEADER3
00000003 l__HEADER4
00000003 l__HEADER5
00000003 l__HEADER6
00000003 l__HEADER7
00000004 l__HEADER1
00000007 l__DATA
0000000C l__HEADER8
0000000F l__GSINIT
00000200 s__CODE
00000305 l__INITIALIZED
00000305 l__INITIALIZER
00000423 l__CODE
00000623 s__HOME
00000623 s__INITIALIZER
00000928 s__GSINIT
00000937 s__GSFINAL
00004000 _input0 boot_rom
00004001 _input1 boot_rom
00008000 s__DATA
00008007 s__INITIALIZED
0000830C s__BSEG
0000830C s__BSS
0000830C s__HEAP
ASxxxx Linker V03.00 + NoICE + sdld, page 2.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_CODE 00000200 00000423 = 1059. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000200 __clock crt0
00000204 _exit crt0
0000020A _putchar boot_rom
0000036B _VGA_WIDTH boot_rom
0000036D _VGA_HEIGHT boot_rom
0000036F _put_pixel boot_rom
000003A2 _cls boot_rom
000003F8 _draw_line boot_rom
000005AF _main boot_rom
000005FD _abs
00000609 __mulint
0000060F __mul16
ASxxxx Linker V03.00 + NoICE + sdld, page 3.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER0 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 4.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER1 00000000 00000004 = 4. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 5.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER2 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 6.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER3 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 7.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER4 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 8.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER5 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 9.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER6 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 10.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER7 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 11.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HEADER8 00000000 0000000C = 12. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 12.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_INITIALIZER 00000623 00000305 = 773. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 13.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSINIT 00000928 0000000F = 15. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000928 gsinit crt0
ASxxxx Linker V03.00 + NoICE + sdld, page 14.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSFINAL 00000937 00000001 = 1. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00 + NoICE + sdld, page 15.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_DATA 00008000 00000007 = 7. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008000 _hsync boot_rom
00008001 _hsync_last boot_rom
00008002 _vsync boot_rom
00008003 _vsync_last boot_rom
00008004 _input0_cache boot_rom
00008005 _input1_cache boot_rom
00008006 _color boot_rom
ASxxxx Linker V03.00 + NoICE + sdld, page 16.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_INITIALIZED 00008007 00000305 = 773. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008007 _y boot_rom
00008008 _cur_x boot_rom
0000800A _cur_y boot_rom
0000800C _font font
ASxxxx Linker V03.00 + NoICE + sdld, page 17.
Files Linked [ module(s) ]
/usr/bin/../share/sdcc/lib/z80/crt0.rel [ crt0 ]
boot_rom.rel [ boot_rom ]
font.rel [ font ]
Libraries Linked [ object file ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ abs.rel ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ mul.rel ]
ASxxxx Linker V03.00 + NoICE + sdld, page 18.
User Base Address Definitions
_CODE = 0x0200
_DATA = 0x8000

72
src/boot_rom.noi Normal file
View File

@@ -0,0 +1,72 @@
DEF .__.ABS. 0x0
DEF l__BSEG 0x0
DEF l__BSS 0x0
DEF l__CABS 0x0
DEF l__DABS 0x0
DEF l__HEADER 0x0
DEF l__HEAP 0x0
DEF l__HOME 0x0
DEF s__CABS 0x0
DEF s__DABS 0x0
DEF s__HEADER 0x0
DEF s__HEADER0 0x0
DEF s__HEADER1 0x0
DEF s__HEADER2 0x0
DEF s__HEADER3 0x0
DEF s__HEADER4 0x0
DEF s__HEADER5 0x0
DEF s__HEADER6 0x0
DEF s__HEADER7 0x0
DEF s__HEADER8 0x0
DEF l__GSFINAL 0x1
DEF l__HEADER0 0x3
DEF l__HEADER2 0x3
DEF l__HEADER3 0x3
DEF l__HEADER4 0x3
DEF l__HEADER5 0x3
DEF l__HEADER6 0x3
DEF l__HEADER7 0x3
DEF l__HEADER1 0x4
DEF l__DATA 0x7
DEF l__HEADER8 0xC
DEF l__GSINIT 0xF
DEF s__CODE 0x200
DEF l__INITIALIZED 0x305
DEF l__INITIALIZER 0x305
DEF l__CODE 0x423
DEF s__HOME 0x623
DEF s__INITIALIZER 0x623
DEF s__GSINIT 0x928
DEF s__GSFINAL 0x937
DEF _input0 0x4000
DEF _input1 0x4001
DEF s__DATA 0x8000
DEF s__INITIALIZED 0x8007
DEF s__BSEG 0x830C
DEF s__BSS 0x830C
DEF s__HEAP 0x830C
DEF __clock 0x200
DEF _exit 0x204
DEF _putchar 0x20A
DEF _VGA_WIDTH 0x36B
DEF _VGA_HEIGHT 0x36D
DEF _put_pixel 0x36F
DEF _cls 0x3A2
DEF _draw_line 0x3F8
DEF _main 0x5AF
DEF _abs 0x5FD
DEF __mulint 0x609
DEF __mul16 0x60F
DEF gsinit 0x928
DEF _hsync 0x8000
DEF _hsync_last 0x8001
DEF _vsync 0x8002
DEF _vsync_last 0x8003
DEF _input0_cache 0x8004
DEF _input1_cache 0x8005
DEF _color 0x8006
DEF _y 0x8007
DEF _cur_x 0x8008
DEF _cur_y 0x800A
DEF _font 0x800C
LOAD boot_rom.ihx

51
src/boot_rom.sym Normal file
View File

@@ -0,0 +1,51 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 1.
Hexadecimal [16-Bits]
Symbol Table
.__.$$$. = 2710 L
.__.ABS. = 0000 G
.__.CPU. = 0000 L
.__.H$L. = 0000 L
0 _VGA_HEIGHT 0163 GR
0 _VGA_WIDTH 0161 GR
__mulint **** GX
7 __xinit__cur_x 0001 R
7 __xinit__cur_y 0003 R
7 __xinit__y 0000 R
_abs **** GX
0 _cls 0198 GR
1 _color 0006 GR
2 _cur_x 0001 GR
2 _cur_y 0003 GR
0 _draw_line 01EE GR
_font **** GX
1 _hsync 0000 GR
1 _hsync_last 0001 GR
_input0 = 4000 G
1 _input0_cache 0004 GR
_input1 = 4001 G
1 _input1_cache 0005 GR
0 _main 03A5 GR
0 _put_pixel 0165 GR
0 _putchar 0000 GR
1 _vsync 0002 GR
1 _vsync_last 0003 GR
2 _y 0000 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 2.
Hexadecimal [16-Bits]
Area Table
0 _CODE size 3F3 flags 0
1 _DATA size 7 flags 0
2 _INITIALIZED size 5 flags 0
3 _DABS size 0 flags 8
4 _HOME size 0 flags 0
5 _GSINIT size 0 flags 0
6 _GSFINAL size 0 flags 0
7 _INITIALIZER size 5 flags 0
8 _CABS size 0 flags 8

816
src/font.asm Normal file
View File

@@ -0,0 +1,816 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.8.0 #10562 (Linux)
;--------------------------------------------------------
.module font
.optsdcc -mz80
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _font
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _INITIALIZED
_font::
.ds 768
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area _DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area _HOME
.area _GSINIT
.area _GSFINAL
.area _GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area _HOME
.area _HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area _CODE
.area _CODE
.area _INITIALIZER
__xinit__font:
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x78 ; 120 'x'
.db #0x78 ; 120 'x'
.db #0x78 ; 120 'x'
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0xcc ; 204
.db #0x66 ; 102 'f'
.db #0x33 ; 51 '3'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x36 ; 54 '6'
.db #0x7f ; 127
.db #0x36 ; 54 '6'
.db #0x36 ; 54 '6'
.db #0x7f ; 127
.db #0x36 ; 54 '6'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xd6 ; 214
.db #0xd0 ; 208
.db #0x7c ; 124
.db #0x16 ; 22
.db #0xd6 ; 214
.db #0x7c ; 124
.db #0x10 ; 16
.db #0xe3 ; 227
.db #0xa6 ; 166
.db #0xec ; 236
.db #0x18 ; 24
.db #0x37 ; 55 '7'
.db #0x65 ; 101 'e'
.db #0xc7 ; 199
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x4c ; 76 'L'
.db #0x38 ; 56 '8'
.db #0x45 ; 69 'E'
.db #0xc6 ; 198
.db #0xce ; 206
.db #0x7a ; 122 'z'
.db #0x01 ; 1
.db #0x06 ; 6
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x10 ; 16
.db #0x54 ; 84 'T'
.db #0x38 ; 56 '8'
.db #0xfe ; 254
.db #0x38 ; 56 '8'
.db #0x54 ; 84 'T'
.db #0x10 ; 16
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x7e ; 126
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x03 ; 3
.db #0x06 ; 6
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xde ; 222
.db #0xfe ; 254
.db #0xee ; 238
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x1c ; 28
.db #0x3c ; 60
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0x0e ; 14
.db #0x3c ; 60
.db #0x0e ; 14
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0xfe ; 254
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfc ; 252
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x06 ; 6
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xc6 ; 198
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xc6 ; 198
.db #0xde ; 222
.db #0xde ; 222
.db #0xdc ; 220
.db #0xc0 ; 192
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xee ; 238
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xce ; 206
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xec ; 236
.db #0xf8 ; 248
.db #0xf0 ; 240
.db #0xf8 ; 248
.db #0xec ; 236
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xee ; 238
.db #0xfe ; 254
.db #0xd6 ; 214
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xe6 ; 230
.db #0xf6 ; 246
.db #0xfe ; 254
.db #0xee ; 238
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xea ; 234
.db #0x74 ; 116 't'
.db #0x02 ; 2
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0x7c ; 124
.db #0x0e ; 14
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xfe ; 254
.db #0xfc ; 252
.db #0x00 ; 0
.db #0xe3 ; 227
.db #0x76 ; 118 'v'
.db #0x3c ; 60
.db #0x18 ; 24
.db #0x3c ; 60
.db #0x6e ; 110 'n'
.db #0xc7 ; 199
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x1c ; 28
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x1c ; 28
.db #0x00 ; 0
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x06 ; 6
.db #0x03 ; 3
.db #0x00 ; 0
.db #0x70 ; 112 'p'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x70 ; 112 'p'
.db #0x18 ; 24
.db #0x3c ; 60
.db #0x66 ; 102 'f'
.db #0xc3 ; 195
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xff ; 255
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0x0e ; 14
.db #0x7e ; 126
.db #0xce ; 206
.db #0x7e ; 126
.db #0x00 ; 0
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x06 ; 6
.db #0x06 ; 6
.db #0x7e ; 126
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x3c ; 60
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0xfc ; 252
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x7c ; 124
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0xf8 ; 248
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xcc ; 204
.db #0xd8 ; 216
.db #0xf0 ; 240
.db #0xd8 ; 216
.db #0xcc ; 204
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0xe0 ; 224
.db #0x7c ; 124
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x7e ; 126
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x6c ; 108 'l'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x7c ; 124
.db #0xce ; 206
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x70 ; 112 'p'
.db #0xdb ; 219
.db #0x0e ; 14
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x10 ; 16
.db #0x28 ; 40
.db #0x44 ; 68 'D'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x00 ; 0
.area _CABS (ABS)

101
src/font.c Normal file
View File

@@ -0,0 +1,101 @@
/* Autogenerated file, DO NOT EDIT !!! */
unsigned char font[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x30, 0x78, 0x78, 0x78, 0x30, 0x00, 0x30, 0x00,
0xCC, 0x66, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x36, 0x7F, 0x36, 0x36, 0x7F, 0x36, 0x00,
0x7C, 0xD6, 0xD0, 0x7C, 0x16, 0xD6, 0x7C, 0x10,
0xE3, 0xA6, 0xEC, 0x18, 0x37, 0x65, 0xC7, 0x00,
0x38, 0x4C, 0x38, 0x45, 0xC6, 0xCE, 0x7A, 0x01,
0x06, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0C,
0x60, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x60,
0x10, 0x54, 0x38, 0xFE, 0x38, 0x54, 0x10, 0x00,
0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x30,
0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00,
0x00, 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00,
0x7C, 0xCE, 0xDE, 0xFE, 0xEE, 0xCE, 0x7C, 0x00,
0x1C, 0x3C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x00,
0x7C, 0xCE, 0x0E, 0x1C, 0x38, 0x70, 0xFE, 0x00,
0x7C, 0xCE, 0x0E, 0x3C, 0x0E, 0xCE, 0x7C, 0x00,
0xCE, 0xCE, 0xCE, 0xCE, 0xFE, 0x0E, 0x0E, 0x00,
0xFE, 0xE0, 0xE0, 0xFC, 0x0E, 0x0E, 0xFC, 0x00,
0x7C, 0xE6, 0xE0, 0xFC, 0xE6, 0xE6, 0x7C, 0x00,
0xFE, 0x06, 0x0E, 0x1C, 0x38, 0x38, 0x38, 0x00,
0x7C, 0xE6, 0xE6, 0x7C, 0xE6, 0xE6, 0x7C, 0x00,
0x7C, 0xCE, 0xCE, 0x7E, 0x0E, 0x0E, 0xFC, 0x00,
0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00,
0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x60, 0x00,
0x00, 0x18, 0x30, 0x60, 0x30, 0x18, 0x00, 0x00,
0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00,
0x00, 0x30, 0x18, 0x0C, 0x18, 0x30, 0x00, 0x00,
0x7C, 0xC6, 0x0E, 0x1C, 0x38, 0x00, 0x38, 0x00,
0x7C, 0xC6, 0xDE, 0xDE, 0xDC, 0xC0, 0x7C, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xFE, 0xE6, 0xE6, 0x00,
0xFC, 0xE6, 0xE6, 0xFC, 0xE6, 0xE6, 0xFC, 0x00,
0x7C, 0xE6, 0xE0, 0xE0, 0xE6, 0xE6, 0x7C, 0x00,
0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xFC, 0x00,
0xFE, 0xE0, 0xE0, 0xFE, 0xE0, 0xE0, 0xFE, 0x00,
0xFE, 0xE0, 0xE0, 0xFE, 0xE0, 0xE0, 0xE0, 0x00,
0x7C, 0xE6, 0xE0, 0xEE, 0xE6, 0xE6, 0x7C, 0x00,
0xE6, 0xE6, 0xE6, 0xFE, 0xE6, 0xE6, 0xE6, 0x00,
0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0x0E, 0x0E, 0x0E, 0x0E, 0xCE, 0xCE, 0x7C, 0x00,
0xE6, 0xEC, 0xF8, 0xF0, 0xF8, 0xEC, 0xE6, 0x00,
0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xFE, 0x00,
0xC6, 0xEE, 0xFE, 0xD6, 0xC6, 0xC6, 0xC6, 0x00,
0xC6, 0xE6, 0xF6, 0xFE, 0xEE, 0xE6, 0xE6, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0xFC, 0xE6, 0xE6, 0xFC, 0xE0, 0xE0, 0xE0, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xE6, 0xEA, 0x74, 0x02,
0xFC, 0xE6, 0xE6, 0xFC, 0xE6, 0xE6, 0xE6, 0x00,
0x7C, 0xE6, 0xE0, 0x7C, 0x0E, 0xCE, 0x7C, 0x00,
0xFE, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x38, 0x00,
0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0xFE, 0xFC, 0x00,
0xE3, 0x76, 0x3C, 0x18, 0x3C, 0x6E, 0xC7, 0x00,
0xE6, 0xE6, 0x7C, 0x38, 0x38, 0x38, 0x38, 0x00,
0xFE, 0x0E, 0x1C, 0x38, 0x70, 0xE0, 0xFE, 0x00,
0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1C,
0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x00,
0x70, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x70,
0x18, 0x3C, 0x66, 0xC3, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
0x30, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7C, 0x0E, 0x7E, 0xCE, 0x7E, 0x00,
0xC0, 0xC0, 0xFC, 0xE6, 0xE6, 0xE6, 0xFC, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xE0, 0xE6, 0x7C, 0x00,
0x06, 0x06, 0x7E, 0xCE, 0xCE, 0xCE, 0x7E, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xFE, 0xE0, 0x7E, 0x00,
0x3C, 0x70, 0x70, 0xFC, 0x70, 0x70, 0x70, 0x00,
0x00, 0x00, 0x7C, 0xCE, 0xCE, 0x7E, 0x0E, 0x7C,
0xC0, 0xC0, 0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0x00,
0x18, 0x00, 0x18, 0x38, 0x38, 0x38, 0x38, 0x00,
0x0C, 0x00, 0x0C, 0x1C, 0x1C, 0x1C, 0x1C, 0xF8,
0xC0, 0xC0, 0xCC, 0xD8, 0xF0, 0xD8, 0xCC, 0x00,
0x18, 0x18, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0x00, 0x00, 0xFC, 0xD6, 0xD6, 0xD6, 0xD6, 0x00,
0x00, 0x00, 0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0x00, 0x00, 0xFC, 0xE6, 0xE6, 0xFC, 0xE0, 0xE0,
0x00, 0x00, 0x7E, 0xCE, 0xCE, 0x7E, 0x0E, 0x0E,
0x00, 0x00, 0xFC, 0xE6, 0xE0, 0xE0, 0xE0, 0x00,
0x00, 0x00, 0x7E, 0xE0, 0x7C, 0x0E, 0xFC, 0x00,
0x18, 0x18, 0x7E, 0x38, 0x38, 0x38, 0x38, 0x00,
0x00, 0x00, 0xE6, 0xE6, 0xE6, 0xE6, 0x7E, 0x00,
0x00, 0x00, 0xE6, 0xE6, 0xE6, 0x6C, 0x38, 0x00,
0x00, 0x00, 0xD6, 0xD6, 0xD6, 0xD6, 0xFC, 0x00,
0x00, 0x00, 0xE6, 0x7C, 0x38, 0x7C, 0xCE, 0x00,
0x00, 0x00, 0xCE, 0xCE, 0xCE, 0x7E, 0x0E, 0xFC,
0x00, 0x00, 0xFE, 0x1C, 0x38, 0x70, 0xFE, 0x00,
0x0C, 0x18, 0x18, 0x30, 0x18, 0x18, 0x0C, 0x00,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x60, 0x30, 0x30, 0x18, 0x30, 0x30, 0x60, 0x00,
0x70, 0xDB, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x10, 0x28, 0x44, 0xFE, 0x00, 0x00,
};

816
src/font.lst Normal file
View File

@@ -0,0 +1,816 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ANSI-C Compiler
3 ; Version 3.8.0 #10562 (Linux)
4 ;--------------------------------------------------------
5 .module font
6 .optsdcc -mz80
7
8 ;--------------------------------------------------------
9 ; Public variables in this module
10 ;--------------------------------------------------------
11 .globl _font
12 ;--------------------------------------------------------
13 ; special function registers
14 ;--------------------------------------------------------
15 ;--------------------------------------------------------
16 ; ram data
17 ;--------------------------------------------------------
18 .area _DATA
19 ;--------------------------------------------------------
20 ; ram data
21 ;--------------------------------------------------------
22 .area _INITIALIZED
0000 23 _font::
0000 24 .ds 768
25 ;--------------------------------------------------------
26 ; absolute external ram data
27 ;--------------------------------------------------------
28 .area _DABS (ABS)
29 ;--------------------------------------------------------
30 ; global & static initialisations
31 ;--------------------------------------------------------
32 .area _HOME
33 .area _GSINIT
34 .area _GSFINAL
35 .area _GSINIT
36 ;--------------------------------------------------------
37 ; Home
38 ;--------------------------------------------------------
39 .area _HOME
40 .area _HOME
41 ;--------------------------------------------------------
42 ; code
43 ;--------------------------------------------------------
44 .area _CODE
45 .area _CODE
46 .area _INITIALIZER
0000 47 __xinit__font:
0000 00 48 .db #0x00 ; 0
0001 00 49 .db #0x00 ; 0
0002 00 50 .db #0x00 ; 0
0003 00 51 .db #0x00 ; 0
0004 00 52 .db #0x00 ; 0
0005 00 53 .db #0x00 ; 0
0006 00 54 .db #0x00 ; 0
0007 00 55 .db #0x00 ; 0
0008 30 56 .db #0x30 ; 48 '0'
0009 78 57 .db #0x78 ; 120 'x'
000A 78 58 .db #0x78 ; 120 'x'
000B 78 59 .db #0x78 ; 120 'x'
000C 30 60 .db #0x30 ; 48 '0'
000D 00 61 .db #0x00 ; 0
000E 30 62 .db #0x30 ; 48 '0'
000F 00 63 .db #0x00 ; 0
0010 CC 64 .db #0xcc ; 204
0011 66 65 .db #0x66 ; 102 'f'
0012 33 66 .db #0x33 ; 51 '3'
0013 00 67 .db #0x00 ; 0
0014 00 68 .db #0x00 ; 0
0015 00 69 .db #0x00 ; 0
0016 00 70 .db #0x00 ; 0
0017 00 71 .db #0x00 ; 0
0018 00 72 .db #0x00 ; 0
0019 36 73 .db #0x36 ; 54 '6'
001A 7F 74 .db #0x7f ; 127
001B 36 75 .db #0x36 ; 54 '6'
001C 36 76 .db #0x36 ; 54 '6'
001D 7F 77 .db #0x7f ; 127
001E 36 78 .db #0x36 ; 54 '6'
001F 00 79 .db #0x00 ; 0
0020 7C 80 .db #0x7c ; 124
0021 D6 81 .db #0xd6 ; 214
0022 D0 82 .db #0xd0 ; 208
0023 7C 83 .db #0x7c ; 124
0024 16 84 .db #0x16 ; 22
0025 D6 85 .db #0xd6 ; 214
0026 7C 86 .db #0x7c ; 124
0027 10 87 .db #0x10 ; 16
0028 E3 88 .db #0xe3 ; 227
0029 A6 89 .db #0xa6 ; 166
002A EC 90 .db #0xec ; 236
002B 18 91 .db #0x18 ; 24
002C 37 92 .db #0x37 ; 55 '7'
002D 65 93 .db #0x65 ; 101 'e'
002E C7 94 .db #0xc7 ; 199
002F 00 95 .db #0x00 ; 0
0030 38 96 .db #0x38 ; 56 '8'
0031 4C 97 .db #0x4c ; 76 'L'
0032 38 98 .db #0x38 ; 56 '8'
0033 45 99 .db #0x45 ; 69 'E'
0034 C6 100 .db #0xc6 ; 198
0035 CE 101 .db #0xce ; 206
0036 7A 102 .db #0x7a ; 122 'z'
0037 01 103 .db #0x01 ; 1
0038 06 104 .db #0x06 ; 6
0039 0C 105 .db #0x0c ; 12
003A 18 106 .db #0x18 ; 24
003B 00 107 .db #0x00 ; 0
003C 00 108 .db #0x00 ; 0
003D 00 109 .db #0x00 ; 0
003E 00 110 .db #0x00 ; 0
003F 00 111 .db #0x00 ; 0
0040 0C 112 .db #0x0c ; 12
0041 18 113 .db #0x18 ; 24
0042 18 114 .db #0x18 ; 24
0043 18 115 .db #0x18 ; 24
0044 18 116 .db #0x18 ; 24
0045 18 117 .db #0x18 ; 24
0046 18 118 .db #0x18 ; 24
0047 0C 119 .db #0x0c ; 12
0048 60 120 .db #0x60 ; 96
0049 30 121 .db #0x30 ; 48 '0'
004A 30 122 .db #0x30 ; 48 '0'
004B 30 123 .db #0x30 ; 48 '0'
004C 30 124 .db #0x30 ; 48 '0'
004D 30 125 .db #0x30 ; 48 '0'
004E 30 126 .db #0x30 ; 48 '0'
004F 60 127 .db #0x60 ; 96
0050 10 128 .db #0x10 ; 16
0051 54 129 .db #0x54 ; 84 'T'
0052 38 130 .db #0x38 ; 56 '8'
0053 FE 131 .db #0xfe ; 254
0054 38 132 .db #0x38 ; 56 '8'
0055 54 133 .db #0x54 ; 84 'T'
0056 10 134 .db #0x10 ; 16
0057 00 135 .db #0x00 ; 0
0058 00 136 .db #0x00 ; 0
0059 18 137 .db #0x18 ; 24
005A 18 138 .db #0x18 ; 24
005B 7E 139 .db #0x7e ; 126
005C 18 140 .db #0x18 ; 24
005D 18 141 .db #0x18 ; 24
005E 00 142 .db #0x00 ; 0
005F 00 143 .db #0x00 ; 0
0060 00 144 .db #0x00 ; 0
0061 00 145 .db #0x00 ; 0
0062 00 146 .db #0x00 ; 0
0063 00 147 .db #0x00 ; 0
0064 00 148 .db #0x00 ; 0
0065 00 149 .db #0x00 ; 0
0066 18 150 .db #0x18 ; 24
0067 30 151 .db #0x30 ; 48 '0'
0068 00 152 .db #0x00 ; 0
0069 00 153 .db #0x00 ; 0
006A 00 154 .db #0x00 ; 0
006B 7E 155 .db #0x7e ; 126
006C 00 156 .db #0x00 ; 0
006D 00 157 .db #0x00 ; 0
006E 00 158 .db #0x00 ; 0
006F 00 159 .db #0x00 ; 0
0070 00 160 .db #0x00 ; 0
0071 00 161 .db #0x00 ; 0
0072 00 162 .db #0x00 ; 0
0073 00 163 .db #0x00 ; 0
0074 00 164 .db #0x00 ; 0
0075 00 165 .db #0x00 ; 0
0076 30 166 .db #0x30 ; 48 '0'
0077 00 167 .db #0x00 ; 0
0078 00 168 .db #0x00 ; 0
0079 03 169 .db #0x03 ; 3
007A 06 170 .db #0x06 ; 6
007B 0C 171 .db #0x0c ; 12
007C 18 172 .db #0x18 ; 24
007D 30 173 .db #0x30 ; 48 '0'
007E 60 174 .db #0x60 ; 96
007F 00 175 .db #0x00 ; 0
0080 7C 176 .db #0x7c ; 124
0081 CE 177 .db #0xce ; 206
0082 DE 178 .db #0xde ; 222
0083 FE 179 .db #0xfe ; 254
0084 EE 180 .db #0xee ; 238
0085 CE 181 .db #0xce ; 206
0086 7C 182 .db #0x7c ; 124
0087 00 183 .db #0x00 ; 0
0088 1C 184 .db #0x1c ; 28
0089 3C 185 .db #0x3c ; 60
008A 1C 186 .db #0x1c ; 28
008B 1C 187 .db #0x1c ; 28
008C 1C 188 .db #0x1c ; 28
008D 1C 189 .db #0x1c ; 28
008E 1C 190 .db #0x1c ; 28
008F 00 191 .db #0x00 ; 0
0090 7C 192 .db #0x7c ; 124
0091 CE 193 .db #0xce ; 206
0092 0E 194 .db #0x0e ; 14
0093 1C 195 .db #0x1c ; 28
0094 38 196 .db #0x38 ; 56 '8'
0095 70 197 .db #0x70 ; 112 'p'
0096 FE 198 .db #0xfe ; 254
0097 00 199 .db #0x00 ; 0
0098 7C 200 .db #0x7c ; 124
0099 CE 201 .db #0xce ; 206
009A 0E 202 .db #0x0e ; 14
009B 3C 203 .db #0x3c ; 60
009C 0E 204 .db #0x0e ; 14
009D CE 205 .db #0xce ; 206
009E 7C 206 .db #0x7c ; 124
009F 00 207 .db #0x00 ; 0
00A0 CE 208 .db #0xce ; 206
00A1 CE 209 .db #0xce ; 206
00A2 CE 210 .db #0xce ; 206
00A3 CE 211 .db #0xce ; 206
00A4 FE 212 .db #0xfe ; 254
00A5 0E 213 .db #0x0e ; 14
00A6 0E 214 .db #0x0e ; 14
00A7 00 215 .db #0x00 ; 0
00A8 FE 216 .db #0xfe ; 254
00A9 E0 217 .db #0xe0 ; 224
00AA E0 218 .db #0xe0 ; 224
00AB FC 219 .db #0xfc ; 252
00AC 0E 220 .db #0x0e ; 14
00AD 0E 221 .db #0x0e ; 14
00AE FC 222 .db #0xfc ; 252
00AF 00 223 .db #0x00 ; 0
00B0 7C 224 .db #0x7c ; 124
00B1 E6 225 .db #0xe6 ; 230
00B2 E0 226 .db #0xe0 ; 224
00B3 FC 227 .db #0xfc ; 252
00B4 E6 228 .db #0xe6 ; 230
00B5 E6 229 .db #0xe6 ; 230
00B6 7C 230 .db #0x7c ; 124
00B7 00 231 .db #0x00 ; 0
00B8 FE 232 .db #0xfe ; 254
00B9 06 233 .db #0x06 ; 6
00BA 0E 234 .db #0x0e ; 14
00BB 1C 235 .db #0x1c ; 28
00BC 38 236 .db #0x38 ; 56 '8'
00BD 38 237 .db #0x38 ; 56 '8'
00BE 38 238 .db #0x38 ; 56 '8'
00BF 00 239 .db #0x00 ; 0
00C0 7C 240 .db #0x7c ; 124
00C1 E6 241 .db #0xe6 ; 230
00C2 E6 242 .db #0xe6 ; 230
00C3 7C 243 .db #0x7c ; 124
00C4 E6 244 .db #0xe6 ; 230
00C5 E6 245 .db #0xe6 ; 230
00C6 7C 246 .db #0x7c ; 124
00C7 00 247 .db #0x00 ; 0
00C8 7C 248 .db #0x7c ; 124
00C9 CE 249 .db #0xce ; 206
00CA CE 250 .db #0xce ; 206
00CB 7E 251 .db #0x7e ; 126
00CC 0E 252 .db #0x0e ; 14
00CD 0E 253 .db #0x0e ; 14
00CE FC 254 .db #0xfc ; 252
00CF 00 255 .db #0x00 ; 0
00D0 00 256 .db #0x00 ; 0
00D1 30 257 .db #0x30 ; 48 '0'
00D2 00 258 .db #0x00 ; 0
00D3 00 259 .db #0x00 ; 0
00D4 00 260 .db #0x00 ; 0
00D5 30 261 .db #0x30 ; 48 '0'
00D6 00 262 .db #0x00 ; 0
00D7 00 263 .db #0x00 ; 0
00D8 00 264 .db #0x00 ; 0
00D9 30 265 .db #0x30 ; 48 '0'
00DA 00 266 .db #0x00 ; 0
00DB 00 267 .db #0x00 ; 0
00DC 00 268 .db #0x00 ; 0
00DD 30 269 .db #0x30 ; 48 '0'
00DE 60 270 .db #0x60 ; 96
00DF 00 271 .db #0x00 ; 0
00E0 00 272 .db #0x00 ; 0
00E1 18 273 .db #0x18 ; 24
00E2 30 274 .db #0x30 ; 48 '0'
00E3 60 275 .db #0x60 ; 96
00E4 30 276 .db #0x30 ; 48 '0'
00E5 18 277 .db #0x18 ; 24
00E6 00 278 .db #0x00 ; 0
00E7 00 279 .db #0x00 ; 0
00E8 00 280 .db #0x00 ; 0
00E9 00 281 .db #0x00 ; 0
00EA 7E 282 .db #0x7e ; 126
00EB 00 283 .db #0x00 ; 0
00EC 7E 284 .db #0x7e ; 126
00ED 00 285 .db #0x00 ; 0
00EE 00 286 .db #0x00 ; 0
00EF 00 287 .db #0x00 ; 0
00F0 00 288 .db #0x00 ; 0
00F1 30 289 .db #0x30 ; 48 '0'
00F2 18 290 .db #0x18 ; 24
00F3 0C 291 .db #0x0c ; 12
00F4 18 292 .db #0x18 ; 24
00F5 30 293 .db #0x30 ; 48 '0'
00F6 00 294 .db #0x00 ; 0
00F7 00 295 .db #0x00 ; 0
00F8 7C 296 .db #0x7c ; 124
00F9 C6 297 .db #0xc6 ; 198
00FA 0E 298 .db #0x0e ; 14
00FB 1C 299 .db #0x1c ; 28
00FC 38 300 .db #0x38 ; 56 '8'
00FD 00 301 .db #0x00 ; 0
00FE 38 302 .db #0x38 ; 56 '8'
00FF 00 303 .db #0x00 ; 0
0100 7C 304 .db #0x7c ; 124
0101 C6 305 .db #0xc6 ; 198
0102 DE 306 .db #0xde ; 222
0103 DE 307 .db #0xde ; 222
0104 DC 308 .db #0xdc ; 220
0105 C0 309 .db #0xc0 ; 192
0106 7C 310 .db #0x7c ; 124
0107 00 311 .db #0x00 ; 0
0108 7C 312 .db #0x7c ; 124
0109 E6 313 .db #0xe6 ; 230
010A E6 314 .db #0xe6 ; 230
010B E6 315 .db #0xe6 ; 230
010C FE 316 .db #0xfe ; 254
010D E6 317 .db #0xe6 ; 230
010E E6 318 .db #0xe6 ; 230
010F 00 319 .db #0x00 ; 0
0110 FC 320 .db #0xfc ; 252
0111 E6 321 .db #0xe6 ; 230
0112 E6 322 .db #0xe6 ; 230
0113 FC 323 .db #0xfc ; 252
0114 E6 324 .db #0xe6 ; 230
0115 E6 325 .db #0xe6 ; 230
0116 FC 326 .db #0xfc ; 252
0117 00 327 .db #0x00 ; 0
0118 7C 328 .db #0x7c ; 124
0119 E6 329 .db #0xe6 ; 230
011A E0 330 .db #0xe0 ; 224
011B E0 331 .db #0xe0 ; 224
011C E6 332 .db #0xe6 ; 230
011D E6 333 .db #0xe6 ; 230
011E 7C 334 .db #0x7c ; 124
011F 00 335 .db #0x00 ; 0
0120 FC 336 .db #0xfc ; 252
0121 E6 337 .db #0xe6 ; 230
0122 E6 338 .db #0xe6 ; 230
0123 E6 339 .db #0xe6 ; 230
0124 E6 340 .db #0xe6 ; 230
0125 E6 341 .db #0xe6 ; 230
0126 FC 342 .db #0xfc ; 252
0127 00 343 .db #0x00 ; 0
0128 FE 344 .db #0xfe ; 254
0129 E0 345 .db #0xe0 ; 224
012A E0 346 .db #0xe0 ; 224
012B FE 347 .db #0xfe ; 254
012C E0 348 .db #0xe0 ; 224
012D E0 349 .db #0xe0 ; 224
012E FE 350 .db #0xfe ; 254
012F 00 351 .db #0x00 ; 0
0130 FE 352 .db #0xfe ; 254
0131 E0 353 .db #0xe0 ; 224
0132 E0 354 .db #0xe0 ; 224
0133 FE 355 .db #0xfe ; 254
0134 E0 356 .db #0xe0 ; 224
0135 E0 357 .db #0xe0 ; 224
0136 E0 358 .db #0xe0 ; 224
0137 00 359 .db #0x00 ; 0
0138 7C 360 .db #0x7c ; 124
0139 E6 361 .db #0xe6 ; 230
013A E0 362 .db #0xe0 ; 224
013B EE 363 .db #0xee ; 238
013C E6 364 .db #0xe6 ; 230
013D E6 365 .db #0xe6 ; 230
013E 7C 366 .db #0x7c ; 124
013F 00 367 .db #0x00 ; 0
0140 E6 368 .db #0xe6 ; 230
0141 E6 369 .db #0xe6 ; 230
0142 E6 370 .db #0xe6 ; 230
0143 FE 371 .db #0xfe ; 254
0144 E6 372 .db #0xe6 ; 230
0145 E6 373 .db #0xe6 ; 230
0146 E6 374 .db #0xe6 ; 230
0147 00 375 .db #0x00 ; 0
0148 38 376 .db #0x38 ; 56 '8'
0149 38 377 .db #0x38 ; 56 '8'
014A 38 378 .db #0x38 ; 56 '8'
014B 38 379 .db #0x38 ; 56 '8'
014C 38 380 .db #0x38 ; 56 '8'
014D 38 381 .db #0x38 ; 56 '8'
014E 38 382 .db #0x38 ; 56 '8'
014F 00 383 .db #0x00 ; 0
0150 0E 384 .db #0x0e ; 14
0151 0E 385 .db #0x0e ; 14
0152 0E 386 .db #0x0e ; 14
0153 0E 387 .db #0x0e ; 14
0154 CE 388 .db #0xce ; 206
0155 CE 389 .db #0xce ; 206
0156 7C 390 .db #0x7c ; 124
0157 00 391 .db #0x00 ; 0
0158 E6 392 .db #0xe6 ; 230
0159 EC 393 .db #0xec ; 236
015A F8 394 .db #0xf8 ; 248
015B F0 395 .db #0xf0 ; 240
015C F8 396 .db #0xf8 ; 248
015D EC 397 .db #0xec ; 236
015E E6 398 .db #0xe6 ; 230
015F 00 399 .db #0x00 ; 0
0160 E0 400 .db #0xe0 ; 224
0161 E0 401 .db #0xe0 ; 224
0162 E0 402 .db #0xe0 ; 224
0163 E0 403 .db #0xe0 ; 224
0164 E0 404 .db #0xe0 ; 224
0165 E0 405 .db #0xe0 ; 224
0166 FE 406 .db #0xfe ; 254
0167 00 407 .db #0x00 ; 0
0168 C6 408 .db #0xc6 ; 198
0169 EE 409 .db #0xee ; 238
016A FE 410 .db #0xfe ; 254
016B D6 411 .db #0xd6 ; 214
016C C6 412 .db #0xc6 ; 198
016D C6 413 .db #0xc6 ; 198
016E C6 414 .db #0xc6 ; 198
016F 00 415 .db #0x00 ; 0
0170 C6 416 .db #0xc6 ; 198
0171 E6 417 .db #0xe6 ; 230
0172 F6 418 .db #0xf6 ; 246
0173 FE 419 .db #0xfe ; 254
0174 EE 420 .db #0xee ; 238
0175 E6 421 .db #0xe6 ; 230
0176 E6 422 .db #0xe6 ; 230
0177 00 423 .db #0x00 ; 0
0178 7C 424 .db #0x7c ; 124
0179 E6 425 .db #0xe6 ; 230
017A E6 426 .db #0xe6 ; 230
017B E6 427 .db #0xe6 ; 230
017C E6 428 .db #0xe6 ; 230
017D E6 429 .db #0xe6 ; 230
017E 7C 430 .db #0x7c ; 124
017F 00 431 .db #0x00 ; 0
0180 FC 432 .db #0xfc ; 252
0181 E6 433 .db #0xe6 ; 230
0182 E6 434 .db #0xe6 ; 230
0183 FC 435 .db #0xfc ; 252
0184 E0 436 .db #0xe0 ; 224
0185 E0 437 .db #0xe0 ; 224
0186 E0 438 .db #0xe0 ; 224
0187 00 439 .db #0x00 ; 0
0188 7C 440 .db #0x7c ; 124
0189 E6 441 .db #0xe6 ; 230
018A E6 442 .db #0xe6 ; 230
018B E6 443 .db #0xe6 ; 230
018C E6 444 .db #0xe6 ; 230
018D EA 445 .db #0xea ; 234
018E 74 446 .db #0x74 ; 116 't'
018F 02 447 .db #0x02 ; 2
0190 FC 448 .db #0xfc ; 252
0191 E6 449 .db #0xe6 ; 230
0192 E6 450 .db #0xe6 ; 230
0193 FC 451 .db #0xfc ; 252
0194 E6 452 .db #0xe6 ; 230
0195 E6 453 .db #0xe6 ; 230
0196 E6 454 .db #0xe6 ; 230
0197 00 455 .db #0x00 ; 0
0198 7C 456 .db #0x7c ; 124
0199 E6 457 .db #0xe6 ; 230
019A E0 458 .db #0xe0 ; 224
019B 7C 459 .db #0x7c ; 124
019C 0E 460 .db #0x0e ; 14
019D CE 461 .db #0xce ; 206
019E 7C 462 .db #0x7c ; 124
019F 00 463 .db #0x00 ; 0
01A0 FE 464 .db #0xfe ; 254
01A1 38 465 .db #0x38 ; 56 '8'
01A2 38 466 .db #0x38 ; 56 '8'
01A3 38 467 .db #0x38 ; 56 '8'
01A4 38 468 .db #0x38 ; 56 '8'
01A5 38 469 .db #0x38 ; 56 '8'
01A6 38 470 .db #0x38 ; 56 '8'
01A7 00 471 .db #0x00 ; 0
01A8 E6 472 .db #0xe6 ; 230
01A9 E6 473 .db #0xe6 ; 230
01AA E6 474 .db #0xe6 ; 230
01AB E6 475 .db #0xe6 ; 230
01AC E6 476 .db #0xe6 ; 230
01AD E6 477 .db #0xe6 ; 230
01AE 7C 478 .db #0x7c ; 124
01AF 00 479 .db #0x00 ; 0
01B0 E6 480 .db #0xe6 ; 230
01B1 E6 481 .db #0xe6 ; 230
01B2 E6 482 .db #0xe6 ; 230
01B3 E6 483 .db #0xe6 ; 230
01B4 E6 484 .db #0xe6 ; 230
01B5 7C 485 .db #0x7c ; 124
01B6 38 486 .db #0x38 ; 56 '8'
01B7 00 487 .db #0x00 ; 0
01B8 C6 488 .db #0xc6 ; 198
01B9 C6 489 .db #0xc6 ; 198
01BA C6 490 .db #0xc6 ; 198
01BB D6 491 .db #0xd6 ; 214
01BC D6 492 .db #0xd6 ; 214
01BD FE 493 .db #0xfe ; 254
01BE FC 494 .db #0xfc ; 252
01BF 00 495 .db #0x00 ; 0
01C0 E3 496 .db #0xe3 ; 227
01C1 76 497 .db #0x76 ; 118 'v'
01C2 3C 498 .db #0x3c ; 60
01C3 18 499 .db #0x18 ; 24
01C4 3C 500 .db #0x3c ; 60
01C5 6E 501 .db #0x6e ; 110 'n'
01C6 C7 502 .db #0xc7 ; 199
01C7 00 503 .db #0x00 ; 0
01C8 E6 504 .db #0xe6 ; 230
01C9 E6 505 .db #0xe6 ; 230
01CA 7C 506 .db #0x7c ; 124
01CB 38 507 .db #0x38 ; 56 '8'
01CC 38 508 .db #0x38 ; 56 '8'
01CD 38 509 .db #0x38 ; 56 '8'
01CE 38 510 .db #0x38 ; 56 '8'
01CF 00 511 .db #0x00 ; 0
01D0 FE 512 .db #0xfe ; 254
01D1 0E 513 .db #0x0e ; 14
01D2 1C 514 .db #0x1c ; 28
01D3 38 515 .db #0x38 ; 56 '8'
01D4 70 516 .db #0x70 ; 112 'p'
01D5 E0 517 .db #0xe0 ; 224
01D6 FE 518 .db #0xfe ; 254
01D7 00 519 .db #0x00 ; 0
01D8 1C 520 .db #0x1c ; 28
01D9 18 521 .db #0x18 ; 24
01DA 18 522 .db #0x18 ; 24
01DB 18 523 .db #0x18 ; 24
01DC 18 524 .db #0x18 ; 24
01DD 18 525 .db #0x18 ; 24
01DE 18 526 .db #0x18 ; 24
01DF 1C 527 .db #0x1c ; 28
01E0 00 528 .db #0x00 ; 0
01E1 60 529 .db #0x60 ; 96
01E2 30 530 .db #0x30 ; 48 '0'
01E3 18 531 .db #0x18 ; 24
01E4 0C 532 .db #0x0c ; 12
01E5 06 533 .db #0x06 ; 6
01E6 03 534 .db #0x03 ; 3
01E7 00 535 .db #0x00 ; 0
01E8 70 536 .db #0x70 ; 112 'p'
01E9 30 537 .db #0x30 ; 48 '0'
01EA 30 538 .db #0x30 ; 48 '0'
01EB 30 539 .db #0x30 ; 48 '0'
01EC 30 540 .db #0x30 ; 48 '0'
01ED 30 541 .db #0x30 ; 48 '0'
01EE 30 542 .db #0x30 ; 48 '0'
01EF 70 543 .db #0x70 ; 112 'p'
01F0 18 544 .db #0x18 ; 24
01F1 3C 545 .db #0x3c ; 60
01F2 66 546 .db #0x66 ; 102 'f'
01F3 C3 547 .db #0xc3 ; 195
01F4 00 548 .db #0x00 ; 0
01F5 00 549 .db #0x00 ; 0
01F6 00 550 .db #0x00 ; 0
01F7 00 551 .db #0x00 ; 0
01F8 00 552 .db #0x00 ; 0
01F9 00 553 .db #0x00 ; 0
01FA 00 554 .db #0x00 ; 0
01FB 00 555 .db #0x00 ; 0
01FC 00 556 .db #0x00 ; 0
01FD 00 557 .db #0x00 ; 0
01FE 00 558 .db #0x00 ; 0
01FF FF 559 .db #0xff ; 255
0200 30 560 .db #0x30 ; 48 '0'
0201 18 561 .db #0x18 ; 24
0202 0C 562 .db #0x0c ; 12
0203 00 563 .db #0x00 ; 0
0204 00 564 .db #0x00 ; 0
0205 00 565 .db #0x00 ; 0
0206 00 566 .db #0x00 ; 0
0207 00 567 .db #0x00 ; 0
0208 00 568 .db #0x00 ; 0
0209 00 569 .db #0x00 ; 0
020A 7C 570 .db #0x7c ; 124
020B 0E 571 .db #0x0e ; 14
020C 7E 572 .db #0x7e ; 126
020D CE 573 .db #0xce ; 206
020E 7E 574 .db #0x7e ; 126
020F 00 575 .db #0x00 ; 0
0210 C0 576 .db #0xc0 ; 192
0211 C0 577 .db #0xc0 ; 192
0212 FC 578 .db #0xfc ; 252
0213 E6 579 .db #0xe6 ; 230
0214 E6 580 .db #0xe6 ; 230
0215 E6 581 .db #0xe6 ; 230
0216 FC 582 .db #0xfc ; 252
0217 00 583 .db #0x00 ; 0
0218 00 584 .db #0x00 ; 0
0219 00 585 .db #0x00 ; 0
021A 7C 586 .db #0x7c ; 124
021B E6 587 .db #0xe6 ; 230
021C E0 588 .db #0xe0 ; 224
021D E6 589 .db #0xe6 ; 230
021E 7C 590 .db #0x7c ; 124
021F 00 591 .db #0x00 ; 0
0220 06 592 .db #0x06 ; 6
0221 06 593 .db #0x06 ; 6
0222 7E 594 .db #0x7e ; 126
0223 CE 595 .db #0xce ; 206
0224 CE 596 .db #0xce ; 206
0225 CE 597 .db #0xce ; 206
0226 7E 598 .db #0x7e ; 126
0227 00 599 .db #0x00 ; 0
0228 00 600 .db #0x00 ; 0
0229 00 601 .db #0x00 ; 0
022A 7C 602 .db #0x7c ; 124
022B E6 603 .db #0xe6 ; 230
022C FE 604 .db #0xfe ; 254
022D E0 605 .db #0xe0 ; 224
022E 7E 606 .db #0x7e ; 126
022F 00 607 .db #0x00 ; 0
0230 3C 608 .db #0x3c ; 60
0231 70 609 .db #0x70 ; 112 'p'
0232 70 610 .db #0x70 ; 112 'p'
0233 FC 611 .db #0xfc ; 252
0234 70 612 .db #0x70 ; 112 'p'
0235 70 613 .db #0x70 ; 112 'p'
0236 70 614 .db #0x70 ; 112 'p'
0237 00 615 .db #0x00 ; 0
0238 00 616 .db #0x00 ; 0
0239 00 617 .db #0x00 ; 0
023A 7C 618 .db #0x7c ; 124
023B CE 619 .db #0xce ; 206
023C CE 620 .db #0xce ; 206
023D 7E 621 .db #0x7e ; 126
023E 0E 622 .db #0x0e ; 14
023F 7C 623 .db #0x7c ; 124
0240 C0 624 .db #0xc0 ; 192
0241 C0 625 .db #0xc0 ; 192
0242 FC 626 .db #0xfc ; 252
0243 E6 627 .db #0xe6 ; 230
0244 E6 628 .db #0xe6 ; 230
0245 E6 629 .db #0xe6 ; 230
0246 E6 630 .db #0xe6 ; 230
0247 00 631 .db #0x00 ; 0
0248 18 632 .db #0x18 ; 24
0249 00 633 .db #0x00 ; 0
024A 18 634 .db #0x18 ; 24
024B 38 635 .db #0x38 ; 56 '8'
024C 38 636 .db #0x38 ; 56 '8'
024D 38 637 .db #0x38 ; 56 '8'
024E 38 638 .db #0x38 ; 56 '8'
024F 00 639 .db #0x00 ; 0
0250 0C 640 .db #0x0c ; 12
0251 00 641 .db #0x00 ; 0
0252 0C 642 .db #0x0c ; 12
0253 1C 643 .db #0x1c ; 28
0254 1C 644 .db #0x1c ; 28
0255 1C 645 .db #0x1c ; 28
0256 1C 646 .db #0x1c ; 28
0257 F8 647 .db #0xf8 ; 248
0258 C0 648 .db #0xc0 ; 192
0259 C0 649 .db #0xc0 ; 192
025A CC 650 .db #0xcc ; 204
025B D8 651 .db #0xd8 ; 216
025C F0 652 .db #0xf0 ; 240
025D D8 653 .db #0xd8 ; 216
025E CC 654 .db #0xcc ; 204
025F 00 655 .db #0x00 ; 0
0260 18 656 .db #0x18 ; 24
0261 18 657 .db #0x18 ; 24
0262 38 658 .db #0x38 ; 56 '8'
0263 38 659 .db #0x38 ; 56 '8'
0264 38 660 .db #0x38 ; 56 '8'
0265 38 661 .db #0x38 ; 56 '8'
0266 38 662 .db #0x38 ; 56 '8'
0267 00 663 .db #0x00 ; 0
0268 00 664 .db #0x00 ; 0
0269 00 665 .db #0x00 ; 0
026A FC 666 .db #0xfc ; 252
026B D6 667 .db #0xd6 ; 214
026C D6 668 .db #0xd6 ; 214
026D D6 669 .db #0xd6 ; 214
026E D6 670 .db #0xd6 ; 214
026F 00 671 .db #0x00 ; 0
0270 00 672 .db #0x00 ; 0
0271 00 673 .db #0x00 ; 0
0272 FC 674 .db #0xfc ; 252
0273 E6 675 .db #0xe6 ; 230
0274 E6 676 .db #0xe6 ; 230
0275 E6 677 .db #0xe6 ; 230
0276 E6 678 .db #0xe6 ; 230
0277 00 679 .db #0x00 ; 0
0278 00 680 .db #0x00 ; 0
0279 00 681 .db #0x00 ; 0
027A 7C 682 .db #0x7c ; 124
027B E6 683 .db #0xe6 ; 230
027C E6 684 .db #0xe6 ; 230
027D E6 685 .db #0xe6 ; 230
027E 7C 686 .db #0x7c ; 124
027F 00 687 .db #0x00 ; 0
0280 00 688 .db #0x00 ; 0
0281 00 689 .db #0x00 ; 0
0282 FC 690 .db #0xfc ; 252
0283 E6 691 .db #0xe6 ; 230
0284 E6 692 .db #0xe6 ; 230
0285 FC 693 .db #0xfc ; 252
0286 E0 694 .db #0xe0 ; 224
0287 E0 695 .db #0xe0 ; 224
0288 00 696 .db #0x00 ; 0
0289 00 697 .db #0x00 ; 0
028A 7E 698 .db #0x7e ; 126
028B CE 699 .db #0xce ; 206
028C CE 700 .db #0xce ; 206
028D 7E 701 .db #0x7e ; 126
028E 0E 702 .db #0x0e ; 14
028F 0E 703 .db #0x0e ; 14
0290 00 704 .db #0x00 ; 0
0291 00 705 .db #0x00 ; 0
0292 FC 706 .db #0xfc ; 252
0293 E6 707 .db #0xe6 ; 230
0294 E0 708 .db #0xe0 ; 224
0295 E0 709 .db #0xe0 ; 224
0296 E0 710 .db #0xe0 ; 224
0297 00 711 .db #0x00 ; 0
0298 00 712 .db #0x00 ; 0
0299 00 713 .db #0x00 ; 0
029A 7E 714 .db #0x7e ; 126
029B E0 715 .db #0xe0 ; 224
029C 7C 716 .db #0x7c ; 124
029D 0E 717 .db #0x0e ; 14
029E FC 718 .db #0xfc ; 252
029F 00 719 .db #0x00 ; 0
02A0 18 720 .db #0x18 ; 24
02A1 18 721 .db #0x18 ; 24
02A2 7E 722 .db #0x7e ; 126
02A3 38 723 .db #0x38 ; 56 '8'
02A4 38 724 .db #0x38 ; 56 '8'
02A5 38 725 .db #0x38 ; 56 '8'
02A6 38 726 .db #0x38 ; 56 '8'
02A7 00 727 .db #0x00 ; 0
02A8 00 728 .db #0x00 ; 0
02A9 00 729 .db #0x00 ; 0
02AA E6 730 .db #0xe6 ; 230
02AB E6 731 .db #0xe6 ; 230
02AC E6 732 .db #0xe6 ; 230
02AD E6 733 .db #0xe6 ; 230
02AE 7E 734 .db #0x7e ; 126
02AF 00 735 .db #0x00 ; 0
02B0 00 736 .db #0x00 ; 0
02B1 00 737 .db #0x00 ; 0
02B2 E6 738 .db #0xe6 ; 230
02B3 E6 739 .db #0xe6 ; 230
02B4 E6 740 .db #0xe6 ; 230
02B5 6C 741 .db #0x6c ; 108 'l'
02B6 38 742 .db #0x38 ; 56 '8'
02B7 00 743 .db #0x00 ; 0
02B8 00 744 .db #0x00 ; 0
02B9 00 745 .db #0x00 ; 0
02BA D6 746 .db #0xd6 ; 214
02BB D6 747 .db #0xd6 ; 214
02BC D6 748 .db #0xd6 ; 214
02BD D6 749 .db #0xd6 ; 214
02BE FC 750 .db #0xfc ; 252
02BF 00 751 .db #0x00 ; 0
02C0 00 752 .db #0x00 ; 0
02C1 00 753 .db #0x00 ; 0
02C2 E6 754 .db #0xe6 ; 230
02C3 7C 755 .db #0x7c ; 124
02C4 38 756 .db #0x38 ; 56 '8'
02C5 7C 757 .db #0x7c ; 124
02C6 CE 758 .db #0xce ; 206
02C7 00 759 .db #0x00 ; 0
02C8 00 760 .db #0x00 ; 0
02C9 00 761 .db #0x00 ; 0
02CA CE 762 .db #0xce ; 206
02CB CE 763 .db #0xce ; 206
02CC CE 764 .db #0xce ; 206
02CD 7E 765 .db #0x7e ; 126
02CE 0E 766 .db #0x0e ; 14
02CF FC 767 .db #0xfc ; 252
02D0 00 768 .db #0x00 ; 0
02D1 00 769 .db #0x00 ; 0
02D2 FE 770 .db #0xfe ; 254
02D3 1C 771 .db #0x1c ; 28
02D4 38 772 .db #0x38 ; 56 '8'
02D5 70 773 .db #0x70 ; 112 'p'
02D6 FE 774 .db #0xfe ; 254
02D7 00 775 .db #0x00 ; 0
02D8 0C 776 .db #0x0c ; 12
02D9 18 777 .db #0x18 ; 24
02DA 18 778 .db #0x18 ; 24
02DB 30 779 .db #0x30 ; 48 '0'
02DC 18 780 .db #0x18 ; 24
02DD 18 781 .db #0x18 ; 24
02DE 0C 782 .db #0x0c ; 12
02DF 00 783 .db #0x00 ; 0
02E0 18 784 .db #0x18 ; 24
02E1 18 785 .db #0x18 ; 24
02E2 18 786 .db #0x18 ; 24
02E3 18 787 .db #0x18 ; 24
02E4 18 788 .db #0x18 ; 24
02E5 18 789 .db #0x18 ; 24
02E6 18 790 .db #0x18 ; 24
02E7 18 791 .db #0x18 ; 24
02E8 60 792 .db #0x60 ; 96
02E9 30 793 .db #0x30 ; 48 '0'
02EA 30 794 .db #0x30 ; 48 '0'
02EB 18 795 .db #0x18 ; 24
02EC 30 796 .db #0x30 ; 48 '0'
02ED 30 797 .db #0x30 ; 48 '0'
02EE 60 798 .db #0x60 ; 96
02EF 00 799 .db #0x00 ; 0
02F0 70 800 .db #0x70 ; 112 'p'
02F1 DB 801 .db #0xdb ; 219
02F2 0E 802 .db #0x0e ; 14
02F3 00 803 .db #0x00 ; 0
02F4 00 804 .db #0x00 ; 0
02F5 00 805 .db #0x00 ; 0
02F6 00 806 .db #0x00 ; 0
02F7 00 807 .db #0x00 ; 0
02F8 00 808 .db #0x00 ; 0
02F9 00 809 .db #0x00 ; 0
02FA 10 810 .db #0x10 ; 16
02FB 28 811 .db #0x28 ; 40
02FC 44 812 .db #0x44 ; 68 'D'
02FD FE 813 .db #0xfe ; 254
02FE 00 814 .db #0x00 ; 0
02FF 00 815 .db #0x00 ; 0
816 .area _CABS (ABS)

27
src/font.sym Normal file
View File

@@ -0,0 +1,27 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 1.
Hexadecimal [16-Bits]
Symbol Table
.__.$$$. = 2710 L
.__.ABS. = 0000 G
.__.CPU. = 0000 L
.__.H$L. = 0000 L
7 __xinit__font 0000 R
2 _font 0000 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 2.
Hexadecimal [16-Bits]
Area Table
0 _CODE size 0 flags 0
1 _DATA size 0 flags 0
2 _INITIALIZED size 300 flags 0
3 _DABS size 0 flags 8
4 _HOME size 0 flags 0
5 _GSINIT size 0 flags 0
6 _GSFINAL size 0 flags 0
7 _INITIALIZER size 300 flags 0
8 _CABS size 0 flags 8

4
verilator/Makefile
View File

@@ -55,8 +55,8 @@ CC_OPT = -O
V_SRC = \
sim.v \
$(RTL)/soc.v \
$(RTL)/bram.v \
$(RTL)/vga.v \
$(RTL)/dpram.v \
$(RTL)/video.v \
../rtl/tv80/tv80_core.v \
../rtl/tv80/tv80_alu.v \
../rtl/tv80/tv80_mcode.v \

16
verilator/imgui.ini
View File

@@ -9,27 +9,27 @@ Size=520,600
Collapsed=0
[Window][Virtual Dev Board v1.0]
Pos=580,10
Pos=150,89
Size=1000,1000
Collapsed=0
[Window][RAM Editor]
Pos=1411,643
Size=544,319
Pos=1048,137
Size=565,478
Collapsed=0
[Window][ROM Editor]
Pos=1396,251
Size=669,377
Pos=2,629
Size=547,377
Collapsed=0
[Window][VRAM Editor]
Pos=7,652
Pos=1064,618
Size=560,393
Collapsed=0
[Window][CPU Registers]
Pos=20,471
Size=269,174
Pos=738,825
Size=269,180
Collapsed=0

97
verilator/rom.hex
View File

@@ -1,97 +0,0 @@
C3 00 01 00 00 00 00 00 ED 4D 00 00
00 00 00 00 ED 4D 00 00 00 00 00 00
ED 4D 00 00 00 00 00 00 ED 4D 00 00
00 00 00 00 ED 4D 00 00 00 00 00 00
ED 4D 00 00 00 00 00 00 ED 4D 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 31 FF FF CD 76 04 CD 45
03 C3 04 02 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 3E 02 CF C9
3E 00 CF 76 18 FD DD E5 DD 21 00 00
DD 39 DD 4E 05 06 00 69 60 29 29 09
29 29 29 29 29 DD 5E 04 16 00 19 DD
7E 06 77 DD E1 C9 DD E5 DD 21 00 00
DD 39 21 F7 FF 39 F9 DD 7E 04 DD 96
06 30 04 3E 01 18 02 3E FF DD 77 F9
DD 7E 05 DD 96 07 30 04 3E 01 18 02
3E FF DD 77 FC DD 66 06 2E 00 DD 5E
04 16 00 7C 93 4F 7D 9A 47 C5 C5 CD
6A 04 F1 C1 DD 75 FA DD 66 07 2E 00
DD 5E 05 16 00 7C 93 5F 7D 9A 57 C5
D5 D5 CD 6A 04 F1 D1 C1 DD 75 F8 DD
7E FA DD 96 F8 30 1C C5 D5 CD 6A 04
F1 C1 DD 75 FA C5 CD 6A 04 F1 DD 75
F8 0E 00 DD 7E FC DD 77 FB 18 07 DD
4E F9 DD 36 FB 00 DD 5E FA CB 3B DD
36 F7 00 C5 D5 DD 66 08 DD 6E 05 E5
DD 7E 04 F5 33 CD 0A 02 F1 33 D1 C1
DD 66 FA 16 00 DD 6E F8 06 00 7C 95
67 7A 98 57 DD 73 FE DD 36 FF 00 7B
DD 86 F8 5F DD 6E 04 DD 7E 05 DD 77
FD DD 7E FE 94 DD 7E FF 9A E2 0E 03
EE 80 FA 28 03 7B DD 96 FA 5F 7D DD
86 F9 DD 77 04 DD 7E FD DD 86 FC DD
77 05 18 0D 09 DD 75 04 DD 7E FD DD
86 FB DD 77 05 DD 34 F7 DD 7E FA DD
96 F7 30 87 DD F9 DD E1 C9 0E 00 11
00 00 61 0C 43 C5 D5 E5 33 C5 33 21
00 9F E5 AF F5 33 CD 2E 02 F1 F1 33
D1 C1 13 7B D6 64 7A 17 3F 1F DE 80
38 DC 11 9F 00 61 0C 43 C5 D5 E5 33
3E 63 F5 33 C5 33 21 00 00 E5 CD 2E
02 F1 F1 33 D1 C1 1B CB 7A 28 E2 11
00 00 61 0C 43 C5 D5 E5 33 AF F5 33
C5 33 21 00 63 E5 CD 2E 02 F1 F1 33
D1 C1 13 7B D6 A0 7A 17 3F 1F DE 80
38 DC 11 00 00 61 0C 43 C5 D5 E5 33
C5 33 21 63 9F E5 AF F5 33 CD 2E 02
F1 F1 33 D1 C1 13 7B D6 64 7A 17 3F
1F DE 80 38 DC 11 63 00 61 0C 43 C5
D5 E5 33 C5 33 21 63 00 E5 3E 9F F5
33 CD 2E 02 F1 F1 33 D1 C1 1B CB 7A
28 E2 11 00 00 61 0C 43 C5 D5 E5 33
AF F5 33 C5 33 21 9F 63 E5 CD 2E 02
F1 F1 33 D1 C1 13 7B D6 A0 7A 17 3F
1F DE 80 38 DC 11 9F 00 61 0C 43 C5
D5 E5 33 3E 63 F5 33 C5 33 21 9F 00
E5 CD 2E 02 F1 F1 33 D1 C1 1B CB 7A
28 E2 11 63 00 61 0C 43 C5 D5 E5 33
C5 33 21 00 00 E5 3E 9F F5 33 CD 2E
02 F1 F1 33 D1 C1 1B CB 7A 28 E2 C3
47 03 E1 D1 D5 E5 AF 6F 67 ED 52 F0
EB C9 01 00 00 78 B1 28 08 11 00 80
21 76 04 ED B0 C9

23
verilator/sim.v
View File

@@ -7,11 +7,12 @@
`define USE_VGA
//`define USE_CGA
module top(VGA_R,VGA_B,VGA_G,VGA_HS,VGA_VS,VGA_HB,VGA_VB,reset,clk_sys,clk_vid,ioctl_download,ioctl_addr,ioctl_dout,ioctl_index,ioctl_wait,ioctl_wr);
module top(VGA_R,VGA_B,VGA_G,VGA_HS,VGA_VS,VGA_HB,VGA_VB,reset,clk_sys,clk_vid,inputs,ioctl_download,ioctl_addr,ioctl_dout,ioctl_index,ioctl_wait,ioctl_wr);
input clk_sys/*verilator public_flat*/;
input clk_vid/*verilator public_flat*/;
input reset/*verilator public_flat*/;
input [11:0] inputs/*verilator public_flat*/;
output [7:0] VGA_R/*verilator public_flat*/;
output [7:0] VGA_G/*verilator public_flat*/;
@@ -30,12 +31,19 @@ module top(VGA_R,VGA_B,VGA_G,VGA_HS,VGA_VS,VGA_HB,VGA_VB,reset,clk_sys,clk_vid,i
input [7:0] ioctl_index;
output reg ioctl_wait=1'b0;
wire btn_start = inputs[6];
wire btn_coin = inputs[8];
wire m_bomb = inputs[5];
wire m_fire = inputs[4];
wire m_right = inputs[0];
wire m_left = inputs[1];
wire m_down = inputs[2];
wire m_up = inputs[3];
wire VGA_DE;
soc soc(
.clk_sys(clk_sys), // wrong
.pixel_clock(clk_sys), // wrong
.clk_sys(clk_sys),
.clk_pix(clk_sys),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
@@ -43,9 +51,12 @@ soc soc(
.VGA_B(VGA_B),
.VGA_HB(VGA_HB),
.VGA_VB(VGA_VB),
.VGA_DE(VGA_DE)
.VGA_DE(VGA_DE),
.dn_addr(ioctl_addr[13:0]),
.dn_data(ioctl_dout),
.dn_wr(ioctl_wr),
.inputs({btn_coin, btn_start, m_bomb, m_fire, m_right, m_left, m_down, m_up})
);
endmodule

31
verilator/sim_main.cpp
View File

@@ -59,7 +59,7 @@ SimVideo video(VGA_WIDTH, VGA_HEIGHT, VGA_ROTATE);
// ------------------
int initialReset = 48;
bool run_enable = 1;
int batchSize = 2500000 / 100;
int batchSize = 250000 / 100;
bool single_step = 0;
bool multi_step = 0;
int multi_step_amount = 1024;
@@ -176,7 +176,7 @@ int main(int argc, char** argv, char** env) {
// Setup video output
if (video.Initialise(windowTitle) == 1) { return 1; }
//bus.QueueDownload("bird.bin", 0);
bus.QueueDownload("../src/boot_rom.bin", 0);
#ifdef WIN32
@@ -220,7 +220,7 @@ int main(int argc, char** argv, char** env) {
if (ImGui::Button("START")) { run_enable = 1; } ImGui::SameLine();
if (ImGui::Button("STOP")) { run_enable = 0; } ImGui::SameLine();
ImGui::Checkbox("RUN", &run_enable);
ImGui::SliderInt("Batch size", &batchSize, 1, 1000000);
ImGui::SliderInt("Batch size", &batchSize, 1, 100000);
if (single_step == 1) { single_step = 0; }
if (ImGui::Button("Single Step")) { run_enable = 0; single_step = 1; }
@@ -242,15 +242,15 @@ int main(int argc, char** argv, char** env) {
ImGui::Image(video.texture_id, ImVec2(video.output_width * m, video.output_height * m));
ImGui::End();
//ImGui::Begin("ROM Editor");
//mem_edit_1.DrawContents(top->top__DOT__soc__DOT__rom__DOT__mem, 4096, 0);
//ImGui::End();
//ImGui::Begin("RAM Editor");
//mem_edit_2.DrawContents(top->top__DOT__soc__DOT__ram__DOT__mem, 4096, 0);
//ImGui::End();
//ImGui::Begin("VRAM Editor");
//mem_edit_3.DrawContents(top->top__DOT__soc__DOT__vga__DOT__vmem, 16000, 0);
//ImGui::End();
ImGui::Begin("ROM Editor");
mem_edit_1.DrawContents(top->top__DOT__soc__DOT__rom__DOT__mem, 4096, 0);
ImGui::End();
ImGui::Begin("RAM Editor");
mem_edit_2.DrawContents(top->top__DOT__soc__DOT__ram__DOT__mem, 4096, 0);
ImGui::End();
ImGui::Begin("VRAM Editor");
mem_edit_3.DrawContents(top->top__DOT__soc__DOT__video__DOT__vmem, 320*200, 0);
ImGui::End();
ImGui::Begin("CPU Registers");
ImGui::Spacing();
@@ -272,18 +272,17 @@ int main(int argc, char** argv, char** env) {
ImGui::Text("IX 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__IX);
ImGui::Text("IY 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__IY);
ImGui::Text("SP 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__SP);
*//*
ImGui::Text("PC 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__PC);*/
*/
ImGui::End();
video.UpdateTexture();
// Pass inputs to sim
//top->inputs = 0;
top->inputs = 0;
for (int i = 0; i < input.inputCount; i++)
{
//if (input.inputs[i]) { top->inputs |= (1 << i); }
if (input.inputs[i]) { top->inputs |= (1 << i); }
}
// Run simulation

14
verilator/verilate.sh
View File

@@ -1,7 +1,9 @@
verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top sim.v ../rtl/vga.v ../rtl/bram.v ../rtl/soc.v \
#verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top sim.v \
verilator -cc -exe --public --compiler msvc +define+SIMULATION=1 --converge-limit 2000 --top-module top sim.v \
../rtl/video.v ../rtl/dpram.v ../rtl/soc.v \
../rtl/tv80/tv80_core.v \
../rtl/tv80/tv80_alu.v \
../rtl/tv80/tv80_mcode.v \
../rtl/tv80/tv80_reg.v \
../rtl/tv80/tv80n.v \
../rtl/tv80/tv80s.v
../rtl/tv80/tv80_alu.v \
../rtl/tv80/tv80_mcode.v \
../rtl/tv80/tv80_reg.v \
../rtl/tv80/tv80n.v \
../rtl/tv80/tv80s.v